CN1110233C - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1110233C
CN1110233C CN97193991A CN97193991A CN1110233C CN 1110233 C CN1110233 C CN 1110233C CN 97193991 A CN97193991 A CN 97193991A CN 97193991 A CN97193991 A CN 97193991A CN 1110233 C CN1110233 C CN 1110233C
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semiconductor chip
substrate
hole
forms
shield member
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CN1228913A (zh
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中西努
冈本明
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Niigato Precision Co., Ltd.
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Chi Tianyi
Gang Cunjin
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Abstract

本发明的目的在于能将包含在基板上形成的电感器导体的半导体芯片对外部给出的磁影响抑制到最小限度。在基板1上安装包含电感器导体的半导体芯片2，在该安装位置的外侧形成多个通孔8。此外，在基板1的芯片安装面一侧、其相对的面一侧和通孔8的内部形成屏蔽部件4，用该屏蔽部件4从基板1的两面覆盖半导体芯片2。由此，从半导体芯片2中形成的电路发生的磁通在屏蔽部件4的内部循环，不漏出到屏蔽部件4的外部。

Description

半导体装置
发明领域
本发明涉及能进行包含在衬底上形成的电感器导体的半导体芯片的磁屏蔽的半导体装置。
背景技术
一般来说，线圈是重要的电路构成部件，对于所构成的电路可以说是必不可少的部件。例如，利用LC谐振的振荡电路及在收发信号的两用机中包含的调谐电路只有使用线圈才能实现。
但是，由于从上述的电路内包含的线圈发生磁通，故必须进行不因该磁通而使周围的部件受到影响的设计。例如，在印刷布线板上将2个线圈配置成分离开，或在必须将多个线圈接近地配置的情况下，必须考虑磁通的方向想办法进行配置。
图5是在将3个线圈邻接地配置的情况下对其配置方向想了办法后的图。如该图中所示，将各线圈配置成在邻接的线圈之间使线圈的方向相差90度，即，使从邻接的线圈发生的磁通互相垂直。这样，通过使从邻接的各线圈发生的磁通互相垂直，可将各线圈间的磁耦合抑制到最小限度。
但是，如上所述，对线圈的配置方向想办法使得从线圈发生的磁通呈互相垂直，从而将各线圈间的磁耦合抑制到最小限度的现有方式限于在印刷布线板上配置线圈那样的情况。
在半导体衬底上利用薄膜形成技术形成螺旋形状的电感器导体的情况下，磁通的发生方向被限定于相对于半导体衬底的垂直方向。因此，以接近的方式形成的电感器导体的线圈相互间发生磁耦合，在打算作为电路元件使其电分离的情况下是不理想的。特别是在半导体衬底上与各种有源元件一起形成电感器导体等的无源元件的情况下，由于一般是利用半导体制造技术使电路整体实现小型化，故将电路中包含的多个电感器导体配置成充分地分离开是困难的。
图6是用于说明从包含在半导体衬底上形成的电感器导体的半导体电路发生的磁通的状态的图。如果电流流到该图中示出的半导体电路内部的电感器导体中，则如用该图的箭头a所示那样，在与半导体衬底表面大致垂直方向上发生磁通。该磁通使在半导体衬底上形成的其它半导体元件等的工作受到影响，容易成为噪声及误操作的原因。
发明内容
本发明是鉴于这些问题而作出的，其目的在于，提供这样一种半导体装置，该半导体装置能将包含在衬底上形成的电感器导体的半导体芯片对外部给出的磁影响抑制到最小限度。
根据本发明，提供了一种半导体装置，包括：半导体芯片，安装在衬底上并包含电感器导体；多个通孔，在所述半导体芯片的安装位置的外侧的所述衬底中形成；以及屏蔽部件，在所述衬底的所述半导体芯片的安装面一侧和对应于所述半导体芯片的安装位置的所述衬底的背面一侧形成，同时充填所述通孔的内部并覆盖所述半导体芯片，进行所述半导体芯片中形成的电路的磁屏蔽。
优选地，在上述半导体装置中，将键合引线焊在所述半导体芯片上，以所述半导体芯片的安装位置作为基准，在所述衬底上形成的衬底用焊区的外侧形成所述通孔。
优选地，在上述半导体装置中，将键合引线焊在所述半导体芯片上，在所述衬底上形成的衬底用焊区与所述半导体芯片的安装位置之间形成所述通孔。
优选地，在上述半导体装置中，在所述半导体芯片的表面上形成用于保护所述半导体芯片的封装材料，使用导电性或绝缘性的磁性体在所述封装材料的表面上形成所述屏蔽部件。
优选地，在上述半导体装置中，将邻接的所述通孔间的距离定为用所述半导体芯片中形成的电路的工作频率的倒数来表示的波长以下。
优选地，在上述半导体装置中，使用印刷布线板作为所述衬底。
本发明的半导体装置用包含通孔内部并在衬底的两面上形成的屏蔽部件来覆盖安装在衬底上并包含电感器导体的半导体芯片。由此，由于从半导体芯片中形成的电路发生的磁通在屏蔽部件中循环，故磁通不漏到屏蔽部件的外部。
特别是在连接键合引线(bonding wire)的衬底用焊区(pad)的外侧处形成通孔(through hole)的情况下，可由于屏蔽部件覆盖整个键合引线，能可靠地防止键合引线的断线。在衬底用焊区的内侧处形成通孔的情况下，可减小屏蔽部件的外形尺寸，可实现半导体装置整体的小型化。
此外，在衬底上安装半导体芯片时，一般在半导体芯片的表面上形成封装材料，通过在该封装材料的表面上形成屏蔽部件，可原封不动地利用现有的制造工序来进行磁屏蔽。此外，通过将邻接的通孔间的距离定为低于用半导体芯片中形成的电路的工作频率的倒数来表示的波长，可减少通过通孔间漏出的磁通的量。
如以上所述，如果按照本发明，则由于在包含电感器导体的半导体芯片的安装位置的外侧的衬底内形成通孔，在该通孔的内部、衬底的半导体芯片安装面一侧和相对于该安装面的面一侧形成屏蔽部件来覆盖半导体芯片，故从半导体芯片中形成的电路发生的磁通在屏蔽部件的内部循环，这样就没有使外部受到磁的不良影响的担心。
附图说明
图1是第1实施形态的半导体装置的平面图；
图2是图1中示出的A-A线剖面图；
图3是示出图2中示出的半导体芯片附近的磁通的流动的图；
图4是第2实施形态的半导体装置的剖面图；
图5是在邻接地配置3个线圈时对其配置方向想了办法后的图；和
图6是示出从包含衬底上形成的电感器导体的半导体电路发生的磁通的状态的图。
具体实施方式
〔第1实施形态〕
图1是第1实施形态的半导体装置的平面图，图2是图1中示出的A-A线剖面图。如这些图中所示，本实施形态的半导体装置包括：在衬底1上安装的半导体芯片2；用于保护该半导体芯片2的封装材料3；以及在封装材料3的表面上形成的、进行磁屏蔽的屏蔽部件4。作为衬底1，主要使用陶瓷或玻璃环氧衬底等。
图1和图2中示出的半导体芯片2包括：以螺旋形状形成的电感器导体；晶体管及二极管等有源元件；以及电阻及电容器等的无源元件。作为电感器导体的材料，可使用铝或金等金属薄膜、或多晶硅等的半导体材料等。
半导体芯片2或是以已完成的状态安装在图1中示出的衬底1上，或是将衬底1作为衬底、使用蒸镀及离子注入等已知的半导体制造技术来形成。
如图1中所示，在半导体芯片2的表面上形成多个用于与芯片外部进行信号的输入输出的键合焊区5(bonding pad)，将键合引线6分别焊在各键合焊区5上。将这些键合引线6连接到在衬底1上形成的衬底用焊区7上。如图1中所示，在衬底用焊区7的外侧的衬底1上以一定间隔形成了通孔8。
这样来形成封装材料3，使其覆盖半导体芯片2和键合引线6的表面，作为封装材料3的材料，可使用例如环氧树脂等绝缘性材料。为了屏蔽从半导体芯片2中形成的电路发生的磁通而设置屏蔽部件4，该部件在包含通孔8的内部的衬底1的芯片安装面一侧和相对于芯片安装面的面一侧形成。更具体地说，形成芯片安装面一侧的屏蔽部件4a，使其覆盖包含通孔8的半导体芯片2，以大致平面状并包含通孔8来形成相对于芯片安装面的面一侧的屏蔽部件4b。此外，在通孔8的内部也充填屏蔽部件4c，屏蔽部件4从衬底1的两侧覆盖了半导体芯片2。
作为屏蔽部件4的材料，可使用绝缘性或导电性的磁性体，例如可使用γ铁氧体或钡铁氧体等各种磁性体膜。特别是，作为磁记录媒体，一般的γ铁氧体具有在平行于形成γ铁氧体的薄膜的衬底的面方向上排列了微小磁铁那样的磁化方向，在对半导体芯片2内的电感器导体与屏蔽部件4进行磁耦合时是方便的。此外，在使用钡铁氧体的情况下，由于可利用涂敷来形成磁性体膜，故制造变得容易。
此外，关于这些磁性体膜的材料及形成方法，可考虑各种材料及形成方法，例如有以真空蒸镀FeO等来形成磁性体膜的方法、此外还有使用分子束外延法(MBE法)、化学气相生长法(CVD法)、溅射法等来形成磁性体膜的方法等。
图3是示出图2中示出的半导体芯片2附近的磁通的流动的图，是将半导体芯片2附近的剖面扩大后的图。
如该图中所示，利用在衬底1的两面上形成的屏蔽部件4来覆盖半导体芯片2，利用该屏蔽部件4来形成磁路。因而，从电感器导体发生的磁通在大致与半导体芯片2垂直的方向上从衬底1的上表面一侧的屏蔽部件4a通过通孔8的内部的屏蔽部件4c流到下面一侧的屏蔽部件4b，再返回到上表面一侧的屏蔽部件4a。因此，磁通不会漏出到屏蔽部件4的外侧，可将由从半导体芯片2中形成的电路发生的磁通产生的对外部的磁影响抑制到最小限度。
再有，由于以一定间隔在衬底1上形成了通孔8，故存在磁通通过邻接的通孔8之间漏出到外部的担心。因此，最好将通孔8的间隔定为在用半导体芯片2中形成的电路的工作频率的倒数来表示的波长以下。
其次，说明图1中示出的半导体装置的制造工序的概略情况。如以上所述，或是将已完成的半导体芯片2安装在衬底1上，或是在衬底1上利用已知的制造工序形成半导体芯片2。其次，将从半导体芯片2引出的键合引线6连接到衬底1上的衬底用焊区7上后，将液状的封装材料3涂敷在半导体芯片2和键合引线6的周边并进行固化。以上的工序可原封不动地利用现有的制造工序。
其次，在衬底1上的半导体芯片的安装位置的外侧形成通孔8。再有，也可预先在衬底1中形成通孔8。其次，以通孔8的位置作为基准，在封装材料3的表面上蒸镀磁性体膜等，形成屏蔽部件4。此时，在通孔8的内部也充填屏蔽部件4。其次，在衬底1的相对于芯片安装面的面一侧以大致平面状并包含通孔8蒸镀磁性体膜等，完成屏蔽部件4。再有，也可利用环氧树脂等来覆盖屏蔽部件4的表面。
这样，由于第1实施形态的半导体装置在衬底1中形成用于充填屏蔽部件的通孔8，并用屏蔽部件4从衬底1的两面来覆盖半导体芯片2，故可高效率地用屏蔽部件4来屏蔽从半导体芯片2中形成的电路发生的磁通，没有使安装在衬底1上的其它部件受到磁的不良影响的担心。
此外，由于到在衬底1上安装半导体芯片2并用封装材料3进行封装的工序可原封不动地利用现有的制造工序，故可进行磁屏蔽而不大幅度地改变制造工序，可将制造成本的上升抑制到最小限度。
〔第2实施形态〕
第1实施形态说明了在衬底用焊区7的外侧形成通孔8的例子，但也可在半导体芯片2的安装位置与衬底用焊区7之间形成通孔8。
图4是第2实施形态的半导体装置的剖面图。在该图中，对与第1实施形态的半导体装置共同的构成部分附以相同的符号，以下以不同点为中心来说明。
如图4中所示，第2实施形态的通孔8在半导体芯片2的安装位置与衬底用焊区7之间形成。与第1实施形态相同，形成屏蔽部件4使其包含通孔8，键合引线6贯通屏蔽部件4，在屏蔽部件4的外侧与衬底1上的衬底用焊区7连接。用绝缘性的磁性体形成屏蔽部件4，以免键合引线6相互间短路。其它的结构与第1实施形态相同，在利用在衬底1的两面上形成并且也充填通孔8的内部的屏蔽部件4对半导体芯片2进行磁屏蔽这一点上，与第1实施形态也是共同的。
这样，由于第2实施形态的半导体装置在衬底用焊区7与半导体芯片2的安装位置之间形成通孔8，故可比第1实施形态减小屏蔽部件4的外形尺寸，可实现衬底1上的高密度安装。
再有，在上述各实施形态中，说明了在衬底1的芯片安装面一侧、相对于芯片安装面的面一侧和通孔8的内部使用同一种类的磁性体来形成屏蔽部件4，但也可分别使用不同的材料来形成屏蔽部件4。特别是由于通孔8的内部，与芯片安装面及相对于芯片安装面的面相比，磁通密度较高，故也可在通孔8的内部和其以外的部分改变磁性体的种类，以免磁通饱和。
此外，在上述的各实施形态中，说明了除电感器导体以外还包含晶体管等的有源元件的半导体芯片2的例子，但在衬底1上只形成电感器导体的情况下，通过用屏蔽部件4来覆盖电感器导体，可得到与上述各实施形态同样的效果。
此外，在上述的各实施形态中，说明了在半导体芯片2和屏蔽部件4之间形成了封装材料3的例子，但也可省略封装材料3而在半导体芯片上直接形成屏蔽部件，谋求用屏蔽部件来保护半导体芯片。
此外，在上述的各实施形态中，说明了在衬底1上形成半导体芯片2及封装材料3等的例子，但也可使用印刷布线板来代替衬底1，在印刷布线板上安装半导体芯片2，同时在其周围的印刷布线板内形成通孔8，在包含通孔8的印刷布线板的相对的2个面上形成屏蔽部件4。如果能进行这样的COB(板上的芯片)安装，则由于使从包含电感器导体的半导体芯片2发生的磁通不漏出到屏蔽部件的外部，故没有使安装在印刷布线板上的其它部件受到磁的不良影响的担心，可实现印刷布线板的高密度安装。
此外，在上述的各实施形态中，使用了陶瓷或玻璃环氧衬底等作为衬底1，但也可使用由n型硅(n-Si)或其它的半导体材料(例如锗或非晶硅等的非晶质材料)构成的半导体衬底作为衬底1。
此外，在图1中图示了在衬底1中形成了圆形的通孔8的例子，但通孔的形状也可以是除圆形以外的形状(例如矩形)，此外，通孔的尺寸及个数也不限于图1中示出的那样。例如，也可在半导体芯片2的周围形成沟状的通孔。
此外，在上述的各实施形态中，说明了在衬底1上对半导体芯片2用引线键合进行COB安装的情况，但也可将本发明应用于除此以外的安装方法，例如在衬底1上对半导体芯片2进行倒装芯片安装的情况。

Claims (6)

1.一种半导体装置，其特征在于：
包括：
半导体芯片，安装在衬底上并包含电感器导体；
多个通孔，在所述半导体芯片的安装位置的外侧的所述衬底中形成；以及
屏蔽部件，在所述衬底的所述半导体芯片的安装面一侧和对应于所述半导体芯片的安装位置的所述衬底的背面一侧形成，同时充填所述通孔的内部并覆盖所述半导体芯片，
进行所述半导体芯片中形成的电路的磁屏蔽。
2.如权利要求1中所述的半导体装置，其特征在于：
将键合引线焊在所述半导体芯片上，
以所述半导体芯片的安装位置作为基准，在所述衬底上形成的衬底用焊区的外侧形成所述通孔。
3.如权利要求1中所述的半导体装置，其特征在于：
将键合引线焊在所述半导体芯片上，
在所述衬底上形成的衬底用焊区与所述半导体芯片的安装位置之间形成所述通孔。
4.如权利要求1中所述的半导体装置，其特征在于：
在所述半导体芯片的表面上形成用于保护所述半导体芯片的封装材料，
使用导电性或绝缘性的磁性体在所述封装材料的表面上形成所述屏蔽部件。
5.如权利要求1中所述的半导体装置，其特征在于：
将邻接的所述通孔间的距离定为用所述半导体芯片中形成的电路的工作频率的倒数来表示的波长以下。
6.如权利要求1中所述的半导体装置，其特征在于：
使用印刷布线板作为所述衬底。
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EP0897256A1 (en) 1999-02-17
US6097080A (en) 2000-08-01
KR100367069B1 (ko) 2003-03-29
DE69727373D1 (de) 2004-03-04
EP0897256B1 (en) 2004-01-28
KR19990082206A (ko) 1999-11-25
EP0897256A4 (en) 1999-09-15
DE69727373T2 (de) 2004-12-09
CN1228913A (zh) 1999-09-15
WO1997040654A1 (fr) 1997-10-30

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