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Semiconductor device

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Publication number
WO1997040654A1
WO1997040654A1 PCT/JP1997/001412 JP9701412W WO1997040654A1 WO 1997040654 A1 WO1997040654 A1 WO 1997040654A1 JP 9701412 W JP9701412 W JP 9701412W WO 1997040654 A1 WO1997040654 A1 WO 1997040654A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
chip
formed
board
semiconductor
members
Prior art date
Application number
PCT/JP1997/001412
Other languages
English (en)
French (fr)
Inventor
Tsutomu Nakanishi
Akira Okamoto
Original Assignee
Okamura, Susumu
Ikeda, Takeshi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01014Silicon [Si]
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    • H01L2924/097Glass-ceramics, e.g. devitrified glass
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    • H01L2924/3025Electromagnetic shielding
PCT/JP1997/001412 1996-04-24 1997-04-23 Semiconductor device WO1997040654A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8/127783 1996-04-24
JP12778396 1996-04-24

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09171455 US6097080A (en) 1996-04-24 1997-04-23 Semiconductor device having magnetic shield layer circumscribing the device
DE1997627373 DE69727373D1 (de) 1996-04-24 1997-04-23 Halbleitervorrichtung
DE1997627373 DE69727373T2 (de) 1996-04-24 1997-04-23 Halbleitervorrichtung
EP19970919662 EP0897256B1 (en) 1996-04-24 1997-04-23 Semiconductor device

Publications (1)

Publication Number Publication Date
WO1997040654A1 true true WO1997040654A1 (en) 1997-10-30

Family

ID=14968579

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/001412 WO1997040654A1 (en) 1996-04-24 1997-04-23 Semiconductor device

Country Status (6)

Country Link
US (1) US6097080A (ja)
KR (1) KR100367069B1 (ja)
CN (1) CN1110233C (ja)
DE (2) DE69727373D1 (ja)
EP (1) EP0897256B1 (ja)
WO (1) WO1997040654A1 (ja)

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US7525758B2 (en) 2005-06-30 2009-04-28 Kabushiki Kaisha Toshiba Disk drive with non-magnetic cover and base plated with conductively connected magnetic shielding layers
WO2011046091A1 (ja) * 2009-10-13 2011-04-21 日本電気株式会社 磁性体装置

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US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US20080035974A1 (en) * 1998-12-21 2008-02-14 Megica Corporation High performance system-on-chip using post passivation process
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US20070108551A1 (en) * 2003-05-27 2007-05-17 Megica Corporation High performance system-on-chip inductor using post passivation process
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
EP1179872A4 (en) * 1999-03-24 2007-06-06 Rohm Co Ltd Circuit module for protecting a rechargeable battery and method of manufacture thereof
US20020030257A1 (en) * 1999-06-18 2002-03-14 Joseph M. Brand Semiconductor device utiling an encapsulant for locking a semiconductor die to circuit substrate
US6414383B1 (en) * 1999-07-16 2002-07-02 Agere Systems Guardian Corp. Very low magnetic field integrated circuit
JP4398056B2 (ja) * 2000-04-04 2010-01-13 Necトーキン株式会社 樹脂モールド体
JP3781610B2 (ja) * 2000-06-28 2006-05-31 株式会社東芝 半導体装置
US6452253B1 (en) * 2000-08-31 2002-09-17 Micron Technology, Inc. Method and apparatus for magnetic shielding of an integrated circuit
US6515352B1 (en) * 2000-09-25 2003-02-04 Micron Technology, Inc. Shielding arrangement to protect a circuit from stray magnetic fields
DE10057918A1 (de) * 2000-11-21 2002-06-06 Kerafol Keramische Folien Gmbh Ferritfolie
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
JP2003124538A (ja) * 2001-10-16 2003-04-25 Sony Corp 情報記憶装置およびその情報記憶装置を実装した電子機器
US6906396B2 (en) * 2002-01-15 2005-06-14 Micron Technology, Inc. Magnetic shield for integrated circuit packaging
JP2004064052A (ja) * 2002-07-27 2004-02-26 Samsung Electro Mech Co Ltd ノイズ遮蔽型積層基板とその製造方法
US7382043B2 (en) 2002-09-25 2008-06-03 Maxwell Technologies, Inc. Method and apparatus for shielding an integrated circuit from radiation
US7191516B2 (en) 2003-07-16 2007-03-20 Maxwell Technologies, Inc. Method for shielding integrated circuit devices
DE10343362B4 (de) * 2003-09-15 2005-09-22 Institut für Maschinen, Antriebe und elektronische Gerätetechnik gGmbH - IMG Verfahren zur Herstellung einer Leiterplatte mit verbessertem EMV-Verhalten
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
CN1901163B (zh) 2005-07-22 2011-04-13 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
US7968978B2 (en) * 2007-06-14 2011-06-28 Raytheon Company Microwave integrated circuit package and method for forming such package
US8466539B2 (en) * 2011-02-23 2013-06-18 Freescale Semiconductor Inc. MRAM device and method of assembling same
CN102760667B (zh) * 2011-04-29 2014-10-29 力成科技股份有限公司 形成双面电磁屏蔽层的半导体封装方法及构造
JP5829562B2 (ja) * 2012-03-28 2015-12-09 ルネサスエレクトロニクス株式会社 半導体装置
CN105493267A (zh) * 2013-09-04 2016-04-13 株式会社东芝 半导体装置及其制造方法

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7372057B2 (en) 2004-08-31 2008-05-13 Xtreme Technologies Gmbh Arrangement for providing a reproducible target flow for the energy beam-induced generation of short-wavelength electromagnetic radiation
US7525758B2 (en) 2005-06-30 2009-04-28 Kabushiki Kaisha Toshiba Disk drive with non-magnetic cover and base plated with conductively connected magnetic shielding layers
WO2011046091A1 (ja) * 2009-10-13 2011-04-21 日本電気株式会社 磁性体装置
JPWO2011046091A1 (ja) * 2009-10-13 2013-03-07 日本電気株式会社 磁性体装置

Also Published As

Publication number Publication date Type
KR100367069B1 (ko) 2003-03-29 grant
EP0897256A1 (en) 1999-02-17 application
EP0897256A4 (en) 1999-09-15 application
DE69727373D1 (de) 2004-03-04 grant
EP0897256B1 (en) 2004-01-28 grant
US6097080A (en) 2000-08-01 grant
CN1110233C (zh) 2003-05-28 grant
DE69727373T2 (de) 2004-12-09 grant
CN1228913A (zh) 1999-09-15 application

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