CN110060998B - 一种反相电路结构、栅极驱动电路及显示面板 - Google Patents

一种反相电路结构、栅极驱动电路及显示面板 Download PDF

Info

Publication number
CN110060998B
CN110060998B CN201910357148.3A CN201910357148A CN110060998B CN 110060998 B CN110060998 B CN 110060998B CN 201910357148 A CN201910357148 A CN 201910357148A CN 110060998 B CN110060998 B CN 110060998B
Authority
CN
China
Prior art keywords
pole
active layer
layer
nmos transistor
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910357148.3A
Other languages
English (en)
Other versions
CN110060998A (zh
Inventor
李杰良
许玉萍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xiamen Tianma Microelectronics Co Ltd
Original Assignee
Xiamen Tianma Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiamen Tianma Microelectronics Co Ltd filed Critical Xiamen Tianma Microelectronics Co Ltd
Priority to CN201910357148.3A priority Critical patent/CN110060998B/zh
Publication of CN110060998A publication Critical patent/CN110060998A/zh
Priority to US16/726,260 priority patent/US11508761B2/en
Application granted granted Critical
Publication of CN110060998B publication Critical patent/CN110060998B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明实施例公开一种反相电路结构、栅极驱动电路及显示面板。该反相电路结构至少包括一PMOS晶体管和一NMOS晶体管，包括依次层叠的第一有源层、栅极层和第二有源层，栅极层与第一有源层之间设有第一绝缘层，栅极层和第二有源层之间设有第二绝缘层；栅极层包括图形化的栅极，栅极与控制输入端电连接；栅极在第一有源层的正投影为第一区域，第一区域内的部分具有相同的厚度；栅极在第二有源层的正投影为第二区域，第二区域内的部分具有相同的厚度；PMOS的第一极与第一电压输入端电连接，第二极与输出端电连接；NMOS的第一极与第二电压输入端电连接，第二极与输出端电连接。本发明实施例可减小反相器占用面积，并消除hump现象。

Description

一种反相电路结构、栅极驱动电路及显示面板
技术领域
本发明实施例涉及显示技术，尤其涉及一种反相电路结构、栅极驱动电路及显示面板。
背景技术
互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)反相器由一个P沟道晶体管(PMOS)和一个N沟道晶体管(NMOS)串联组成。图1所示为一种CMOS反相器的等效电路图，该CMOS反相器包括控制输入端IN、输出端OUT、第一电压输入端VGH和第二电压输入端VGL，其中PMOS的栅极和NMOS的栅极都与控制输入端IN电连接，PMOS的漏极和NMOS的漏极都与输出端OUT电连接。PMOS的开启电压VGS(th)P<0，NMOS的开启电压VGS(th)N>0，通常为了保证正常工作，要求VGH>|VGS(th)P|+VGS(th)N。若输入端IN为低电平(如-7V)，则PMOS导通，NMOS截止，输出电压接近VGH。若输入端IN为高电平(如VGH)，则NMOS导通，PMOS截止，输出电压接近VGL。
现有技术中，PMOS和NMOS一般为平面结构，需要占用较大面积；且栅极一般设计为线状，图2所示为现有技术中的CMOS反相器中的PMOS/NMOS的部分结构示意图，图3所示为现有技术中的CMOS反相器的电压-电流(V-I)特性示意图。图2中示出了栅极1，绝缘层2和有源层3，由于有源层3包括主沟道区a和两侧斜坡的子沟道区b，图3中曲线I1为主沟道区a的V-I曲线，曲线I2为子沟道区b的V-I曲线，当栅极1施加相同的电压时，主沟道区a和子沟道区b的电流不同，会导致V-I曲线不平滑，即出现驼峰(hump)现象(I3)。
发明内容
本发明实施例提供一种反相电路结构、栅极驱动电路及显示面板，可以有效减小反相器的占用面积，且消除hump现象。
第一方面，本发明实施例提供一种反相电路结构，至少包括一个PMOS晶体管和一个NMOS晶体管，所述反相电路结构包括依次层叠设置的第一有源层、栅极层和第二有源层，所述栅极层与所述第一有源层之间设置有第一绝缘层，以及所述栅极层和所述第二有源层之间设置有第二绝缘层；
所述栅极层包括图形化的栅极，所述栅极与控制输入端电连接；
所述栅极在所述第一有源层的正投影为第一区域，所述第一有源层的位于所述第一区域内的部分具有相同的厚度；所述栅极在所述第二有源层的正投影为第二区域，所述第二有源层的位于所述第二区域内的部分具有相同的厚度；
所述PMOS晶体管的第一极与第一电压输入端电连接，第二极与输出端电连接；所述NMOS晶体管的第一极与第二电压输入端电连接，第二极与所述输出端电连接。
第二方面，本发明实施例还提供一种栅极驱动电路，包括至少一个上述的反相电路结构。
第三方面，本发明实施例还提供一种显示面板，包括上述的栅极驱动电路。
本发明实施例提供的反相电路结构，至少包括一个PMOS晶体管和一个NMOS晶体管，该反相电路结构包括依次层叠设置的第一有源层、栅极层和第二有源层，栅极层与第一有源层之间设置有第一绝缘层，以及栅极层和第二有源层之间设置有第二绝缘层；栅极层包括图形化的栅极，栅极与控制输入端电连接；栅极在第一有源层的正投影为第一区域，第一有源层的位于第一区域内的部分具有相同的厚度；栅极在第二有源层的正投影为第二区域，第二有源层的位于第二区域内的部分具有相同的厚度；PMOS晶体管的第一极与第一电压输入端电连接，第二极与输出端电连接；NMOS晶体管的第一极与第二电压输入端电连接，第二极与输出端电连接。通过将第一有源层、栅极层和第二有源层层叠设置，形成立体型反相电路结构，相对于平面型反相电路结构，可以有效减小反相电路的占用面积，用于显示面板的驱动电路时可以有效减小显示面板边框；通过设计图形化的栅极结构，有助于增加晶体管沟道的宽长比，提高晶体管的性能；通过设置第一区域内的第一有源层具有相同的厚度，第二区域内的第二有源层具有相同的厚度，可以避免晶体管的沟道区产生子沟道，从而避免V-I曲线不平滑，消除hump现象。
附图说明
图1为一种CMOS反相器的等效电路图；
图2为现有技术中的CMOS反相器中的PMOS/NMOS的部分结构示意图；
图3为现有技术中的CMOS反相器的电压-电流(V-I)特性示意图；
图4为本发明实施例提供的一种反相电路结构示意图；
图5为图4沿剖线A-A′的一种剖面结构示意图；
图6为图4沿剖线B-B′的一种剖面结构示意图；
图7为本发明实施例提供的另一种反相电路结构示意图；
图8为图7沿剖线C-C′的一种剖面结构示意图；
图9为图7沿剖线D-D′的一种剖面结构示意图；
图10为图7沿剖线C-C′的另一种剖面结构示意图；
图11为是图7沿剖线D-D′的另一种剖面结构示意图；
图12为图7沿剖线C-C′的又一种剖面结构示意图；
图13为图7沿剖线D-D′的又一种剖面结构示意图；
图14为图7沿剖线D-D′的又一种剖面结构示意图；
图15为图7沿剖线C-C′的又一种剖面结构示意图；
图16为图7沿剖线D-D′的又一种剖面结构示意图；
图17为图7沿剖线D-D′的又一种剖面结构示意图；
图18为本发明实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
在本发明实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本发明。需要注意的是，本发明实施例所描述的“上”、“下”、“左”、“右”等方位词是以附图所示的角度来进行描述的，不应理解为对本发明实施例的限定。此外在上下文中，还需要理解的是，当提到一个元件被形成在另一个元件“上”或“下”时，其不仅能够直接形成在另一个元件“上”或者“下”，也可以通过中间元件间接形成在另一元件“上”或者“下”。术语“第一”、“第二”等仅用于描述目的，并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
本发明实施例提供一种反相电路结构，至少包括一个PMOS晶体管和一个NMOS晶体管，该反相电路结构包括依次层叠设置的第一有源层、栅极层和第二有源层，栅极层与第一有源层之间设置有第一绝缘层，以及栅极层和第二有源层之间设置有第二绝缘层；栅极层包括图形化的栅极，栅极与控制输入端电连接；栅极在第一有源层的正投影为第一区域，第一有源层的位于第一区域内的部分具有相同的厚度；栅极在第二有源层的正投影为第二区域，第二有源层的位于第二区域内的部分具有相同的厚度；PMOS晶体管的第一极与第一电压输入端电连接，第二极与输出端电连接；NMOS晶体管的第一极与第二电压输入端电连接，第二极与输出端电连接。
示例性的，图4所示为本发明实施例提供的一种反相电路结构示意图，图5是图4沿剖线A-A′的一种剖面结构示意图，图6是图4沿剖线B-B′的一种剖面结构示意图。参考图4～图6，本实施例提供的反相电路结构包括一个PMOS晶体管10和一个NMOS晶体管20，反相电路结构包括依次层叠设置的第一有源层13、栅极层11和第二有源层23，栅极层11与第一有源层13之间设置有第一绝缘层12，以及栅极层11和第二有源层23之间设置有第二绝缘层22，第一绝缘层12和第二绝缘层22都可以由硅氧化物(SiOx)形成；栅极层11包括图形化的栅极111，栅极111与控制输入端(图4中未示出)电连接；栅极111在第一有源层13的正投影为第一区域c，第一有源层13的位于第一区域c内的部分具有相同的厚度；栅极111在第二有源层23的正投影为第二区域d，第二有源层23的位于第二区域d内的部分具有相同的厚度；PMOS晶体管10的第一极14与第一电压输入端(图4中未示出)电连接，第二极15与输出端(图4中未示出)电连接；NMOS晶体管20的第一极24与第二电压输入端(图4中未示出)电连接，第二极25与输出端(图4中未示出)电连接。
可以理解的是，在本实施例中，PMOS晶体管10和NMOS晶体管20共用栅极111，示例性的，PMOS晶体管10对应第一有源层13，NMOS晶体管20对应第二有源层23，PMOS晶体管10设置在NMOS晶体管20下方，在其他实施例中，PMOS晶体管10也可以设置在NMOS晶体管20上方，对应图1所示的等效电路图，栅极111与控制输入端IN电连接，PMOS晶体管10的第一极14为源极，与第一电压输入端VGH电连接，第二极14为漏极，与输出端OUT电连接，NMOS晶体管20的第一极24为源极，与第二电压输入端VGL电连接，第二极25为漏极，与输出端OUT电连接。栅极111为图形化结构，例如图4中所示栅极111的边缘为矩形的环状图形，可以有效增加晶体管沟道的宽长比。
本发明实施例的技术方案，通过将第一有源层、栅极层和第二有源层层叠设置，形成立体型反相电路结构，相对于平面型反相电路结构，可以有效减小反相电路的占用面积，用于显示面板的驱动电路时可以有效减小显示面板边框。可以理解的是，平面型的反相电路结构中，两个晶体管的栅极输入信号相同，因此需要先设计连接走线，将两个晶体管的栅极电连接到一起，再接入相同的输入端，此外，两个晶体管的输出信号也需要设计额外信号走线电连接到相同的输出端，而本发明实施例中的立体型反相电路结构中，两个TFT共用栅极层，栅极信号端连接在一起，两个TFT输出端也可以复用相同的电极，因此简化了反相电路结构中的信号走线设计。进一步的，通过将栅极设置在两个有源层之间，形成立体的电路结构，以及设计图形化的栅极结构，例如包括多个条状子栅极结构，使得实现相同的沟道宽长比占用的面积减小，即相同的占用面积下，立体型的反相电路结构会有更大的宽长比，有利于提高晶体管的性能。本发明的实施例中，两个有源层为整面设计，将栅极设置于两个有源层之间，得到立体型的反相电路结构，相对于平面型反相电路结构中每个有源层的面积可以更大，此外通过设计图案化的栅极，使栅极对应的有源层具有相同的厚度，可以避免有源层和栅极之间存在的斜坡区域，从而避免了晶体管的沟道区产生子沟道，从而避免V-I曲线不平滑，消除hump现象。
在上述实施例的基础上，可选的，图形化的栅极包括至少两个条状子栅极，至少两个条状子栅极通过至少一个公共端电连接。
可选的，条状子栅极构成环状图形。
继续参考图4，可以理解的是，将条状子栅极设计为环状，可以在B-B′的延伸方向上也设置导电沟道，进一步增加沟道区的宽长比，将条状子栅极背离控制输入端的一侧电连接，还可以保证栅极的电位均衡，均匀沟道区电场，进而提升器件性能。
可选的，环状图形的外侧边缘为四边形。
可以理解的是，图形化栅极外侧边缘的形状可以为正方形、矩形、平行四边形、梯形的形状，具体实施时可以根据实际条件选择，图4中示意性的示出环状图形为矩形。
示例性的，图7所示为本发明实施例提供的另一种反相电路结构示意图。参考图7，图形化的栅极111包括条状子栅极111a和条状子栅极111b，两个条状子栅极通过一个公共端111c电连接。
需要说明的是，图7中的栅极形状只是示意性的，具体实施时可以根据实际需求设计条状子栅极的形状和数量，例如形状可以为折线形，网格状等，本发明实施例对此不作限定。通过设置栅极为条状子栅极，可以在相同的器件占用面积的条件下增大沟道区的宽长比，提升晶体管的性能。
可选的，沿第一方向，PMOS晶体管的第二极和NMOS晶体管的第二极位于两个条状子栅极之间；第一方向垂直于条状子栅极的延伸方向。
示例性的，图8是图7沿剖线C-C′的一种剖面结构示意图，图9是图7沿剖线D-D′的一种剖面结构示意图。参考图7～图9，沿第一方向x，PMOS晶体管10的第二极15和NMOS晶体管20的第二极25位于条状子栅极111a和条状子栅极111b之间；第一方向x垂直于条状子栅极111a/111b的延伸方向y。
可选的，继续参考图8和图9，PMOS晶体管10的第二极15复用为NMOS晶体管20的第二极25，NMOS晶体管20的第二极25与第二有源层23电连接，同时，NMOS晶体管20的第二极25通过依次贯穿第二有源层23、第二绝缘层22和第一绝缘层12的通孔与第一有源层13电连接；或者，图10是图7沿剖线C-C′的另一种剖面结构示意图，图11是图7沿剖线D-D′的另一种剖面结构示意图，NMOS晶体管20的第二极25复用为PMOS晶体管10的第二极15，PMOS晶体管10的第二极15与第一有源层13电连接，同时，PMOS晶体管10的第二极15通过依次贯穿第一有源层13、第一绝缘层12和第二绝缘层22的通孔与第二有源层23电连接。通过PMOS晶体管10的第二极15复用为NMOS晶体管20的第二极25，可以在一个工艺流程中形成两个电极，简化反相电路结构，有助于降低工艺难度，降低制作成本。
可以理解的是，图8和图10所示的反相电路结构的差别在于PMOS晶体管10和NMOS晶体管20的层叠方式相反，具体实施时，可以根据实际工艺条件进行选择，本发明实施例对PMOS晶体管10和NMOS晶体管20的层叠方式不作限定。
可选的，第一有源层包括多晶硅有源层，第二有源层包括氧化物有源层。
可以理解的是，本发明实施例中，第一有源层可以利用低温多晶硅(LTPS)通过在源区和漏区进行P型高掺杂，从而在导通时形成P型导电沟道，作为PMOS晶体管的有源层；第二有源层可以利用锌(Zn)、铟(In)、锡(Sn)、镓(Ga)和铝(Al)等元素中至少一种元素的氧化物或者硫氧化物作为NMOS晶体管的有源层，由于本实施例中NMOS晶体管的利用氧化物有源层，因此制作时无需进行N型高掺杂，可以简化工艺，降低制作成本。
图12是图7沿剖线C-C′的又一种剖面结构示意图，图13是图7沿剖线D-D′的又一种剖面结构示意图，参考图12和图13，可选的，本实施例提供的反相电路结构还包括：衬底30，第一有源层13位于栅极层11靠近衬底30的一侧；第三绝缘层32，PMOS晶体管10的第一极14、PMOS晶体管10的第二极15、NMOS晶体管20的第一极24以及NMOS晶体管20的第二极25均位于第三绝缘层32远离第二有源层23的一侧；PMOS晶体管10的第一极14通过依次贯穿第三绝缘层32、第二绝缘层22和第一绝缘层11的第一通孔40与第一有源层13电连接，PMOS晶体管10的第二极15通过依次贯穿第三绝缘层32、第二绝缘层22和第一绝缘层12的第二通孔41与第一有源层13电连接；NMOS晶体管20的第一极24通过第三绝缘层32的第三通孔42与第二有源层23电连接，NMOS晶体管20的第二极25通过第三绝缘层32的第四通孔43与第二有源层23电连接；第二有源层23为图形化结构，暴露出第一通孔40和第二通孔41所在的区域。
可以理解的是，图12和图13所示的反相电路结构为PMOS晶体管10位于NMOS晶体管20下方，其中第三绝缘层32可以与第一绝缘层12和第二绝缘层22采用相同的材料，例如硅氧化物(SiOx)，第一通孔40和第二通孔41可以在形成第三绝缘层32之后依次贯穿三个绝缘层形成，且第二有源层23预留暴露出第一通孔40和第二通孔41所在的区域图形化结构，然后注入与相应电极的金属材料形成电极，第三通孔42、第四通孔43可以在形成第三绝缘层32之后贯穿第三绝缘层32形成。
图14是图7沿剖线D-D′的又一种剖面结构示意图，参考图14，可选的，PMOS晶体管的第一极14和NMOS晶体管的第一极24同层设置，PMOS晶体管的第二极15和NMOS晶体管的第二极25同层设置；NMOS晶体管的第一极24与第二有源层23之间的距离和NMOS晶体管的第二极25与第二有源层23之间的距离不同。
可以理解的是，图14中示例性的示出NMOS晶体管20的第一极24与第二有源层23之间的距离d1小于NMOS晶体管20的第二极25与第二有源层23之间的距离d2，在其他实施例中，还可以设置NMOS晶体管20的第一极24与第二有源层23之间的距离大于NMOS晶体管20的第二极25与第二有源层23之间的距离，通过设置晶体管的第一极和第二极位于不同层，可以提高器件膜层设置的灵活性，例如可以将晶体管的第一极和第二极在衬底上的垂直投影重合，从而减小反相电路结构的占用面积。
图15是图7沿剖线C-C′的又一种剖面结构示意图，图16是图7沿剖线D-D′的又一种剖面结构示意图，参考图15和图16，可选的，本实施例提供的反相电路结构还包括：衬底30，第二有源层23位于栅极层11靠近衬底30的一侧；第四绝缘层33，PMOS晶体管10的第一极14、PMOS晶体管10的第二极15、NMOS晶体管20的第一极24以及NMOS晶体管20的第二极25均位于第四绝缘层33远离第一有源层13的一侧；NMOS晶体管20的第一极24通过依次贯穿第四绝缘层33、第一绝缘层12和第二绝缘层22的第五通孔44与第二有源层23电连接，NMOS晶体管20的第二极25通过依次贯穿第四绝缘层33、第一绝缘层12和第二绝缘层22的第六通孔45与第二有源层23电连接；PMOS晶体管10的第一极14通过第四绝缘层33的第七通孔46与第一有源层13电连接，PMOS晶体管10的第二极15通过第四绝缘层33的第八通孔47与第一有源层13电连接；第一有源层13为图形化结构，暴露出第五通孔44和第六通孔45所在的区域。
可以理解的是，本实施例与图12和图13所示的实施例不同之处在于PMOS晶体管10位于NMOS晶体管20上方。当PMOS晶体管10位于NMOS晶体管20上方时，可以适当增加第一绝缘层12与第二绝缘层22的厚度，以避免形成第一有源层13时由于温度等原因造成第二有源层23的损伤。
图17是图7沿剖线D-D′的又一种剖面结构示意图，参考图17，可选的，PMOS晶体管的第一极14和NMOS晶体管的第一极24同层设置，PMOS晶体管的第二极15和NMOS晶体管的第二极25同层设置；NMOS晶体管的第一极24与第一有源层13的距离和NMOS晶体管的第二极25与第一有源层13的距离不同。
可以理解的是，图17中示例性的示出NMOS晶体管的第一极24与第一有源层13之间的距离d3小于NMOS晶体管的第二极25与第一有源层13之间的距离d4，在其他实施例中，还可以设置NMOS晶体管的第一极24与第一有源层13之间的距离大于NMOS晶体管的第二极25与第一有源层13之间的距离，通过设置晶体管的第一极和第二极位于不同层，可以提高器件膜层设置的灵活性，例如可以将晶体管的第一极和第二极在衬底上的垂直投影重合，从而减小反相电路结构的面积。
可选的，继续参考图12、图13或图15、图16，PMOS晶体管10的第一极14、NMOS晶体管20的第一极24、PMOS晶体管10的第二极15以及NMOS晶体管20的第二极25同层设置。
可以理解的是，PMOS晶体管10的第一极14和第二极15、NMOS晶体管20的第一极24和第二极25同层设置时，所有电极都可以采用同一工艺一次形成，有助于简化工艺流程，提高制作效率，降低成本。
本发明实施例还提供一种栅极驱动电路，包括至少一个上述实施例提供的任意一种反相电路结构。本发明实施例提供的栅极驱动电路可以用于显示面板中，例如可以为包括薄膜晶体管的液晶显示面板或有机发光显示面板，反相电路与显示面板上的薄膜晶体管的栅极电连接，用于控制薄膜晶体管打开或关闭。示例性的，图18所示为本发明实施例提供的一种显示面板的结构示意图，该显示面板包括显示区100和围绕显示区的边框区200。由于栅极驱动电路300一般设置于显示面板的边框区200，本发明实施例提供的反相电路结构相对于现有的平面结构面积更小，可以有效降低栅极驱动电路占有显示面板的宽度，实现显示面板的窄边框，提高显示面板的屏占比。
本发明实施例还提供一种显示面板，包括上述实施例提供的栅极驱动电路。该显示面板可以用于手机、电脑以及智能可穿戴设备等显示装置中。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (12)

1.一种反相电路结构，其特征在于，至少包括一个PMOS晶体管和一个NMOS晶体管，所述PMOS晶体管的面积与所述NMOS晶体管的面积相同，所述反相电路结构包括依次层叠设置的第一有源层、栅极层和第二有源层，所述栅极层与所述第一有源层之间设置有第一绝缘层，以及所述栅极层和所述第二有源层之间设置有第二绝缘层，所述栅极层完全位于所述PMOS晶体管和所述NMOS晶体管所在区域内；
所述栅极层包括图形化的栅极，所述栅极与控制输入端电连接，所述图形化的栅极包括至少两个条状子栅极，至少两个所述条状子栅极通过至少一个公共端电连接；
所述栅极在所述第一有源层的正投影为第一区域，所述第一有源层的位于所述第一区域内的部分具有相同的厚度；所述栅极在所述第二有源层的正投影为第二区域，所述第二有源层的位于所述第二区域内的部分具有相同的厚度；
所述PMOS晶体管的第一极与第一电压输入端电连接，第二极与输出端电连接；所述NMOS晶体管的第一极与第二电压输入端电连接，第二极与所述输出端电连接；
所述第一有源层包括多晶硅有源层，所述第二有源层包括氧化物有源层；
所述NMOS晶体管的第一极与所述第一有源层之间的距离和所述NMOS晶体管的第二极与所述第一有源层之间的距离不同，其中二者距离不同通过同一绝缘层在不同区域设置不同的厚度实现。
2.根据权利要求1所述的反相电路结构，其特征在于，沿第一方向，所述PMOS晶体管的第二极和所述NMOS晶体管的第二极位于两个所述条状子栅极之间；所述第一方向垂直于所述条状子栅极的延伸方向。
3.根据权利要求2所述的反相电路结构，其特征在于，所述PMOS晶体管的第二极复用为所述NMOS晶体管的第二极，所述NMOS晶体管的第二极与所述第二有源层电连接，同时，所述NMOS晶体管的第二极通过依次贯穿所述第二有源层、所述第二绝缘层和所述第一绝缘层的通孔与所述第一有源层电连接；或者，
所述NMOS晶体管的第二极复用为所述PMOS晶体管的第二极，所述PMOS晶体管的第二极与所述第一有源层电连接，同时，所述PMOS晶体管的第二极通过依次贯穿所述第一有源层、所述第一绝缘层和所述第二绝缘层的通孔与所述第二有源层电连接。
4.根据权利要求1所述的反相电路结构，其特征在于，所述条状子栅极构成环状图形。
5.根据权利要求4所述的反相电路结构，其特征在于，所述环状图形的外侧边缘为四边形。
6.根据权利要求1所述的反相电路结构，其特征在于，还包括：
衬底，所述第一有源层位于所述栅极层靠近所述衬底的一侧；
第三绝缘层，所述PMOS晶体管的第一极、所述PMOS晶体管的第二极、所述NMOS晶体管的第一极以及所述NMOS晶体管的第二极均位于所述第三绝缘层远离所述第二有源层的一侧；
所述PMOS晶体管的第一极通过依次贯穿所述第三绝缘层、所述第二绝缘层和所述第一绝缘层的第一通孔与所述第一有源层电连接，所述PMOS晶体管的第二极通过依次贯穿所述第三绝缘层、所述第二绝缘层和所述第一绝缘层的第二通孔与所述第一有源层电连接；
所述NMOS晶体管的第一极通过所述第三绝缘层的第三通孔与所述第二有源层电连接，所述NMOS晶体管的第二极通过所述第三绝缘层的第四通孔与所述第二有源层电连接；
所述第二有源层为图形化结构，暴露出所述第一通孔和所述第二通孔所在的区域。
7.据权利要求6所述的反相电路结构，其特征在于，所述PMOS晶体管的第一极和所述NMOS晶体管的第一极同层设置，所述PMOS晶体管的第二极和所述NMOS晶体管的第二极同层设置。
8.根据权利要求1所述的反相电路结构，其特征在于，还包括：
衬底，所述第二有源层位于所述栅极层靠近所述衬底的一侧；
第四绝缘层，所述PMOS晶体管的第一极、所述PMOS晶体管的第二极、所述NMOS晶体管的第一极以及所述NMOS晶体管的第二极均位于所述第四绝缘层远离所述第一有源层的一侧；
所述NMOS晶体管的第一极通过依次贯穿所述第四绝缘层、所述第一绝缘层和所述第二绝缘层的第五通孔与所述第二有源层电连接，所述NMOS晶体管的第二极通过依次贯穿所述第四绝缘层、所述第一绝缘层和所述第二绝缘层的第六通孔与所述第二有源层电连接；
所述PMOS晶体管的第一极通过所述第四绝缘层的第七通孔与所述第一有源层电连接，所述PMOS晶体管的第二极通过所述第四绝缘层的第八通孔与所述第一有源层电连接；
所述第一有源层为图形化结构，暴露出所述第五通孔和所述第六通孔所在的区域。
9.根据权利要求8所述的反相电路结构，其特征在于，所述PMOS晶体管的第一极和所述NMOS晶体管的第一极同层设置，所述PMOS晶体管的第二极和所述NMOS晶体管的第二极同层设置。
10.根据权利要求6或8所述的反相电路结构，其特征在于，所述PMOS晶体管的第一极、所述NMOS晶体管的第一极、所述PMOS晶体管的第二极以及所述NMOS晶体管的第二极同层设置。
11.一种栅极驱动电路，其特征在于，包括至少一个如权利要求1～10任一项所述的反相电路结构。
12.一种显示面板，其特征在于，包括权利要求11所述的栅极驱动电路。
CN201910357148.3A 2019-04-29 2019-04-29 一种反相电路结构、栅极驱动电路及显示面板 Active CN110060998B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201910357148.3A CN110060998B (zh) 2019-04-29 2019-04-29 一种反相电路结构、栅极驱动电路及显示面板
US16/726,260 US11508761B2 (en) 2019-04-29 2019-12-24 Inverter circuit structure, gate driving circuit and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910357148.3A CN110060998B (zh) 2019-04-29 2019-04-29 一种反相电路结构、栅极驱动电路及显示面板

Publications (2)

Publication Number Publication Date
CN110060998A CN110060998A (zh) 2019-07-26
CN110060998B true CN110060998B (zh) 2022-05-17

Family

ID=67321559

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910357148.3A Active CN110060998B (zh) 2019-04-29 2019-04-29 一种反相电路结构、栅极驱动电路及显示面板

Country Status (2)

Country Link
US (1) US11508761B2 (zh)
CN (1) CN110060998B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117642866A (zh) * 2022-06-29 2024-03-01 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202758893U (zh) * 2012-08-03 2013-02-27 成都国微电子有限公司 一种晶体管版图结构及芯片版图结构

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727517B2 (en) * 2001-09-28 2004-04-27 The Hong Kong University Of Science And Technology Three dimensional integrated circuits
JP2005354023A (ja) * 2004-05-14 2005-12-22 Seiko Epson Corp 半導体装置および半導体装置の製造方法
KR100665848B1 (ko) * 2005-03-21 2007-01-09 삼성전자주식회사 적층 타입 디커플링 커패시터를 갖는 반도체 장치
JP2006269665A (ja) * 2005-03-23 2006-10-05 Lg Phillips Lcd Co Ltd 薄膜トランジスタ回路とその製造方法
US7646063B1 (en) * 2005-06-15 2010-01-12 Pmc-Sierra, Inc. Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions
KR101243890B1 (ko) * 2006-04-10 2013-03-20 삼성전자주식회사 유효 채널 길이를 증가시키기 위한 ｃｍｏｓ 인버터 레이아웃
US8049253B2 (en) * 2007-07-11 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR100989136B1 (ko) * 2008-04-11 2010-10-20 삼성모바일디스플레이주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
KR101623958B1 (ko) * 2008-10-01 2016-05-25 삼성전자주식회사 인버터 및 그의 동작방법과 인버터를 포함하는 논리회로
US8384439B2 (en) * 2008-11-28 2013-02-26 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
FR2949904B1 (fr) * 2009-09-07 2012-01-06 Commissariat Energie Atomique Circuit integre a transistors mos couples electrostatiquement et procede de realisation d'un tel circuit integre
JP2011258760A (ja) * 2010-06-09 2011-12-22 Ricoh Co Ltd 積層型半導体装置
CN103178060A (zh) * 2011-12-23 2013-06-26 上海中科联和显示技术有限公司 场效应晶体管互补反相器及其制备方法
CN103367353A (zh) * 2012-03-30 2013-10-23 东莞万士达液晶显示器有限公司 主动元件及主动元件阵列基板
US9087904B2 (en) * 2012-06-08 2015-07-21 Joled Inc. Thin-film transistor having tapered organic etch-stopper layer
US20140103440A1 (en) * 2012-10-15 2014-04-17 Texas Instruments Incorporated I-shaped gate electrode for improved sub-threshold mosfet performance
KR102087438B1 (ko) * 2013-12-17 2020-04-16 에스케이하이닉스 주식회사 작은 옵셋을 갖는 모스 트랜지스터 및 그 제조방법과, 이를 이용한 전자소자
CN104752426A (zh) * 2013-12-26 2015-07-01 昆山国显光电有限公司 共栅极立体式cmos器件、oled器件及其制造方法
US9595546B2 (en) * 2014-02-25 2017-03-14 Lg Display Co., Ltd. Display backplane and method of fabricating the same
EP3113226B1 (en) 2014-02-25 2019-05-08 LG Display Co., Ltd. Display backplane and method for manufacturing same
JP6541398B2 (ja) * 2014-04-11 2019-07-10 株式会社半導体エネルギー研究所 半導体装置
KR20170013240A (ko) * 2014-05-30 2017-02-06 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 이를 제조하기 위한 방법
JP6647830B2 (ja) * 2015-10-20 2020-02-14 ローム株式会社 半導体装置及びそれを用いた半導体集積回路
WO2018029594A1 (en) * 2016-08-09 2018-02-15 King Abdullah University Of Science And Technology A semiconductor device including monolithically integrated pmos and nmos transistors
KR101905717B1 (ko) * 2017-03-02 2018-11-21 포항공과대학교 산학협력단 삼차원 적층구조의 듀얼 게이트 박막 트랜지스터 논리 회로
CN107154407A (zh) * 2017-05-17 2017-09-12 厦门天马微电子有限公司 复合薄膜晶体管器件及其制造方法、显示面板和显示装置
KR102446823B1 (ko) * 2017-06-16 2022-09-26 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN107527925B (zh) * 2017-08-25 2019-11-05 京东方科技集团股份有限公司 显示基板及其制造方法、显示面板、显示装置
JP2019050323A (ja) * 2017-09-12 2019-03-28 シャープ株式会社 アクティブマトリクス基板およびデマルチプレクサ回路
CN109509793B (zh) * 2017-09-15 2020-12-01 京东方科技集团股份有限公司 薄膜晶体管、其制造方法及电子装置
CN107799521A (zh) * 2017-10-10 2018-03-13 深圳市华星光电半导体显示技术有限公司 Cmos反相器及阵列基板
CN107910375A (zh) * 2017-11-02 2018-04-13 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN109686301B (zh) * 2019-02-28 2020-10-16 厦门天马微电子有限公司 光感电路及其驱动方法、显示面板和显示装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202758893U (zh) * 2012-08-03 2013-02-27 成都国微电子有限公司 一种晶体管版图结构及芯片版图结构

Also Published As

Publication number Publication date
US11508761B2 (en) 2022-11-22
CN110060998A (zh) 2019-07-26
US20200135774A1 (en) 2020-04-30

Similar Documents

Publication Publication Date Title
US10050097B2 (en) Organic light-emitting diode display
CN107978610B (zh) 一种阵列基板、显示面板、显示装置及阵列基板的制造方法
CN107731858B (zh) 一种阵列基板、其制作方法及显示面板
KR102141557B1 (ko) 어레이 기판
US10074328B2 (en) Active matrix substrate
TWI692015B (zh) 電晶體裝置
CN110676253B (zh) 一种静电释放电路、阵列基板、显示面板及显示装置
KR102640164B1 (ko) 박막 트랜지스터 표시판
US11362118B2 (en) Array substrate, manufacturing method thereof, and display panel
CN103299431A (zh) 半导体装置
CN112289841A (zh) 显示面板及显示装置
KR20140022523A (ko) 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 유기 발광장치
CN111508974A (zh) 阵列基板及其制作方法、移位寄存器单元、显示面板
US20160351719A1 (en) Thin film transistor and method of manufacturing same
EP3754637B1 (en) Pixel unit, array substrate and display device
CN110060998B (zh) 一种反相电路结构、栅极驱动电路及显示面板
CN206619596U (zh) 阵列基板和显示面板
US10833140B1 (en) Display substrate, manufacturing method thereof, display device and mask plate
CN105633136A (zh) 一种薄膜晶体管、其驱动方法、阵列基板及显示装置
CN109817646B (zh) 基板、显示面板及基板的制备方法
US20220238620A1 (en) Display substrate and display device
CN110085677B (zh) 驱动晶体管、阵列基板和显示面板
US10976627B2 (en) Active matrix substrate and liquid crystal display panel comprising same
CN105633098A (zh) 一种驱动背板及其制备方法和应用
CN110600488A (zh) 一种氧化物薄膜晶体管及其驱动方法、显示装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant