CN1100346C - 引线框和片式半导体封装制造方法 - Google Patents
引线框和片式半导体封装制造方法 Download PDFInfo
- Publication number
- CN1100346C CN1100346C CN97100725A CN97100725A CN1100346C CN 1100346 C CN1100346 C CN 1100346C CN 97100725 A CN97100725 A CN 97100725A CN 97100725 A CN97100725 A CN 97100725A CN 1100346 C CN1100346 C CN 1100346C
- Authority
- CN
- China
- Prior art keywords
- lead
- chip
- wire
- wafer
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
制造片式半导体封装的方法包括下列步骤:把引线框牢固地对准设置于晶片上;进行引线键合工艺,用金属线电连接有台阶的每根引线和晶片上多个中心焊盘中相应的一个;进行化合物模制工艺,模制包括金属线和引线在内的区域,但使每根有弯折引线的最上表面外露;在每根引线的外露部分上镀敷导电金属材料;及锯切晶片,形成分立半导体芯片。
Description
技术领域
本发明涉及半导体封装制造方法,特别涉及引线框和片式半导体封装制造方法,用于简化制造步骤,因此易于批量生产。
背景技术
近年来,随着半导体封装元件的日益小型化,半导体封装需要小型化和减薄,所以人们研制了LOC(芯片上引线)型半导体封装,并将其投入批量生产。
图1展示了一种常规LOC型半导体封装,如图1所示,在垫片1上安装有半导体芯片2,芯片上除中心部位外形成有粘性覆盖膜4,膜4上设置有多根引线3,引线3有多个弯折点,并从引线框9伸出。在芯片2表面中心部位,形成有多个芯片焊盘5,每个焊盘通过金属线6与相应的一根引线3电连接。在包括引线3、粘性膜4、芯片焊盘5和金属线6的芯片2上模制环氧树脂化合物7,其中引线3的前部邻近引线框9,该部分的上表面外露。
下面,参照图2A至2E,说明这样构成的常规片式半导体封装的制造方法。
首先,如图2A所示,进行芯片键合工艺,以便在从管芯基座框8延伸的垫片1上安装半导体芯片2。管芯基座框8上有芯片2,该框与引线框9对准,引线框9适于中心焊盘键合,并且其上延伸出多根有多个弯折的引线3。然后,进行焊接工艺,连接管芯基座框8和引线框9。
如图2B所示,用金属线6进行引线键合工艺,电连接形成在芯片2表面中心上的每个芯片焊盘5与相应的引线3。
然后,如图2C所示,通过焊接连接到框8、9上的芯片2与形成在下模板12表面上形成的槽13对准。接着,把上模板11贴到下模板12上,再把模制化合物7注入通风孔12a中。
如图2D所示,在完成了模制工艺后,模板11、12与框8、9是分离的。然后进行修整工艺,切掉从模制封装体7中外突出的部分,从而完成片式半导体封装,引线3从封装体7的底表面外露。
为了制造常规片式半导体封装,在进行管芯接合之前,需先由晶片20分离出分立半导体芯片2。然后将分离的芯片2对准封接在管芯基座框8的垫片1上,以便进行引线键合。
然而,重复且复杂的制造工艺使得分别把芯片贴到垫片上的操作要花费大量时间。另外,复杂的工艺还会导致芯片外伤,因而会妨碍生产率的提高。
发明内容
因此,本发明的目的是提供一种制造片式半导体封装的方法,能够通过简化制造工艺来提高生产率。
本发明的另一个目的是提供一种引线框,用于制造本发明的片式半导体封装。
根据本发明,实现上述目的的制造片式半导体封装的方法包括下列步骤:把引线框牢固地对准设置于晶片上,其中引线框包括多根分别相应于晶片上芯片划分线的引线支撑条,多根有台阶和弯折的引线从每根支撑条延伸一定距离,其中晶片包括多个中心焊盘型芯片,各芯片被彼此划分开,以便彼此间分离;进行引线键合工艺,用金属线电连接每根引线和相应的一个晶片中心焊盘;进行化合物模制工艺,模制包括金属线和引线在内的区域,同时使每根有弯折引线的最上表面外露;在每根引线的外露部分上镀敷导电金属材料;及锯切晶片,形成分立半导体芯片。
另外,半导体芯片封装的引线框包括:多根相应于晶片上相应芯片划分线的引线支撑条;相互面对地从每根引线支撑条向每个芯片的垂直中线延伸的多根引线,其中,每根引线皆具有一个以上的台阶或弯折。
附图说明
图1是常规片式半导体封装的剖面图;
图2A是说明管芯键合及引线框焊接工艺的图1所示封装的分解透视图;
图2B是展示引线键合步骤的图2所示已组装封装的透视图;
图2C是展示化合物模制步骤的常规片式半导体封装制造工艺的透视图;
图2D是已完成的常规半导体封装的透视图;
图2E是已完成的常规半导体封装的底视图;
图3是带有芯片上的多个中心焊盘的半导体晶片的平面图;
图4是根据本发明的引线框的平面图;
图5A是安装在半导体晶片上的本发明引线框的平面图;
图5B是展示本发明的引线键合工艺的平面图;
图5C是沿图5B中A-A线所取的剖面图;
图5D是展示模制工艺的本发明芯片封装的剖面图;
图5E是展示镀敷工艺的本发明芯片封装的剖面图。
具体实施方式
下面将参照各附图说明本发明制造片式半导体封装的方法。
如图3所示,把晶片20划成网格状,划分出多个管芯或芯片21,此后其中每个芯片皆可以从其上分离开。在每个芯片21的中心部位对准式地形成有多个中心焊盘21a。
参见图4,沿引线框30的行和列线上,延伸着支撑多根引线32的引线支撑条31。引线支撑条31是相应于图3所示的晶片20的芯片划分线分别设置的。
由引线支撑条31包围着的每个格子内,引线32分别从每列引线支撑条31向每个格子的垂直中心线延伸一定距离,因而容易封装中心焊盘型半导体芯片。另外,每根引线32有不止一个弯折或台阶,每根引线支撑条31的宽度最好小于晶片20的厚度。
下面将说明本发明制造片式半导体封装的方法。
首先,如图5A所示,把图4所示引线框30安装在图3所示的晶片20上,使引线支撑条31分别与相应的每根图3所示芯片划分线对准,然后借助粘性覆盖膜40把框30和晶片20牢固地贴在一起,同时每个芯片21之上延伸的多根引线32与每个芯片21中心部位排列的每侧中心焊盘21a对准。
然后,如图5B和5C所示,利用金属线50进行引线键合工艺,电连接每根引线32和相应的一个中心焊盘21a。
然后,如图5D所示,利用环氧树脂模制化合物60进行模制工艺,密封每个包括金属线50、中心焊盘21a和引线32的半导体封装,但每根皆具有台阶或弯折的引线32的最上表面外露。
如图5E所示,进行镀敷工艺,利用导电金属材料70,在每根外露的引线32上作电镀,其中导电金属材料70可以是焊料。
最后,沿每根引线框30的引线支撑条31进行锯切工艺,形成分立的半导体芯片,从而完成本发明的片式半导体芯片封装,此时,由于形成的每根引线支撑条31的宽度小于划开的晶片20的厚度,所以完全可以在锯切工艺期间将每根引线支撑条消除掉。
如上所述,本发明的制造片式半导体封装的方法,把引线框牢固地装在晶片上,随后进行引线键合工艺和化合物模制工艺,最后将晶片分成分立芯片,从而减少了必要的制造步骤,因此容易进行批量生产。
Claims (8)
1.一种制造片式半导体封装的方法,包括下列步骤:
把引线框牢固地对准设置于晶片上,其中引线框包括多根分别相应于晶片上芯片划分线的引线支撑条,多根有台阶和弯折的引线从每根支撑条延伸一定距离,其中晶片包括多个中心焊盘型芯片,各芯片被彼此划分开,以便彼此间分离;
进行引线键合工艺,用金属线电连接每根引线和相应的一个晶片中心焊盘;
进行化合物模制工艺,模制包括金属线和引线在内的区域,同时外露每根引线的最上表面;
在每根引线的外露部分上镀敷导电金属材料;及
锯切晶片,形成分立半导体芯片。
2.根据权利要求1的方法,其特征为,用电镀技术进行镀敷步骤。
3.根据权利要求1的方法,其特征为,施加粘性覆盖膜,连接引线框与晶片。
4.根据权利要求1的方法,其特征为,模制步骤用环氧树脂化合物。
5.根据权利要求1的方法,其特征为,导电金属材料是焊料。
6.一种半导体芯片封装的引线框,包括:
多根对应于晶片上相应芯片划分线的引线支撑条;及
相互面对地从每根引线支撑条伸出并接近其间的每个芯片的垂直中线的多根引线,其中,每根引线皆具有一个以上的台阶或弯折。
7.根据权利要求6的方法,其特征为,多根引线支撑条构成矩形格子。
8.根据权利要求6的方法,其特征为,每根引线支撑条的宽度皆小于晶片厚度。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR16645/96 | 1996-05-17 | ||
KR1019960016645A KR0179920B1 (ko) | 1996-05-17 | 1996-05-17 | 칩 사이즈 패키지의 제조방법 |
KR16645/1996 | 1996-05-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1166052A CN1166052A (zh) | 1997-11-26 |
CN1100346C true CN1100346C (zh) | 2003-01-29 |
Family
ID=19459008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN97100725A Expired - Fee Related CN1100346C (zh) | 1996-05-17 | 1997-02-26 | 引线框和片式半导体封装制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5926380A (zh) |
JP (1) | JP2814233B2 (zh) |
KR (1) | KR0179920B1 (zh) |
CN (1) | CN1100346C (zh) |
DE (1) | DE19712551B4 (zh) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0844665A3 (en) * | 1996-11-21 | 1999-10-27 | Texas Instruments Incorporated | Wafer level packaging |
KR100390897B1 (ko) * | 1997-12-29 | 2003-08-19 | 주식회사 하이닉스반도체 | 칩 크기 패키지의 제조방법 |
KR100324602B1 (ko) * | 1998-06-27 | 2002-04-17 | 박종섭 | 일괄패키지공정이가능한반도체장치의제조방법 |
US6341070B1 (en) * | 1998-07-28 | 2002-01-22 | Ho-Yuan Yu | Wafer-scale packing processes for manufacturing integrated circuit (IC) packages |
SG87769A1 (en) * | 1998-09-29 | 2002-04-16 | Texas Instr Singapore Pte Ltd | Direct attachment of semiconductor chip to organic substrate |
DE19856833A1 (de) * | 1998-12-09 | 2000-06-21 | Siemens Ag | Verfahren zur Herstellung eines integrierten Schaltkreises |
FR2787241B1 (fr) | 1998-12-14 | 2003-01-31 | Ela Medical Sa | Composant microelectronique cms enrobe, notamment pour un dispositif medical implantable actif, et son procede de fabrication |
JP4148593B2 (ja) * | 1999-05-14 | 2008-09-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
KR100355748B1 (ko) * | 1999-11-01 | 2002-10-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조용 부재 |
DE19927747C1 (de) * | 1999-06-17 | 2000-07-06 | Siemens Ag | Multichipmodul aus einem zusammenhängenden Waferscheibenteil für die LOC-Montage sowie Verfahren zu dessen Herstellung |
US7211877B1 (en) * | 1999-09-13 | 2007-05-01 | Vishay-Siliconix | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US6271060B1 (en) * | 1999-09-13 | 2001-08-07 | Vishay Intertechnology, Inc. | Process of fabricating a chip scale surface mount package for semiconductor device |
US7042070B2 (en) | 1999-09-22 | 2006-05-09 | Texas Instruments Incorporated | Direct attachment of semiconductor chip to organic substrate |
KR100440789B1 (ko) * | 1999-12-30 | 2004-07-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지와 이것의 제조방법 |
JP2001339029A (ja) * | 2000-05-26 | 2001-12-07 | Shinko Electric Ind Co Ltd | 多層リードフレーム及びこれを用いた半導体装置 |
SG112799A1 (en) * | 2000-10-09 | 2005-07-28 | St Assembly Test Services Ltd | Leaded semiconductor packages and method of trimming and singulating such packages |
US6686258B2 (en) | 2000-11-02 | 2004-02-03 | St Assembly Test Services Ltd. | Method of trimming and singulating leaded semiconductor packages |
US7754537B2 (en) * | 2003-02-25 | 2010-07-13 | Tessera, Inc. | Manufacture of mountable capped chips |
US6972480B2 (en) * | 2003-06-16 | 2005-12-06 | Shellcase Ltd. | Methods and apparatus for packaging integrated circuit devices |
US7936062B2 (en) | 2006-01-23 | 2011-05-03 | Tessera Technologies Ireland Limited | Wafer level chip packaging |
US8604605B2 (en) | 2007-01-05 | 2013-12-10 | Invensas Corp. | Microelectronic assembly with multi-layer support structure |
US7927920B2 (en) * | 2007-02-15 | 2011-04-19 | Headway Technologies, Inc. | Method of manufacturing electronic component package, and wafer and substructure used for manufacturing electronic component package |
US7816176B2 (en) * | 2007-05-29 | 2010-10-19 | Headway Technologies, Inc. | Method of manufacturing electronic component package |
US7906838B2 (en) * | 2007-07-23 | 2011-03-15 | Headway Technologies, Inc. | Electronic component package and method of manufacturing same |
US7676912B2 (en) * | 2007-09-05 | 2010-03-16 | Headway Technologies, Inc. | Method of manufacturing electronic component package |
JP5405785B2 (ja) * | 2008-09-19 | 2014-02-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN102222627B (zh) * | 2010-04-14 | 2013-11-06 | 万国半导体(开曼)股份有限公司 | 具有晶圆尺寸贴片的封装方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4946633A (en) * | 1987-04-27 | 1990-08-07 | Hitachi, Ltd. | Method of producing semiconductor devices |
US5148266A (en) * | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5679977A (en) * | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
KR940007757Y1 (ko) * | 1991-11-14 | 1994-10-24 | 금성일렉트론 주식회사 | 반도체 패키지 |
US5286679A (en) * | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
KR970010678B1 (ko) * | 1994-03-30 | 1997-06-30 | 엘지반도체 주식회사 | 리드 프레임 및 이를 이용한 반도체 패키지 |
US5657206A (en) * | 1994-06-23 | 1997-08-12 | Cubic Memory, Inc. | Conductive epoxy flip-chip package and method |
MY114888A (en) * | 1994-08-22 | 2003-02-28 | Ibm | Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips |
US6165813A (en) * | 1995-04-03 | 2000-12-26 | Xerox Corporation | Replacing semiconductor chips in a full-width chip array |
-
1996
- 1996-05-17 KR KR1019960016645A patent/KR0179920B1/ko not_active IP Right Cessation
-
1997
- 1997-02-26 CN CN97100725A patent/CN1100346C/zh not_active Expired - Fee Related
- 1997-03-25 DE DE19712551A patent/DE19712551B4/de not_active Expired - Fee Related
- 1997-05-06 US US08/851,955 patent/US5926380A/en not_active Expired - Lifetime
- 1997-05-09 JP JP9119048A patent/JP2814233B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1166052A (zh) | 1997-11-26 |
JP2814233B2 (ja) | 1998-10-22 |
JPH1050920A (ja) | 1998-02-20 |
DE19712551B4 (de) | 2006-02-16 |
KR0179920B1 (ko) | 1999-03-20 |
DE19712551A1 (de) | 1997-11-20 |
US5926380A (en) | 1999-07-20 |
KR970077540A (ko) | 1997-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1100346C (zh) | 引线框和片式半导体封装制造方法 | |
US6630729B2 (en) | Low-profile semiconductor package with strengthening structure | |
US8071426B2 (en) | Method and apparatus for no lead semiconductor package | |
US7429500B2 (en) | Method of manufacturing a semiconductor device | |
KR920010198B1 (ko) | 개량된 리드프레임 및 개량된 리드프레임을 사용하는 전자부품을 제조하는 방법 | |
US20010042904A1 (en) | Frame for semiconductor package | |
CN1412843A (zh) | 引线框架、其制造方法及使用它的半导体器件的制造方法 | |
CN1412842A (zh) | 引线框架以及利用该引线框架制造半导体装置的方法 | |
CN1490870A (zh) | 引线框及其制造方法,以及用该引线框制造的半导体器件 | |
CN101587849A (zh) | 具有通过冲压形成的特征的半导体器件封装 | |
US20040217450A1 (en) | Leadframe-based non-leaded semiconductor package and method of fabricating the same | |
CN100338768C (zh) | 引线框及用此引线框的半导体器件及其制造方法 | |
US9659842B2 (en) | Methods of fabricating QFN semiconductor package and metal plate | |
KR0185790B1 (ko) | 반도체 장치의 제조방법 | |
US11569152B2 (en) | Electronic device with lead pitch gap | |
US6424025B1 (en) | Cross grid array package structure and method of manufacture | |
US6303983B1 (en) | Apparatus for manufacturing resin-encapsulated semiconductor devices | |
KR20090085258A (ko) | 몰딩후 연결단자가 분리되는 반도체 패키지 제조방법 및이에 의한 반도체 패키지 | |
CN102779761A (zh) | 用于封装半导体管芯的引线框架和方法 | |
JPS60189940A (ja) | 樹脂封止型半導体装置の製法 | |
CN220873575U (zh) | 导线架以及封装结构 | |
CN209766412U (zh) | 高密着性预成型基板 | |
CN1314113C (zh) | 防止管脚短路的导线架及具有该导线架的半导体封装件的制法 | |
JPH0653399A (ja) | 樹脂封止型半導体装置 | |
JPH0817995A (ja) | 半導体装置用リードフレーム |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030129 Termination date: 20140226 |