CN1412842A - 引线框架以及利用该引线框架制造半导体装置的方法 - Google Patents

引线框架以及利用该引线框架制造半导体装置的方法 Download PDF

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CN1412842A
CN1412842A CN02146874A CN02146874A CN1412842A CN 1412842 A CN1412842 A CN 1412842A CN 02146874 A CN02146874 A CN 02146874A CN 02146874 A CN02146874 A CN 02146874A CN 1412842 A CN1412842 A CN 1412842A
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lead
lead frame
semiconductor device
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松沢秀树
林真太郎
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Abstract

一种引线框架,用于无引线封装件(半导体装置),例如四线扁平无引线封装件(QFN),该引线框架包括:底座垫部分,该底座垫部分布置在由框架部分确定的开口的中心处;多个引线部分,这些引线部分成梳子形状从框架部分朝着底座垫部分延伸。各个引线部分的、沿将最终分割成半导体装置的区域的周边的部分的引线宽度比相应引线部分的其它部分的引线宽度更窄。在该引线框架中,布置有多个底座垫部分,框架部分环绕各个底座垫部分,与各个底座垫部分相对应的多个引线部分从环绕相应底座垫部分的框架部分朝着相应底座垫部分延伸。而且,胶带粘附在引线框架的一个表面上。

Description

引线框架以及利用该引线框架 制造半导体装置的方法
发明领域
本发明涉及一种引线框架,该引线框架用作封装件(package)的底架,以便安装半导体元件。尤其是,本发明涉及一种引线框架,该引线框架用于无引线封装件(表面安装的半导体装置),例如四线扁平无引线封装件(QFN),并且它的引线形状适于解决由在封装件的装配过程中在切割时产生“毛刺(burr)”所引起的问题,本发明还涉及利用该引线框架制造半导体装置的方法。
背景技术
图1A至图1C示意表示了用于无引线封装件例如QFN中的现有技术的引线框架的结构。在这些附图中,图1A表示了该引线框架的一部分的平面结构图,图1B表示了该引线框架沿图1A中的线A-A’看时的割视结构,而图1C表示了该引线框架沿图1A中的线B-B’看时的剖视结构。
在图1A至图1C中,参考标号10表示用作QFN的基体的引线框架。该引线框架10主要由通过使金属板例如铜板形成图案而获得的底架11构成。该引线框架10形成为这样,即底座垫(die-pad)部分12和环绕该底座垫部分12的引线部分13分开,以便将相应的半导体元件安装在其上。而且,参考标号14表示框架部分。各引线部分13成梳子形状从框架部分14朝着底座垫部分12伸出。还有,各底座垫部分12由从框架部分14的四角伸出的四个支承杆15支承。
还有,金属膜16形成于底架11的整个表面上,胶带17粘接在底架11的背面(在所示实施例中为下平面)上。胶带17的粘接基本起到在封装件装配过程中在模制时防止模铸树脂泄漏到框架的背面(这也称为“模制涌出(mold flush)”),该封装件装配过程将在后面阶段中执行。
还有,参考标记w1表示各引线部分13的引线宽度,参考标记d1表示两个相邻引线部分13之间的间隔(引线间隔)。各引线部分13成梳子形状以恒定的引线宽度w1(图1A)从框架部分14上伸出。而且,虚线CL表示分开线,用于在封装件装配过程中将该引线框架最终分割成各个封装件,该封装件装配过程将在后面的阶段中执行。
当利用具有上述结构的引线框架10来装配封装件(半导体装置)时,其基本方法包括以下步骤:将半导体元件安装在引线框架的底座垫部分上(模片(die)接合);使半导体元件的电极通过接合线与引线框架的引线部分电连接(引线接合);利用模铸树脂密封该半导体元件、接合线等(模制);在剥去胶带后将该引线框架分割成封装件(半导体装置)(切割)等。还有,关于模制的类型,包括单个模制和批量模制,在单个模制中,利用树脂对半导体元件逐个进行密封,而在批量模制中,利用树脂将多个半导体元件一起密封。因为与批量模制方法相比,单个模制方法很难高效进行封装件的装配,因此,近年来,批量模制已经成为主流。
图2A和图2B示意表示了利用上述引线框架10制造的半导体装置的结构。在这些图中,图2A表示了该半导体装置沿图1A中的线A-A’看时的横剖结构,而图2B表示了该半导体装置沿图1A中的线B-B’看时的横剖结构。
在如图2A中所示的半导体装置20中,参考标号21表示安装在底座垫部分12上的半导体元件;参考标号22表示使半导体元件21的各电极与各引线部分13电连接的接合线;而参考标号23表示用于保护半导体元件21、接合线22等的模铸树脂。还有,参考标记BR表示由引线部分13产生的金属“毛刺”。在上述封装件装配过程的切割步骤中,在利用切块机等装置沿分开线CL(图1A)同时切割金属(引线部分13)和树脂(模铸树脂23)时,在切割方向的下游侧将产生这样的毛刺BR。
在利用批量模制方法来对封装件(半导体装置)例如QFN进行装配的步骤中,在把引线框架切割成封装件时将由上述引线部分13产生毛刺BR。
当产生毛刺BR时,相邻引线部分13可能会电短路,如图2B所示。因此,所导致的缺点是生产率或产量降低,而且作为最终产品的封装件(半导体装置)的可靠性降低。
由于该缺点,已知的一种措施是加宽相邻引线部分13之间的间隔(引线间隔d1)。不过,引线间隔d1将在允许范围内选择为特定值,该允许范围由封装件的尺寸和该封装件所需的外部接线端数目之间的关系来确定。因此,加宽引线间隔d1的方法有一定限制。
本发明人利用不同粗糙度的切块机刀片和在切割时采用不同处理速度来进行了一系列试验。结果证明,当切块机的刀片做得相对较精细且处理速度控制得相对较慢时,毛刺的产生将更明显。
因此,对于金属材料和树脂材料的各种组合,需要找出能使毛刺的产生最小的优化条件(最合适的刀片粗糙度和处理速度),切割处理根据该条件来进行。因此,需要进行复杂的处理,以便制造具有更少毛刺的半导体装置。最终,将导致出现相关成本增加的问题。
发明内容
本发明的一个目的是提供一种引线框架和一种利用该引线框架制造半导体装置的方法,其中,即使在半导体装置的装配过程中通过切割而产生了毛刺,该引线框架也能有效防止相邻引线部分之间的短路,从而能提高该半导体装置的可靠性,也有助于缩短它的制造周期和减小它的制造成本。
为了实现上述目的,根据本发明的一个方面,提供了一种引线框架,该引线框架包括:底座垫部分,该底座垫部分布置在由框架部分确定的开口的中心处;多个引线部分,这些引线部分成梳子形状从框架部分朝着底座垫部分延伸;各个引线部分的、沿着将被最终分割成半导体装置的区域的周边的部分的引线宽度比相应引线部分的其它部分的引线宽度更窄。
根据该方面的引线框架,在后面阶段的封装件(半导体装置)装配时将与框架部分分开的部分(即,沿将最终分割成半导体装置的区域的周边的部分)的引线宽度相对较窄。因此,与该部分对应的引线间隔(最终将从封装件中暴露的引线间隔)制成为相对较宽。
因此,即使在切割时由引线部分形成毛刺,在相邻引线部分之间也基本不会发生短路。这样,实际上能够防止发生该短路。这一优点有利于提高作为最终产品的半导体装置的可靠性,并缩短它的制造周期和降低它的制造成本。
而且,根据本发明的另一方面,提供了一种利用上述方面的引线框架制造半导体装置的方法,该方法包括以下步骤:将半导体元件分别安装在引线框架的底座垫部分上;使半导体元件的各电极与引线框架的、与该半导体元件的各电极相对应的多个引线部分分别通过接合线来电连接;通过模铸树脂来密封半导体元件、接合线以及引线部分;剥去胶带;以及沿分开线将以模铸树脂密封的引线框架分割成各个半导体装置,该分开线横穿过该多个引线部分的狭窄部分。
附图的简要说明
图1A至1C是示意表示现有技术的引线框架的结构的视图;
图2A和2B是示意表示利用图1A至1C中所示的引线框架来制造的半导体装置的结构的剖视图;
图3A至3C是示意表示根据本发明一个实施例的引线框架的结构的视图;
图4A和图4B是示意表示利用图3A至3C中所示的引线框架来制造的半导体装置的结构的剖视图;
图5A至5E是表示图4A中所示的半导体装置的制造过程的剖视图;以及
图6A至6G是表示图3A中所示的引线框架中的引线部分(引线形状)的各种变化实例的视图。
优选实施例的说明
图3A至图3C示意表示了用于无引线封装件例如QFN中的、根据本发明一个实施例的引线框架的结构。在该附图中,图3A表示了一部分引线框架的平面结构;图3B表示了该引线框架沿图3A中的线A-A’看时的横剖结构;而图3C表示了该引线框架沿图3A中的线B-B’看时的横剖结构。
该实施例的引线框架30基本包括与图1A至图1C中所示的引线框架10相同的结构。即,该引线框架30主要由通过使金属板形成图案而获得的底架31构成。该引线框架30形成为这样,即底座垫部分32和环绕该底座垫部分32的引线部分33分开,以便将相应的半导体元件安装在其上。而且,参考标号34表示框架部分。各引线部分33成梳子形状从框架部分34朝着底座垫部分32伸出。还有,各底座垫部分32由从框架部分34的四角伸出的四个支承杆35支承。各引线部分33由内部引线部分和外部引线部分(外部接线端)构成,该内部引线部分将与半导体元件的电极电连接,该外部引线部分将与封装基体上的布线电连接。而且,金属膜(电镀膜)36形成于底架31的整个表面上,胶带37粘接在底架31的背面(在所示实施例中为下平面)上,以便基本防止模制涌出。而且,参考标记w2表示各引线部分33的引线宽度,参考标记d2表示两个相邻引线部分33之间的间隔(引线间隔),虚线CL表示分开线。
如后面结合利用引线框架制造半导体装置的方法所述,本实施例的引线框架30的特征在于:在各引线部分33通过半导体装置的装配而与框架部分34分开的位置处的部分(分开线CL穿过的部分)的引线宽度w2比其它部分的引线宽度w1更窄(w2<w1)。换句话说,引线框架30形成为这样,即对应于狭窄部分(引线宽度为w2)的引线间隔d2比对应于其它部分(引线宽度为w1)的引线间隔d1更宽(d2>d1)。
其中,引线宽度w1和引线间隔d1分别与图1A至1C中所示的引线部分13的引线宽度w1和引线间隔d1相同。即,在现有技术(图1A至1C)中,各引线部分13成梳子形状以恒定引线宽度w1从框架部分14上伸出,而在本实施例(图3A至3C)中,各引线部分33成梳子形状并以相对较窄的引线宽度w2从框架部分34上伸出预定距离,再以引线宽度w1进一步延伸。
顺便说明,当引线框架30(底架31)通过蚀刻形成时,狭窄部分的引线宽度w2可设置为100μm或更小。
根据本实施例的引线框架30的结构,各引线部分33的在封装件(半导体装置)装配时将要与框架部分34分开的部分处的引线宽度w2相对更窄(w2<w1)。因此,对应于该部分(引线宽度为w2)的引线间隔d2相对更宽(d2>d1)。
因此,即使在进行切割以便分割成封装件时从引线部分33上产生了毛刺BR,如图4B所示,相邻引线部分33之间也基本不会发生短路,从而实际上能够避免短路的发生。这样,可以提高作为最终产品的封装件(半导体装置)的可靠性,缩短它的制造周期,并减小它的制造成本。
还有,在现有技术中,为了减小毛刺BR的产生,需要根据金属和树脂材料的种类来分别考虑切割刀片的粗糙度和处理速度,以便找到最佳条件,这是由于在最终封装件的周边上的引线间隔d1相对狭窄。相反,在本实施例中,如上所述,引线间隔d2相对较宽。因此,不需要象现有技术那样找出精确的条件。因此,可以缩短制造具有较少毛刺的引线框架所需的时间,并降低制造成本。
而且,毛刺BR的允许范围扩大,因为引线间隔d2相对加宽。因此,切割的处理速度能够提高,这有助于降低制造成本。
尽管没有特别表示,但是本实施例的引线框架30可以通过一系列处理来制造,该一系列处理包括:通过蚀刻或冲压而使金属板形成图案、电解电镀等,这些都是本领域技术人员已知的。下面将介绍该制造方法的一个实例。
首先,通过蚀刻或冲压而使金属板形成如图3A的平面结构图所示的图形,从而形成底架31。铜(Cu)、Cu基合金、铁-镍(Fe-Ni)、Fe-Ni基合金等都可以用作金属板的材料。
然后,通过电解电镀而在底架31的整个表面上形成金属膜36。例如,为了增加附着力而将镍(Ni)电镀在底架31的表面上,同时用该底架31作为供给层(feed layer),再在它上面电镀钯(Pd),以便增加导电性,再在该Pd层上电镀金(Au),从而形成(Ni/Pd/AU)金属膜36。
最后,将由环氧树脂、聚酰亚胺树脂、聚酯树脂等制成的胶带37粘附在底架31的背面(在图3B和3C所示实例中为下表面)上,从而获得引线框架30。
图4A和4B示意表示了利用本实施例的引线框架30制造的半导体装置的结构。在该图中,图4A表示了该半导体装置沿图3A中的线A-A’看时的横剖结构,而图4B表示了该半导体装置沿图3A中的线B-B’看时的横剖结构。
在所示的半导体装置40中,参考标号41表示安装在底座垫部分32上的半导体元件;参考标号42表示用于使半导体元件41的各电极与各引线部分33电连接的接合线;参考标号43表示用于保护半导体元件41、接合线42等的模铸树脂。还有,参考标记BR表示在将于后面介绍的封装件装配过程的切割步骤中由引线部分33产生的金属毛刺。该毛刺BR与在普通实例(图2B)中介绍的毛刺相同。
下面将参考图5A至图5E介绍制造该半导体装置40的方法,这些附图分别表示了在该方法的制造过程中的步骤。
在第一步骤中(图5A),引线框架30由保持器的夹具(未示出)夹持,同时使粘附有胶带37的表面朝下,并将半导体元件41分别安装在引线框架30的各个底座垫部分32上。更准确地说,将粘结剂例如环氧树脂涂覆在底座垫部分32上,并使半导体元件41的底表面(与形成有电极的表面相反的表面)向下放置,从而通过该粘结剂将半导体元件41粘附在底座垫部分32上。
在下一步骤中(图5B),各半导体元件41的电极和在引线框架30的一个表面(在所示实例中为上表面)上的相应引线部分33分别通过接合线42而电连接。这样,各半导体元件41安装在引线框架30上。
应当知道,在该阶段,各个引线部分33同属于两个相邻的底座垫部分32,由图3A中所示的平面结构可知。
在下一步骤中(图5C),根据批量模制方法,在安装有半导体元件41的一侧的引线框架30的整个表面由模铸树脂43密封。尽管在图中没有特别示出,但是该密封通过以下方式进行:将引线框架30布置在下部模制模具(一对上下模具)上,并从上部使该引线框架30与上模具结合,然后充入模铸树脂43。例如,采用传递模塑法作为用于密封的方法。
在下一步骤中(图5D),将以模铸树脂43密封的引线框架30(图5C)从模制模具中取出,然后剥去胶带37并除去底架31。
在最终步骤中(图5E),利用切块机等沿分开线D-D’将底架31(该引线框架安装有各个半导体元件41并利用模铸树脂43密封了整个表面)分成封装件单元,该分开线D-D’以虚线表示,这样,各封装件单元包括一个半导体元件41。其中,分开线D-D’与图3A中以虚线表示的分开线CL对齐,即,与经过使各引线部分33的引线宽度较窄(引线宽度w2)的部分的线对齐。
通过上述步骤,将制成具有QFN封装件结构的半导体装置40(图4A)。
尽管前述实施例介绍了具有如图3A所示的引线形状(引线部分33)的引线框架30的实例以及利用该引线框架30制造半导体装置40的方法的实例,但是,该引线部分的引线形状并不局限于图3A中所示的实例。
由这里所述的要点和结构可知,本发明同样可用于其它引线框架,只要该引线框架包括这样的引线部分(引线形状),其中,在封装件(半导体装置)装配时将要与框架部分34分开的部分的引线宽度w2相对较窄。
图6A至6G示意表示了各种变化结构的实例,它们都源自于图3A中所示的引线部分33(引线形状)。
图6A表示了一种引线形状,其中,通过减小引线部分33的两侧,从而使将要与框架部分34分开的部分(分开线CL经过的部分)的引线宽度w2更窄。图6B表示了一种引线形状,其中,从具有相对较宽的引线宽度w1的部分到具有相对较窄的引线宽度w3的部分的线切成倾斜的。图6C是源自于图6B的引线形状的一种引线形状,其中,通过减小引线部分33的两侧,从而使将要与框架部分34分开的部分的引线宽度w2较窄。图6D表示了源自于图3A中所示的引线形状的一种引线形状,其中,引线部分33的、将要形成相对较窄的引线宽度w3的那一部分仅限于它的一部分(引线部分的一侧)。图6E表示了源自于图6A的引线形状的一种引线形状,其中,通过从两侧减小宽度,使得引线部分33的、将要形成较窄引线宽度w2的那一部分形成于该引线部分的中间位置。图6F表示了源自于图6B的引线形状的一种引线形状,其中,通过从一侧减小宽度,使得引线部分33的、将要形成较窄引线宽度w3的那一部分形成于该引线部分的中间位置。图6G表示了源自于图6C的引线形状的一种引线形状,其中,通过从两侧减小宽度,使得引线部分33的、将要形成较窄引线宽度w2的那一部分形成于该引线部分的中间位置。

Claims (7)

1.一种引线框架,包括:
底座垫部分,该底座垫部分布置在一个由框架部分确定的开口的中心处;
多个引线部分,这些引线部分成梳子形状从框架部分朝着底座垫部分延伸;以及
各个所述引线部分的、沿将要被最终分割成半导体装置的区域的周边的部分的引线宽度比相应引线部分的其它部分的引线宽度更窄。
2.根据权利要求1所述的引线框架,其中:布置有多个所述底座垫部分,所述框架部分环绕各个底座垫部分,与各个底座垫部分相对应的多个引线部分从环绕着相应底座垫部分的框架部分朝着相应的底座垫部分延伸。
3.根据权利要求2所述的引线框架,其中:胶带粘附在所述引线框架的一个表面上。
4.根据权利要求1所述的引线框架,其中:各所述引线部分的狭窄部分的引线宽度选择为小于100微米。
5.根据权利要求1所述的引线框架,其中:当该引线框架最终分割成半导体装置时,所述引线部分用作外部接线端,且该引线部分在相应的半导体装置的安装平面侧暴露于周边部分。
6.一种利用如权利要求3所述的引线框架来制造半导体装置的方法,该方法包括以下步骤:
将半导体元件分别安装在所述引线框架的各个底座垫部分上;
使半导体元件的各电极与所述引线框架的、与该半导体元件的各电极相对应的多个引线部分分别通过接合线来电连接;
通过模铸树脂来密封半导体元件、接合线以及多个引线部分;
剥去胶带;以及
沿分开线将以模铸树脂密封的引线框架分割成各个半导体装置,该分开线横穿过所述多个引线部分的狭窄部分。
7.根据权利要求6所述的方法,其中:所述通过模铸树脂而进行的密封通过批量模制方法来进行,在批量模制方法中,所述引线框架在安装有多个半导体元件的一侧的整个表面由树脂密封。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100345293C (zh) * 2004-05-13 2007-10-24 松下电器产业株式会社 半导体装置及半导体装置的制造方法
CN100435329C (zh) * 2003-06-23 2008-11-19 大动力公司 微引线框封装及制造微引线框封装的方法
CN100446234C (zh) * 2003-11-19 2008-12-24 罗姆股份有限公司 引线框的制造方法及使用该方法的半导体装置的制造方法
CN101308831B (zh) * 2007-05-17 2010-06-09 南茂科技股份有限公司 用于无引线封装的引线框及其封装结构
CN102064144A (zh) * 2010-11-10 2011-05-18 日月光半导体制造股份有限公司 四方扁平无引脚封装及其制作方法
CN102202827A (zh) * 2010-07-20 2011-09-28 联发软件设计(深圳)有限公司 用于多列方形扁平无引脚芯片的预上锡方法以及返修方法

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822322B1 (en) * 2000-02-23 2004-11-23 Oki Electric Industry Co., Ltd. Substrate for mounting a semiconductor chip and method for manufacturing a semiconductor device
US20050179541A1 (en) * 2001-08-31 2005-08-18 Red Wolf Technologies, Inc. Personal property security device
US20050030175A1 (en) * 2003-08-07 2005-02-10 Wolfe Daniel G. Security apparatus, system, and method
KR20030053970A (ko) * 2001-12-24 2003-07-02 동부전자 주식회사 반도체 패키지의 리드 프레임
US6710246B1 (en) 2002-08-02 2004-03-23 National Semiconductor Corporation Apparatus and method of manufacturing a stackable package for a semiconductor device
US6723585B1 (en) * 2002-10-31 2004-04-20 National Semiconductor Corporation Leadless package
US6781243B1 (en) * 2003-01-22 2004-08-24 National Semiconductor Corporation Leadless leadframe package substitute and stack package
DE10334384B4 (de) * 2003-07-28 2014-03-27 Infineon Technologies Ag Chipvorrichtung
KR20050083322A (ko) * 2004-02-23 2005-08-26 삼성테크윈 주식회사 반도체 패키지용 리이드 프레임과 이의 제조방법
US6929485B1 (en) * 2004-03-16 2005-08-16 Agilent Technologies, Inc. Lead frame with interdigitated pins
US7394151B2 (en) * 2005-02-15 2008-07-01 Alpha & Omega Semiconductor Limited Semiconductor package with plated connection
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
NL1029169C2 (nl) * 2005-06-02 2006-12-05 Fico Bv Vlakke drager voor elektronische componenten, omhulde elektronische component en werkwijze.
KR100722597B1 (ko) * 2005-07-04 2007-05-28 삼성전기주식회사 구리 패턴이 형성된 더미 영역을 구비한 반도체 패키지기판
JP4635202B2 (ja) * 2005-07-20 2011-02-23 国立大学法人九州工業大学 両面電極パッケージの製造方法
US7768125B2 (en) 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7947534B2 (en) * 2006-02-04 2011-05-24 Stats Chippac Ltd. Integrated circuit packaging system including a non-leaded package
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
CN100407384C (zh) * 2006-11-24 2008-07-30 宁波康强电子股份有限公司 三极管引线框架的制造方法
KR100789419B1 (ko) * 2006-11-27 2007-12-28 (주)원일사 리드프레임 모재 가공방법
CN100440463C (zh) * 2007-03-21 2008-12-03 宁波康强电子股份有限公司 表面贴装用的引线框架的制造方法
CN100454503C (zh) * 2007-03-21 2009-01-21 宁波康强电子股份有限公司 三极管引线框架的制造方法
US20080237814A1 (en) * 2007-03-26 2008-10-02 National Semiconductor Corporation Isolated solder pads
KR101041199B1 (ko) * 2007-07-27 2011-06-13 엔지케이 인슐레이터 엘티디 세라믹 성형체, 세라믹 부품, 세라믹 성형체의 제조 방법및 세라믹 부품의 제조 방법
US7705476B2 (en) * 2007-11-06 2010-04-27 National Semiconductor Corporation Integrated circuit package
US7619303B2 (en) * 2007-12-20 2009-11-17 National Semiconductor Corporation Integrated circuit package
US20090160039A1 (en) * 2007-12-20 2009-06-25 National Semiconductor Corporation Method and leadframe for packaging integrated circuits
US8642394B2 (en) * 2008-01-28 2014-02-04 Infineon Technologies Ag Method of manufacturing electronic device on leadframe
US7928541B2 (en) 2008-03-07 2011-04-19 Kobe Steel, Ltd. Copper alloy sheet and QFN package
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
JP5183572B2 (ja) * 2009-06-08 2013-04-17 株式会社三井ハイテック リードフレーム及び半導体装置
CN102142419B (zh) * 2010-02-03 2013-04-10 亿光电子工业股份有限公司 双边导线架结构
KR101778832B1 (ko) * 2010-11-02 2017-09-14 다이니폰 인사츠 가부시키가이샤 Led 소자 탑재용 리드 프레임, 수지 부착 리드 프레임, 반도체 장치의 제조 방법 및 반도체 소자 탑재용 리드 프레임
JP5899614B2 (ja) * 2010-11-26 2016-04-06 大日本印刷株式会社 リードフレームおよびリードフレームの製造方法
EP2523211B1 (en) * 2011-05-10 2019-10-23 Nexperia B.V. Leadframe and method for packaging semiconductor die
JP5940257B2 (ja) * 2011-08-01 2016-06-29 株式会社三井ハイテック リードフレーム及びリードフレームの製造方法並びにこれを用いた半導体装置
US20140131086A1 (en) * 2011-09-06 2014-05-15 Texas Instuments Incorporated Lead Frame Strip with Half (1/2) Thickness Pull Out Tab
JP6319644B2 (ja) * 2013-10-01 2018-05-09 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置の製造方法
JP6406787B2 (ja) * 2014-10-23 2018-10-17 株式会社三井ハイテック リードフレーム及びその製造方法
JP6518547B2 (ja) * 2015-08-07 2019-05-22 新光電気工業株式会社 リードフレーム、半導体装置及びリードフレームの製造方法
JP6107995B2 (ja) * 2016-03-10 2017-04-05 大日本印刷株式会社 リードフレームおよびリードフレームの製造方法
JP6603169B2 (ja) * 2016-04-22 2019-11-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP6399126B2 (ja) * 2017-03-07 2018-10-03 大日本印刷株式会社 リードフレームおよびリードフレームの製造方法
JP6631669B2 (ja) * 2018-09-05 2020-01-15 大日本印刷株式会社 リードフレームおよびリードフレームの製造方法
JP7231382B2 (ja) * 2018-11-06 2023-03-01 ローム株式会社 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2632528B2 (ja) * 1988-02-08 1997-07-23 新光電気工業株式会社 リードフレーム
US6448633B1 (en) * 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
JP2001168223A (ja) * 1999-12-07 2001-06-22 Fujitsu Ltd 半導体装置
JP2001320007A (ja) 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
JP3704304B2 (ja) * 2001-10-26 2005-10-12 新光電気工業株式会社 リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100435329C (zh) * 2003-06-23 2008-11-19 大动力公司 微引线框封装及制造微引线框封装的方法
CN100446234C (zh) * 2003-11-19 2008-12-24 罗姆股份有限公司 引线框的制造方法及使用该方法的半导体装置的制造方法
CN100345293C (zh) * 2004-05-13 2007-10-24 松下电器产业株式会社 半导体装置及半导体装置的制造方法
CN101308831B (zh) * 2007-05-17 2010-06-09 南茂科技股份有限公司 用于无引线封装的引线框及其封装结构
CN102202827A (zh) * 2010-07-20 2011-09-28 联发软件设计(深圳)有限公司 用于多列方形扁平无引脚芯片的预上锡方法以及返修方法
WO2012009848A1 (en) * 2010-07-20 2012-01-26 Mediatek (Shenzhen) Inc. Pre-solder method and rework method for multi-row qfn chip
CN102064144A (zh) * 2010-11-10 2011-05-18 日月光半导体制造股份有限公司 四方扁平无引脚封装及其制作方法

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