CN1090220C - 供晶片用的粘合片及使用该粘合片制备半导体器件的工艺 - Google Patents

供晶片用的粘合片及使用该粘合片制备半导体器件的工艺 Download PDF

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CN1090220C
CN1090220C CN94104848A CN94104848A CN1090220C CN 1090220 C CN1090220 C CN 1090220C CN 94104848 A CN94104848 A CN 94104848A CN 94104848 A CN94104848 A CN 94104848A CN 1090220 C CN1090220 C CN 1090220C
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irradiation
slaking
wafer
chip
adhesive sheet
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CN1101367A (zh
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雨海正纯
妹尾秀男
江部和义
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Lintec Corp
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Lintec Corp
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Abstract

本发明公开了一种包括一衬底膜以及形成于其上的一种可辐照熟化的粘合层的供晶片用的粘合片,该粘合片用于半导体器件的制备工艺,所制备的半导体器件具有芯片背面的一部分或全部与模压树脂连接,它能防止外包装裂缝的出现,因而提高了半导体器件的可靠性。

Description

供晶片用的粘合片及使用该粘合片制备半导体器件的工艺
本发明涉及一种供半导体晶片(下文简称“晶片”)用的粘合片及使用该粘合片的制备一种半导体器件的工艺。更具体地说,本发明涉及一种粘合片,它被使用于一种晶片上将晶片固定于其上,而该晶片则业已经受过在制备半导体器件的工艺中的旨在将晶片切成芯片元件(以下简称“芯片”)的晶片加工过程。所述半导体器件具有这样的结构,即芯片背面的一部分全部与包装模压树脂(封装树脂)连接,本发明也涉及使用该粘合片的半导体器件制备工艺。
随着存储器的更高的集成化,用户最近对半导体器件提出了许多要求,例如高速度的响应,降低电力消耗,扩展输出字码结构及扩大外包装的变化。为了应付这些不同的要求,应灵活地进行外包装设计。
为了满足上述要求,提出了LOC(铅在芯片上)结构的半导体器件,该结构在“Nikkei精密器件”(pp.89-97,February,1991)和日本专利公开公布号246125/1990中有描述。LOC结构有许多优点,譬如将尺寸降到最小,高速度的响应,噪声降低及容易安置,因此据说LOC结构被最显著地选用于大规模半导体器件,而后者可望很有发展前景。
在LOC结构中(如图7所示),作为半导体器件铅架(以下简称“铅架”)的内部复合铅层固定在其上已形成有线路的芯片的表面,其办法是使用绝缘带,后者使内部铅层与芯片绝缘,而内铅层与芯片则通过一焊线得以电连接。半导体器件用一种模压树脂封装,芯片的背面与模压树脂连接。
LOC结构具有如上所述的许多优点,但该结构含有必须解决的问题,因为它与传统的外包装结构截然不同。必须解决的问题之一是由于芯片和模压树脂之间的分离所造成的可靠性的下降,外包装出现裂缝等等。
由于外包装出现裂缝等等所导致的可靠性的下降并不是具有LOC结构的半导体器件的固有问题,它是所有具有如图8到9所示结构的半导体器件所具有的一个非常严重的问题,在这些结构中芯片背面的一部分或全部与模压树脂相接。图8所示的一种具有如此结构的半导体器件其冲模垫有一条缝。图9所示的半导体器件具有COL(芯片在铅的上面)结构。
对于芯片和模压树脂之间的间隙或出现外包装裂缝的机理至今有过各种各样的报道。
这些现象的机理之一是湿气侵入IC外包装。
湿气侵入IC外包装的途径可概括地分为以下几种:
(1)通过铅架和树脂之间的界面而侵入,
(2)通过树脂和填充在树脂中的垫料之间的界面而侵入,以及
(3)通过树脂块而侵入。
这些侵入是由毛细作用或扩散作用造成的,当放置IC外包装的环境温度或湿度升高时,IC外包装更容易吸收湿气。此外,当环境湿度升高时,(湿气在初始阶段的扩散速率变得更高,湿气的吸收更快地达到其饱和点。例如,有一则报道说,当IC外包装放置在85℃和85%RH(RH:相对湿度)的环境中任其吸收湿气时,在大约168小时后湿气的吸收达到其饱和点的80~90%。并且即使在常温和75%RH这样的通常大气下,湿气依然容易渗透进IC外包装的模压树脂材料,例如一种环氧树脂。
在诸如SOJ或QFP之类的IC外包装中,焊接封口一般用IR回流法连接,其中热是由红外线产生的或用蒸汽回流法,其中将一种惰性液体蒸发而IC外包装则被露置于高温蒸气中,因为这两种回流方法对大批生产都适用。在IR回流法即前一种方法中,IC外包装被露置于240~250℃高温中,在回流操作中如上文所述的侵入IC外包装内部的湿气因受高温而猛烈膨胀,因而水蒸汽压作用于环氧树脂和铅架之间的界面,产生界面间的间隙。结果便产生外包装裂缝。
即使外包装在常湿下放置168个小时也能经常观察到由IR回流法产生的外包装裂缝,虽然随包装中的铅架形状,芯片的表面积等而定。
促进界面间隙的一个原因是用于封装外包装的树脂材料,例如环氧树脂,和芯片的接触面之间的粘合强度降低。粘合强度很大程度上受被粘物表面清洁度的影向。例如,粘合强度即使对于存在于被粘物表面的埃数量级厚度的异物也是非常敏感的,会使粘合强度降低,从而容易造成湿气侵入或滞留于外包装内,最终导致外包装裂缝的产生。
顺便提一句,通常生产的半导体硅晶片,砷化镓晶片等等的直径相对较大,晶片被切割成芯片,然后这些芯片被传送至随后的装配段。这时半导体晶片要经历这样的操作,如切割,淋洗,干燥,以及射线辐照处理以使粘合片的辐照熟化粘合层熟化至一种能使半导体晶片粘附于粘合片的状态。然后,如有必要,进行一次合片的膨胀操作,随后进行芯片的收拾操作及装配。
打算用于晶片的各加工阶段,从切割阶段到收拾阶段的粘合片要求具有足够的粘合力以便从切割阶段到膨胀阶段使晶片和/或芯片保持在其上面,但在收拾阶段,仅要求粘合片保持这样程度的粘合力即在收拾到的晶片芯片上无粘合剂残存。上述的用于晶片的粘合片,例如在日本专利公布号56112/1989中所叙述的粘合片,已被广泛使用,毫无疑问它们也能用于传统型半导体器件的制备上。
然而,在制备具有芯片背面的一部分或全部与模压树脂连接的结构的半导体器件时,可观察到出现外包装裂缝的麻烦,因此降低了半导体器件的可靠性。
本发明是基于以往工艺中采用的一些先前技术而形成的,而本发明的一个目的是为晶片提供一种粘合片(下文中称为“晶片粘合片”),它用于制备具有这样一种结构的半导体器件,即芯片背面的一部分或全部与模压树脂连接,它能防止外包装裂缝的出现因而提高半导体器件的可靠性。本发明的另一个目的是提供一种使用该粘合片的制备半导体器件的工艺。
本发明的供晶片用的粘合片包括一衬底膜和形成于其上的可辐照熟化的粘合层。所述粘合片被使用于制备半导体器件的工艺中,后者包括下列工序:将晶片的背面粘附于可辐照熟化的粘合层上而该晶片的正面则已形成有线路;将晶片切割成芯片;用射线辐照可辐照熟化的粘合层使所述粘合层熟化;必要时使粘合片膨胀让芯片相互分开;然后收拾芯片,将芯片装配在铅架上;焊接并模压(包封)成这样的结构即芯片背面的一部分或全部与外包装模压树脂连接。此中,可辐照熟化的粘合层由按重量计的100份丙烯酸类粘合剂(由一种丙烯酸酯和一种含OH基的可聚合的单体的共聚物所组成)和50-200份具有两个或两个以上不饱和键的可辐照聚合的化合物所组成,又,可辐照熟化的粘合层经射线辐照熟化后其弹性系数不小于1×109dyn/cm2
本发明的制备半导体器件的工艺使用一种供晶片用的粘合片,该粘合片包括一衬底膜和形成于其上的可辐照熟化的粘合层,该粘合层由按重量计的100份丙烯酸型粘合剂(由一种丙烯酸酯和一种含OH基的可聚合的单体的共聚物组成)和以重量计的50-200份具有两个或两个以上不饱和键的可辐照聚合的化合物所组成,且经射线辐照熟化后其弹性系数不小于1×109dyn/cm2,又该工艺包括下述各工序:将晶片的背面粘附在可辐照熟化的粘合层上,晶片的正面则已形成有线路;将晶片切割成芯片;用射线辐照可辐照熟化的粘合层以熟化所述粘合层;必要时使粘合层膨胀让芯片相互分开;然后收拾芯片;将芯片装配在铅架上;焊接及模压(包封)成这样的结构即芯片背面的一部分或全部与外包装模压树脂连接。
在本发明中,可辐照聚合的含有两个或两个以上不饱和键的化合物的按重量计的20-80%最好是含有四个或四个以上不饱和键的那些可辐照聚合的不饱和化合物。
图1是本发明的一种供晶片用的粘合片的剖面示意图。
图2是本发明的另一种供晶片用的粘合片的剖面示意图。
图3说明一种情况,此中一晶片粘附于供晶片用的粘合片上。
图4说明一种情况,此中晶片被切割成芯片,粘合片被膨胀,以及用射线辐照粘合片。
图5说明芯片的另一个收拾工序。
图6说明芯片的另一个收拾工序。
图7是一种具有LOC结构的半导体器件的剖面图。
图8是一种具有这样的结构即其冲模垫有一条缝的半导体器件的剖面图。
图9是一种具有COL(芯片在铅的上面)结构的半导体器件的剖面图。
下文对本发明的供晶片用的粘合片及使用该粘合片的半导体器件的制备工艺作详细描述。
如图1-6所示,本发明的供晶片用的粘合片1包括衬底膜2及施于其上的可辐照熟化的粘合层。粘合片1用于具有如下结构的半导体器件的制备,该结构为芯片背面的一部分或全部与模压树脂连接。该工艺包括如下工序:将已往加工过的晶片粘附在可辐照熟化的粘合层3上,将处于此种情况下的晶片切割成复合芯片,清洗,干燥,对粘合片1中的可辐照熟化的粘合层3进行辐照处理,使该粘合层熟化以降低粘合层的粘合力,必要时膨胀粘合片使芯片相互分开,然后从可辐照熟化的粘合层收拾芯片,将收得的芯片装配在一个给定的支撑衬底上,譬如一个铅架上,最后用树脂进行模压。
正如可从图1的剖面图看到的,本发明的供晶片用的粘合片1包括衬底膜2和施于衬底膜表面的可辐照熟化的粘合层。在使用该粘合片前,最好在可辐照熟化的粘合层3上使用一隔离片4以保护粘合层3,如图2所示。
本发明的供晶片用的粘合片可制成任何形状,例如带状,标鉴状或其它形状。适合于用作衬底膜2者为具有优良耐水性和耐热性的材料,据此,特别适用的是合成树脂薄膜。以后将会提到,本发明的供晶片用的粘合片是用诸如电子束(EB)或紫外线(UV)加以辐照的,当粘合片用EB加以辐照时,衬底膜不必是透明的,而当用UV加以辐照时,则必须是透明的,虽然可以是有色的。
可用作衬底膜2的合成树脂薄膜为聚乙烯,聚丙烯,聚氯乙烯,聚对苯二甲酸乙二酯,聚对苯二甲酸丁二酯,聚丁烯,聚丁二烯,聚氨基甲酸乙酯,是聚甲基戊烯,乙烯/醋酸乙烯酯共聚物,乙烯/(甲基)丙烯酸共聚物,乙烯/(甲基)丙烯酸甲酯共聚物,乙烯/(甲基)丙烯酸乙酯共聚物等等。这些薄膜的层压制件也是可以使用的。衬底膜2的厚度通常为10-300μm,较好的为50~200μm。
在晶片切割后粘合片需膨胀处理的情况下,最好选用一种横向和纵向具有可延伸性的合成树脂薄膜例如聚氯乙烯薄膜或常用的聚乙烯薄膜作为衬底膜。
本发明的供晶片用的粘合片包括上述衬底膜2和形成在衬底膜2上的可辐照熟化的粘合层3。可辐照熟化粘合层3经用射线辐照熟化后其弹性系数不小于1×109dyn/cm2,较好的为1×109到1×1010dyn/cm2
此处所述的弹性系数用下列方法测定。那就是,制备一小片构成粘合层3的粘合剂样品,其长度为50mm,宽4mm,厚0.2mm。将该样品置于80w/cm的高压汞灯下并用射线辐照1秒种使其熟化。经此熟化后,用一台粘弹性测试装置(由Orientic K.K生产的Rheovibron DDV-II-EP)测定样品在3.5Hz时的弹性系数从而得到弹性系数曲线图,从曲线图求出25℃时的值,作为粘合层的弹性系数。
在衬底膜2上的可辐照熟化的粘合层3包括一种粘合剂和一种可辐照聚合的化合物。适用的粘合剂为由一种丙烯酸酯和一种含OH基的可聚合的单体的共聚物所组成的丙烯酸类粘合剂。丙烯酸类粘合剂是共聚物,它们以含由丙烯酸酯衍生的重复单元和由含OH基的可聚合的单体衍生的重复单元为其主要的构成单元。在共聚物中,含OH基的可聚合的单体的量按摩尔计为0.5-30%,较好的为8~30%,更好的为20~30%。
适用的丙烯酸酯的实例包括含1~10个碳原子的烷基醇的丙烯酸酯和含1~10个碳原子的烷基醇的甲基丙烯酸酯。
适用的含OH基的单体的实例包括丙烯酸-2-羟乙酯,甲基丙烯酸-2-羟乙酯,丙烯酸羟丙酯和甲基丙烯酸羟丙酯。其中较好的为丙烯酸-2-羟乙酯和甲基丙烯酸-2-羟乙酯。
由这些单体共聚而得的共聚物所具有的分子量为1.0×105到10.0×105,较好的为4.0×105到8.0×105
除了上述的构成单元外,丙烯酸粘合剂还可包含其它构成单元例如由酯酸乙烯酯,丙烯腈,乙烯基烷基醚等等所衍生者,如果本发明的目的不受影响的话。
丙烯酸类粘合剂的粘合力和内聚力可任意地由一种交联剂所决定。交联剂的实例包括多元异氰酸酯化合物,多元环氧化合物,多元氮丙啶化合物和螫形化合物。多元异氰酸酯化合物的具体实例包括二异氰酸甲代亚苯酯,二异氰酸二苯甲烷酯,二异氰酸亚己酯,二异氰酸异佛尔酮酯及其加合物。多元环氧化合物的具体实例包括乙二醇二缩水甘油醚和对苯二甲酸二缩水甘油酯。多元氮丙啶化合物的具体实例包括三-2,4,6-(1-吖丙啶基)-1,3,5-三嗪,三〔1-(2-甲基)-吖丙啶基〕氧膦和六〔1-(2-甲基)-吖丙啶基〕三偶磷三嗪。螫合物的具体实例包括乙酰乙酸乙酯二异丙醇铝和三(乙酰乙酸乙酯)铝。
供可辐照熟化的粘合层3使用的可辐照聚合的化合物,可以是广泛使用的低分子量的化合物,它们的分子中至少有两个可光照聚合的碳-碳双键以便能在光辐照下形成三维网状结构,如在日本专利公开公布号196956/1985和223139/1985中所描述者。这种低分子量化合物的具体实例包括三丙烯酸三羟甲基丙烷酯,四丙烯酸四羟甲基甲烷酯,三丙烯酸季戊四醇酯,四丙烯酸季戊四醇酯,五丙烯酸双季戊四醇单羟基酯,六丙烯酸双季戊四醇酯,二丙烯酸1,4-丁二醇酯,丙烯酸1,6-己二醇酯,二丙烯酸聚乙二醇酯和商品供应的丙烯酸低酯。
除上述的丙烯酸酯化合物外,丙烯酸酯氨基甲酸酯低聚物也能用作可辐照聚合的化合物。丙烯酸酯的氨基甲酸酯低聚物可通过下述反应制备:将聚酯或聚醚型多羟基化合物与多元异氰酸酯化合物例如二异氰酸2,4-甲亚苯,二异氰酸2,6-甲亚苯酯,二异氰酸1,3-二甲苯酯,二异氰酸1,4-亚二甲苯酯及二异氰酸4,4-二苯甲烷酯进行反应,从而得到异氰酸酯氨基甲酸酯预聚物,然后将该预聚物与含有羟基的丙烯酸酯或甲基丙烯酸酯反应,例如与丙烯酸2-羟基乙酯,甲基丙烯酸2-羟基乙酯,丙烯酸2-羟基丙酯,甲基丙烯酸2-羟基丙酯,丙烯酸聚乙二醇酯和甲基丙烯酸聚乙二醇酯进行反应。
这些丙烯酸酯氨基甲酸酯低聚物中,那些分子量在3,000-30,000,较好的为3,000-10,000,更好的为4,000-8,000,特别优先被采用,因为含这些丙烯酸酯氨基甲酸酯低聚物的粘合剂在芯片收拾工序中不会粘附在芯片背面,即使晶片的背面是粗糙的。而且,丙烯酸酯氨基甲酸酯低聚物较好的是至少含两个碳-碳双键,更好的是含两个碳-碳双键(即2-功能团的)。并且,当用丙烯酸酯氨基甲酸酯低聚物作为可辐照聚合的化合物时,与日本专利公开公布号196956/1985中所述的使用那些仅仅在分子中含至少两个可光照聚合的碳-碳双键的低分子量化合物相比,能得到一种极其优良的粘合片。换句话说,得到的粘合片在射线辐照以前具有高的粘合力,但于辐照后则该片的粘合力降低至这样一种程度即在芯片收拾工序中芯片的背面无任何粘合剂残存。
在本发明中,优选地将多种可辐照聚合的化合物联合使用。例如,在具有两个或两个以上不饱和键的可辐照聚合的化合物中应有按重量计约约20-80%较好的为约30-70%,为含有四个或四个以上不饱和键者。含四个或四个以上不饱和键的可辐照聚合的化合物的具体实例包括
四季戊四醇酯丙烯酸,
四甲基丙烯酸1,6-双(氨基甲酸甘油酯)己酯(1),
Figure C9410484800121
四甲基丙烯酸双(氨基甲酸甘油酯)异佛尔酮酯(2)。
Figure C9410484800122
及四甲基丙烯酸双(氨基甲酸甘油酯)甲苯酯(3)。
Figure C9410484800131
当这些含四个或四个以上不饱和键的可辐照聚合的化合物的用量以重量计为以可辐照聚合的化合物为100%计的20-80%时,可辐照熟化的粘合层足可被射线辐照而熟化,且粘合剂的内聚力并不降低。
又,特别较好是,相互联合使用含两个或两个以上不饱和键的可辐照聚合的化合物,此中,存在于含两个或两个以上不饱和键的可辐照聚合的化合物总量中的含四个或四个以上不饱和键的化合物用量按重量计为20-80%,较好的为30-70%,含六个或六个以上不饱和键的化合物用量按重量计为20-60%,较好的为30-50%。含六个或六个以上不饱和键的可辐照聚合的化合物的实例包括:
六丙烯酸双季戊四醇酯,
六甲基丙烯酸双季戊四醇酯,
六丙烯酸1.6-双(氨基甲酸季戊四醇酯己酯)(4),(CH2=CH-COOCH2)3CCH2OCONH-C6H12-NHCOOCH2C(CH2OCOCH=CH2)3
                                                     (4)
六丙烯酸双(季戊四醇氨基甲酸酯)异佛尔酮酯(5),
Figure C9410484800132
六丙烯酸双(季戊四醇氨基甲酸酯)甲苯酯(6),
Figure C9410484800133
以下给出特别优选使用的可辐照聚合的化合物组合的突例,但本发明能使用的组合决不限于这些实例。
1.2-官能团的丙烯酸酯氨基甲酸酯低聚物和4-官能团的四丙烯酸季戊四醇酯的组合。
2.2-官能团的丙烯酸酯氨基甲酸酯低聚物和6-官能团的六丙烯酸双季戊四醇酯的组合。
3.2-官能团的丙烯酸酯氨基甲酸酯低聚物和六丙烯酸双(氨基甲酸季戊四醇氨酯)己酯的组合。
关于粘合氨层中丙烯酸型粘合剂和可辐照聚合的化合物的比例,以丙烯酸粘合剂为100份计,所用的可辐照聚合的化合物的量按重量计通常为50-200份,较好的为50-150份,特别好的为70-120份。含按此比例的丙烯酸型粘合剂和可辐照聚合的化合物的粘合片具有高的初始粘合力,并且,经射线辐照后该初始粘合力大大降低,所以能轻易地将芯片从粘合片收拾到。
如果可辐照聚合的化合物的量按重量计小于50份,则化合物经射线辐照熟化后会有大量粘合剂粘附在芯片的背面,这样当用树脂封成外包装时会出现裂纹。另一方面,如果可辐照聚合的化合物的量按重量计大于200份,则粘合剂的内聚力降低,而导致另一个问题(即粘合片与架子脱开),虽然能避免出现外包装裂纹。
供晶片1用的粘合片,包括衬底膜2和如上所述的可辐照熟化的粘合层3,在辐照以前对被粘物具有足够的粘合力但经射线辐照后粘合力明显减弱。更明确地说,射线辐照以前,粘合片对-已经镜面处理的不锈钢具有例如不小于200g/25mm的粘合力,但经射线辐照后粘合力减小到不大于20g/25mm。
如果需要,除了上述的粘合剂及可辐照聚合的化合物以外,可辐照熟化的粘合层3还可含一种可辐照显色的化合物(在辐照时能显出颜色的化合物)。由于在可辐照熟化的粘合层3中加入了辐照显色化合物,粘合片经射线辐照后显色,所以在用一光敏器检测芯片时检测精确度就得以提高,从而避免了在收拾芯片的操作中可能发生的失误。此外,能得到这样一种好处,那就是,能立刻直观确定粘合片是否已被射线辐照过。
可能辐照显色的化合物是那些辐照前无色或淡色但辐照后显出颜色的化合物,这种化合物的较好的实例是隐色染料。较好的能用的是那些常用的隐色染料,例如三苯甲烷类,荧烷类,吩噻嗪类,金胺类及螺吡喃类染料。这些染料的具体实例包括:3-〔N-(对甲苯氨基)〕-7-苯胺基荧烷,3-〔N-(对甲苯基)-N-甲氨基〕-7-苯胺基荧烷,3-〔N-(对甲苯基)-N-乙氨基〕-7-苯胺基荧烷,3-二乙氨基-6-甲基-7-苯胺基荧烷,结晶紫内酯,4,4′,4″-三(二甲氨基)三苯甲醇及4,4′,4″-三(二甲氨基)三苯甲烷。
较好地与上述隐色染料配合使用的是那些常用的显色剂,例如苯酚甲醛树脂的初始聚合物,芳香羧酸衍生物及电子接受体,例如,活性土。为了改变颜色的色调,也可将各种已知的颜色形成物与之配合使用。
可将能辐照显色的化合物以在有机溶剂中的溶液形式或以细颗粒形式掺入至可辐照熟化的粘合层中。被加入至可辐照熟化的粘合层中的化合物数量的范围通常按重量计为0.01-10%,较好的为0.5-5%。如果该量超过以重量计的10%,粘合片被辐照时,射线被化合物吸收过多,因此有时可辐照熟化的粘合层熟化不充分。另一方面,如果化合物的量按重量计为小于0.01%,则粘合片在辐照时不能充分显色,因此在芯片收拾操作中很易出差错。
在某些情况下,可辐照熟化的粘合层3除了含上述的粘合剂及可辐照聚合的化合物以外,还可含光散射无机化合物粉末。通过在可辐照熟化的粘合层3中掺入光散射无机化合物粉末,即使在晶片的被粘住的表面由于种种原因而已经变灰或变黑时,粘合层经射线例如紫外线辐照后其粘合力显著减小,即使在晶片表面的已变灰或变黑的部分也是如此,因此在芯片收拾工序中芯片背面不再有粘合剂残存,而粘合层在辐照以前却具有足够的粘合力。
上文提到的光散射无机化合物是当其被诸如紫外线(UV)或电子束(EB)之类的射线辐照时能无规则地反射射线的化合物。光散射无机化合物粉末的实例包括二氧化硅粉末,氧化铝粉末,硅铝粉末和云母粉末。作为光散射无机化合物。那些几乎能完全反射上述射线的为优先选用者,但那些在一定程度上吸收射线的也能使用。
光散射无机化合物较好的是呈粉末形式,其颗粒直径为1-100μm,较好的为约1-20μm。在可辐照熟化的粘合层中,所用光散射无机化合物的量按重量计需为0.1-10%,较好的为1-4%。如果可辐照熟化的粘合层中的光散射无机化合物的用量按重量计超过10%,有时会降低可辐照熟化的粘合层的粘合力,另一方面,如果该化合物用量按重量计小于0.1%,经辐照后的粘合层中的对应于晶片表面变灰或变黑部分的粘合力未被足够减小,因此,在芯片收拾工序中粘合剂会粘附及残留在芯片背面。
如上所述,通过使用由含有光散射无机化合物粉末的可辐照熟化的粘合层组成的为粘合片,即使由于种种原因被粘住的晶片表面已变灰或变黑,经射线辐照后的粘合层的粘合力,即使在对应于晶片面变灰或变黑的那些部分也明显减小。以下所述者被认为是造成这一点的理由。那就是,本发明的粘合片1具有可辐照熟化的粘合层3,而当该可辐照熟化的粘合层3经射线辐照时,粘合层3中所含的可辐照聚合的化合物被熟化而降低了粘合层的粘合力。然而,晶片表面的有些部分有时会由于种种原因而变灰或变黑。当可辐照熟化的粘合层3被射线辐照时,射线穿过可辐照熟化的粘合层3到达晶片表面。然而,如果晶片表面有变灰或变黑部分,射线被这些部分吸收而不反射。因此,使用于熟化可辐照熟化的粘合层3的射线被与晶片表面变灰或变黑部分相对应的部分所吸收,所以可辐照熟化的粘合层的熟化变成不充分的,粘合层的粘合力也就没有明显减小。因此,可以认为,在芯片收拾工序中粘合剂粘附和残留在芯片背面。
然而当光散射无机化合物粉末掺入可辐照熟化的粘合层3中时,射线在到达晶片表面之前被化合物无规则地反射从而改变其方向。因为这个缘故,即使在晶片表面存在变灰或变黑部分,无规则地反射的射线足以穿透至对应于晶片表面变灰或变黑部分的粘合层的上层区域,因此粘合层的相应部分受到足够的熟化。通过在可辐照熟化的粘合层中掺入光散射无机化合物粉末,即使当晶片表面由于种种原因存在变灰或变黑部分,对对应于晶片表面变灰或变黑部分的粘合层部分的熟化不会变得不充分,因而在芯片收拾工序中不会有粘合剂粘附和残留在芯片背面。
在本发明中,磨粒可分散在衬底膜中。磨粒的颗粒直径为0.5到100μm,较好的为1到50μm,莫氏硬度为6到10,较好的为7到10。这些磨粒的具体实例包括绿色金刚砂,人造刚玉,光学金刚砂,白色铝氧粉,碳化硼,氧化铬(III),氧化铈和金刚石粉末。这些磨粒较好的是无色或白色的。磨粒在衬底膜2中的用量按重量计为0.5到70%,较好的为5到50%。当切割刀以下这样的方式使用即刀刃经过晶片到达衬底的方式使用时尤以使用磨粒为好。
由于衬底膜中加入了磨粒,即使切割刀进入到衬底膜且粘合剂粘在刀刃上,也能由于磨粒的到磨擦作用而将粘合剂轻易地除去。
而且,当用UV辐照熟化粘合层时,上述的粘合层可含有一种UV熟化引发剂,以缩短用UV辐照的聚合熟化的时间和使UV辐照剂量降至最低限度。
这些UV熟化引发剂的实例包括苯偶姻,苯偶姻甲醚,苯偶姻乙醚,苯偶姻异丙醚,苄基二苯基硫化物,一硫化四甲基秋兰姆,偶氮二异丁腈,联苄基,联乙酰和β-氯蒽醌。
在本发明的半导体器件制备工艺中,把已经经过晶片加工的半导体晶片置于上述供晶片使用的粘合片上,然后在此状态下将晶片切割成芯片,以此制备半导体器件。
现将本发明的使用上述供晶片使用的粘合片的半导体器件制备工艺说明如下。
如果如图2所示在粘合片1的上面有一隔离片4,首先移去隔离片4,将粘合片1放置成使得可辐照熟化的粘合层在上面。如图3所示,将待切割的晶片A置于可辐照熟化的粘合层3的表面上。将晶片A在此状态下进行切割,如有需要则进行清洗和干燥。此时,在切割,清洗和干燥等每一操作中芯片将不会从粘合层1中脱落,因为可辐照熟化的粘合层3具有足够的粘合力使芯片粘附并保留在粘合片1上。
随后,将芯片从粘合片上收拾下来并将其装在一支撑衬底例如铅架上。如图4所示,在先于或与收拾操作同时,对粘合片1中的可辐照熟化的粘合层3用一电离辐射B,例如紫外线(UV)或电子束(EB),进行辐照,使可辐照熟化的粘合层3中所含的可辐照聚合的化合物进行聚合和熟化。当可辐照熟化的粘合层3中所含的可辐照聚合的化合物在射线辐照粘合层3时得以聚合和熟化时,粘合层中所含粘合剂的粘合力大大减小,只剩下很微弱的粘合力。
对粘合片1的辐照最好是从衬底膜空白的一面加以实施,在这一面,没有可辐照熟化的粘合层3在其上。所以,如前面所述,当使用的射线为UV时衬底膜2需具备光透射性,但当使用EB作辐照时衬底膜就不总需具备光透射性。
在所描述的方法中,对置有芯片A1,A2……的可辐照熟化的粘合层3进行照射以减小可辐照熟化的粘合层3的粘合力,然后如果需要以预定比例膨胀粘合层。通过膨胀粘合层,芯片之间的距离变宽,借此能容易地从粘合层收拾芯片。以后的工序可依照传统方法加以进行。如图5所示,用一根推棒5从衬底膜2的下侧往上推,推出需待收拾的每个芯片A1,A2……,用例如一个抽吸套筒6进行收拾,然后装在一个支撑衬底,例如一个铅架上。用这种方法收拾芯片A1,A2……,芯片能轻易地被收拾得到的芯片具有优良的品质,无任何污染。照射也可在收拾处加以进行。
并不总是需要在晶片A的整个表面进行一次性辐照,有时可以部分地进行,例如对仅仅与每一芯片A1,A2……相对应的衬底膜的部分进行辐照,辐照时用一辐照管从衬底膜2的背侧进行,以减小对应于辐照部分的粘合剂的粘合力,然后可用推棒5将芯片A1,A2……依次推上,随后收拾推上的每一片芯片。图6所示的是上述辐照方法的一种改进,其中推棒5是空心的,辐射源7置于推棒的空心部分,致使辐照和收拾操作可同时进行,这样,设备能简化且收拾操作所需的时间可缩短。
在本发明的半导体器件制备工艺中,将如上所得的芯片装在一个一定的支撑衬底,例如铅架上,然后根据传统方法用一模压树脂进行焊接及封装操作。如此制得的半导体器件可具有这样的结构,即芯片背面的一部分或全部与模压树脂连接,如图7到9所示。根据本发明的方法,能得到外包装不发生裂缝的半导体器件,因而可提高可靠性。
作为这里所用的模压树脂,较好的为树脂组合物,它们含以甲酚线型酚醛清漆型环氧树脂,萘型环氧树脂,联苯型环氧树脂或芳香族多官能型环氧树脂为主要组份,以添加剂如传统使用的硬化剂(例如,酚醛清漆),二氧化硅,碳和填料等。
本发明的供晶片使用的粘合片用于具有下列结构的半导体器件的制备,即芯片背面的一部分或全部与模压树脂相连接一种,典型的LOC结构。在使用粘合片时,已经经过晶片加工的一块晶片被粘附在粘合片上,然后将晶片切割成芯片。使用此芯片,具有上述结构的半导体器件被制成。根据本发明的工艺制成的半导体器件不会出现外包装裂纹。因而能提高制成品的可靠性。
                    实施例
以下参照实施例说明本发明,但应将其理解为本发明决不限于这些实施例。
在以下的实施例和对照实施例中,“弹性系数”和“外包装裂缝出现率”按下法进行评估。弹性系数
以一可辐照熟化的粘合剂制备一块长50mm,宽4mm及厚0.2mm的粘合剂小样。将该样品置于80w/cm的高压汞灯下并用射线辐照1秒钟使其熟化。熟化后,用一台粘弹性测试装置(由Orientic K.K生产的Rheovibron DDV-II-EP)测定样品在3.5Hz时的弹性数从而得到弹性系数曲线图,从曲线图查出在25℃时的值即为粘合剂的弹性系数。外包装裂缝出现率
切割以后,从经射线辐照过的粘合片收拾芯片。将芯片装在一铅架上,然后进行焊接,并在高压下用模压树脂(邻甲酚类环氧树脂)进行封装。随后将该模压树脂于175℃下加热放置5小时以制成含芯片的外包装。然后将此外包装任其在85℃及85%RH的氛围中放置504小时。然后对外包装进行IR回流处理(所需时间:1分钟)三次,并用SAT法(scanning acomostic tomography)对封装树脂裂缝的出现进行检测。测定所有受测外包装总数中含有裂缝的外包装数所占的百分数即为外包装裂缝出现率。
实施例1〔一种可辐照熟化的粘合剂的制备〕
将下列各物进行混合以制备一种可辐照熟化的粘合剂:按重量计的100份丙烯酸型粘合剂(丙烯酸羟乙酯和丙烯酸丁酯的共聚物,丙烯酸羟乙酯的含量为:按重量计为9%(按mol计为9.8%),按重量计的70份其分子量约为6,000的2-官能团的氨基甲酸酯丙烯酸酯低聚物(Dainichiseika Color and Chemicals有限公司有售),按重量计的30份4官能团的聚酯低聚物和按重量计的10份芳香族异氰酸酯(Toyo Ink有限公司有售)。
测试此可辐照熟化的粘合剂的弹性系数。结果示于表1。〔一种供晶片使用的粘合片的制备〕
在厚度为100μm的聚乙烯薄膜上涂敷以上制得的可辐照熟化的粘合剂,其用量为10g/m2,以形成一可辐照熟化的粘合层。在此可辐照熟化的粘合层上,将一厚度为38μm的经硅氧烷处理过的PET薄膜层压成片作为一隔离片,以制成一种供晶片用的粘合片。〔LOC结构的半导体器件的制备〕
上面得到的供晶片用的粘合片用一扁平架固定,将一块含有试验芯片的6时硅晶片粘附在粘合片上,将晶片切割成尺寸为12.2mm×21.3mm的芯片。用此芯片即可制得LOC封装结构的半导体器件。测试该半导体器件的外包装裂缝出现率。结果示于表1。
实施例2
重复实施例1的步骤,用按重量计的30份6-官能团的丙烯酸聚酯低聚物(Nippon Kayaku有限公司有售)取代按重量计的30份4-官能团的聚酯低聚物。结果示于表1。
实施例3
重复实施例1的步骤,用一种丙烯酸型粘合剂(丙烯酸羟乙酯和丙烯酸丁酸的共聚物,丙烯酸羟乙酯的含量按重量计为25%(按mol计为26.9%))取代在实施例1中所用的丙烯酸型粘合剂。
结果示于表1。
实施例4〔一种可辐照熟化的粘合剂的制备〕
混合下列各物,以制备一种可辐照熟化的粘合剂:按重量计的100份丙烯酸型粘合剂(丙烯酸羟乙酯和丙烯酸丁酯的共聚物,丙烯酸羟乙酯的含量:按重量计为25%(按mol计为26.9%),按重量计的70份分子量为约6,000的2-官能团的丙烯酸氨基酸酯低聚物(Dainichiseika Color and Chemicals有限公司有售),按重量计的30份6-官能团的聚酯低聚物(Nippon Kayaku有限公司有售)和按重量计的10份芳香族异氰酸酯(Toyo lnk有限公司有售)。
测定可辐照熟化的粘合剂的弹性系数。结果示于表1。
然后,重复实施例1的步骤,只是用此可辐照熟化的粘合剂取代实施例1中所用的可辐照熟化的粘合剂。
结果示于表1。对照实施例1
重复实施例1的步骤,只是用丙烯酸和丙烯酸丁酯的共聚物(丙烯酸含量按重量计为9%)作为丙烯酸型粘合剂,其用量按重量计为100份。结果示于表1。对照例2
重复实施例1的步骤,只是将2-官能团的丙烯酸氨基甲酸酯低聚物的用量改为按重量计的100份,并不用4-官能团的聚酯低聚物。结果示于表1。
               表1
  弹性系数 外包装裂缝出现率
    实施例1     3.8×109     0%
    实施例2     6.3×109     0%
    实施例3     4.0×109     0%
    实施例4     6.5×109     0%
对照实施例1     5.6×109     4%
对照实施例2     8.7×107     67%

Claims (8)

1.一种供晶片用的粘合片,包括:衬底膜和形成于其上的可辐照熟化的粘合层,其中的可辐照熟化的粘合层包括:由一种丙烯酸酯和可聚合的单体的共聚物构成的按重量计100份丙烯酸粘合剂和按重量计50-200份含两个或两个以上不饱和键的可辐照聚合的化合物,其特征在于所述可聚合的单体是含OH基的可聚合的单体,所述丙烯酸粘合剂中,来自含OH基的可聚合的单体单元的量为8-30摩尔%,所述可辐照熟化的粘合层经射线辐照熟化后其弹性系数不小于1×109dyn/cm2
2.如权利要求1所述的供晶片用的粘合片,其特征在于按重量计20到80%的含两个或两个以上不饱和键的可辐照聚合的化合物含四个或四个以上不饱和键。
3.如权利要求1或2所述的供晶片用的粘合片,其特征在于所述丙烯酸粘合剂中,来自含OH基的可聚合的单体单元的量为20-30摩尔%。
4.使用如权利要求1所述的粘合片的半导体器件的制备工艺,所述工艺包括下列步骤:将晶片的背面粘附到可辐照熟化的粘合层的上面,晶片的正面则已形成有一回路,将晶片切割成芯片,用射线辐照可辐照熟化的粘合层以熟化所述粘合层,然后收拾芯片,将芯片装配在铅架上,焊结并模压至这样一种结构即芯片背面的一部分或全部与外包装模压树脂连接。
5.如权利要求4所述的半导体器件制备工艺,其特征在于还包括在辐照步骤之后膨胀粘合片,使芯片相互分开的步骤。
6.如权利要求4或5所述的半导体器件制备工艺,其特征在于按重量计的20到80%的含两个或两个以上不饱和键的可辐照聚合的化合物含有四个或四个以上不饱和键。
7.如权利要求4或5所述的半导体器件制备工艺,其特征在于所述丙烯酸粘合剂中,来自含OH基的可聚合的单体单元的量为20-30摩尔%。
8.如权利要求6所述的半导体器件制备工艺,其特征在于所述丙烯酸粘合剂中,来自含OH基的可聚合的单体单元的量为20-30摩尔%。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515564B (zh) * 2008-02-18 2011-07-27 日东电工株式会社 具备切割膜和芯片焊接膜的膜

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19520238C2 (de) * 1995-06-02 1998-01-15 Beiersdorf Ag Selbstklebeband
US6342434B1 (en) 1995-12-04 2002-01-29 Hitachi, Ltd. Methods of processing semiconductor wafer, and producing IC card, and carrier
MY118036A (en) * 1996-01-22 2004-08-30 Lintec Corp Wafer dicing/bonding sheet and process for producing semiconductor device
US6007920A (en) * 1996-01-22 1999-12-28 Texas Instruments Japan, Ltd. Wafer dicing/bonding sheet and process for producing semiconductor device
KR20040000387A (ko) * 1996-10-08 2004-01-03 히다치 가세고교 가부시끼가이샤 접착제 및 양면 접착 필름
GB2320615B (en) * 1996-12-19 2001-06-20 Lintec Corp Process for producing a chip and pressure sensitive adhesive sheet for said process
US6312800B1 (en) 1997-02-10 2001-11-06 Lintec Corporation Pressure sensitive adhesive sheet for producing a chip
US6235387B1 (en) 1998-03-30 2001-05-22 3M Innovative Properties Company Semiconductor wafer processing tapes
JP3739570B2 (ja) 1998-06-02 2006-01-25 リンテック株式会社 粘着シートおよびその利用方法
US6331080B1 (en) 1998-07-15 2001-12-18 3M Innovative Properties Company Optical fiber connector using colored photocurable adhesive
JP3669196B2 (ja) * 1998-07-27 2005-07-06 日東電工株式会社 紫外線硬化型粘着シート
JP3410371B2 (ja) 1998-08-18 2003-05-26 リンテック株式会社 ウエハ裏面研削時の表面保護シートおよびその利用方法
JP3661444B2 (ja) 1998-10-28 2005-06-15 株式会社ルネサステクノロジ 半導体装置、半導体ウエハ、半導体モジュールおよび半導体装置の製造方法
MY140714A (en) * 1999-07-08 2010-01-15 Sunstar Engineering Inc Underfilling material for semiconductor package
JP4230080B2 (ja) * 2000-02-18 2009-02-25 リンテック株式会社 ウエハ貼着用粘着シート
US6372074B1 (en) * 2000-06-14 2002-04-16 Avery Dennison Corporation Method of forming a protective coating for color filters
KR100351705B1 (ko) * 2000-06-27 2002-09-11 한솔제지주식회사 다이싱테이프용 감광성 점착 조성물
US6759121B2 (en) * 2000-07-13 2004-07-06 3M Innovative Properties Company Clear adhesive sheet
US6472065B1 (en) * 2000-07-13 2002-10-29 3M Innovative Properties Company Clear adhesive sheet
TW497236B (en) * 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
US20030092246A1 (en) * 2001-10-11 2003-05-15 Wanat Stanley F. Assembly system for stationing semiconductor wafer suitable for processing and process for manufacturing semiconductor wafer
JP2003234359A (ja) * 2002-02-08 2003-08-22 Hitachi Ltd 半導体装置の製造方法
JP4115711B2 (ja) * 2002-02-14 2008-07-09 日東電工株式会社 フレキシブルプリント配線板固定用接着シート及びフレキシブルプリント配線板への電子部品の実装方法
JP4189156B2 (ja) * 2002-02-22 2008-12-03 株式会社トクヤマ チップ貼設シート
JP2004273895A (ja) * 2003-03-11 2004-09-30 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
DE112004000768B4 (de) * 2003-05-12 2015-07-23 Tokyo Seimitsu Co., Ltd. Verfahren zum Trennen eines plattenartigen Elements
FR2857502B1 (fr) * 2003-07-10 2006-02-24 Soitec Silicon On Insulator Substrats pour systemes contraints
JP2005051018A (ja) * 2003-07-28 2005-02-24 Sanyo Electric Co Ltd 半導体装置及びその製造方法
DE10340409B4 (de) * 2003-09-02 2007-05-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Trägerwafer und Verfahren zum Bearbeiten eines Halbleiterwafers unter Verwendung eines Trägerwafers
US20050249945A1 (en) * 2004-05-10 2005-11-10 Wen Kun Yang Manufacturing tool for wafer level package and method of placing dies
JP2006152141A (ja) * 2004-11-30 2006-06-15 Furukawa Electric Co Ltd:The 粘着テープ
DE102005055769A1 (de) * 2005-11-21 2007-05-24 Tesa Ag Verfahren zur temporären Fixierung eines polymeren Schichtmaterials auf rauen Oberflächen
JP5047556B2 (ja) * 2006-07-26 2012-10-10 リンテック株式会社 光学機能性フィルム貼合用粘着剤、粘着剤付き光学機能性フィルム及びその製造方法
JP5101111B2 (ja) * 2007-01-05 2012-12-19 日東電工株式会社 半導体基板加工用粘着シート
WO2009001492A1 (ja) * 2007-06-22 2008-12-31 Sumitomo Bakelite Co., Ltd. 接着フィルムおよびこれを用いた半導体装置
JP4318743B1 (ja) * 2008-10-07 2009-08-26 昭和高分子株式会社 紫外線硬化型再剥離性粘着剤組成物及びこれを用いた粘着シート
JP2011023396A (ja) * 2009-07-13 2011-02-03 Nitto Denko Corp 表面保護シート
JP5528169B2 (ja) * 2010-03-26 2014-06-25 東洋ゴム工業株式会社 研磨パッドおよびその製造方法、ならびに半導体デバイスの製造方法
EP2368955A1 (de) 2010-03-26 2011-09-28 Sika Technology AG Formgedächtnis-Material auf Basis eines Strukturklebstoffs
GB201012595D0 (en) 2010-07-27 2010-09-08 Zephyros Inc Oriented structural adhesives
JP5687897B2 (ja) * 2010-12-28 2015-03-25 日東電工株式会社 放射線硬化型粘着剤組成物及び粘着シート
JP2012227232A (ja) * 2011-04-15 2012-11-15 Denki Kagaku Kogyo Kk 加工用粘着シート及びそれを用いた板状材料の製造方法
JP6063796B2 (ja) * 2013-03-29 2017-01-18 積水化成品工業株式会社 帯電防止シート
US20160272849A1 (en) * 2013-03-29 2016-09-22 Sekisui Plastics Co., Ltd. Temporary fixing material
US10577523B2 (en) 2013-07-26 2020-03-03 Zephyros, Inc. Relating to thermosetting adhesive films
JP6334223B2 (ja) * 2014-03-26 2018-05-30 リンテック株式会社 粘着シート
CN104312456B (zh) * 2014-10-28 2016-03-30 成都纳硕科技有限公司 一种木质板材用紫外光固化胶及其制备方法
KR102335109B1 (ko) 2014-12-15 2021-12-03 삼성전자 주식회사 미세 패턴 형성 방법 및 이를 이용한 집적회로 소자의 제조 방법
JP6626254B2 (ja) * 2015-02-03 2019-12-25 株式会社テセック 半導体デバイス測定方法
KR102546307B1 (ko) 2015-12-02 2023-06-21 삼성전자주식회사 발광 소자 및 이를 포함하는 표시 장치
JP6917166B2 (ja) * 2017-03-15 2021-08-11 マクセルホールディングス株式会社 ダイシング用粘着テープ、ダイシング用粘着テープの製造方法、および半導体チップの製造方法
JP7035720B2 (ja) * 2018-03-29 2022-03-15 住友ベークライト株式会社 半導体基板加工用粘着テープ
DE102022100661A1 (de) 2022-01-12 2023-07-13 Forschungsverbund Berlin E.V. Verfahren und Vorrichtung zum Herstellen einer Halbleiterstruktur
CN115229671A (zh) * 2022-08-24 2022-10-25 关勒铭(湖州)晶体材料科技有限公司 一种基于固结磨料的新型红宝石高效研磨工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2221470A (en) * 1985-12-27 1990-02-07 Fsk Kk Adhesive sheet for semiconductor wafer processing
US4968559A (en) * 1985-02-14 1990-11-06 Bando Chemical Industries. Ltd. Pressure sensitive adhesive film with barrier layer
EP0439258A2 (en) * 1990-01-12 1991-07-31 Asahi Denka Kogyo Kabushiki Kaisha Actinic radiation-reactive pressure-sensitive adhesive composition

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4296542A (en) * 1980-07-11 1981-10-27 Presco, Inc. Control of small parts in a manufacturing operation
US5187007A (en) * 1985-12-27 1993-02-16 Lintec Corporation Adhesive sheets
DE3639266A1 (de) * 1985-12-27 1987-07-02 Fsk K K Haftfolie
FI88595C (fi) * 1986-08-01 1993-06-10 Lintec Corp Etikettpapper foer kopiering
US5281473A (en) * 1987-07-08 1994-01-25 Furakawa Electric Co., Ltd. Radiation-curable adhesive tape
DE3850451T2 (de) * 1987-07-08 1995-03-09 Furukawa Electric Co Ltd Strahlungsvernetzbare Klebestreifen.
US5149586A (en) * 1987-07-08 1992-09-22 Furukawa Electric Co., Ltd. Radiation-curable adhesive tape
MY103125A (en) * 1987-07-24 1993-04-30 Lintec Corp Cover tape for sealing chip-holding parts of carrier tape
JPH0715087B2 (ja) * 1988-07-21 1995-02-22 リンテック株式会社 粘接着テープおよびその使用方法
JP2683574B2 (ja) * 1988-08-08 1997-12-03 住友電気工業株式会社 電力ケーブルの接続部
JPH05206267A (ja) * 1992-01-29 1993-08-13 Fujitsu Ltd 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4968559A (en) * 1985-02-14 1990-11-06 Bando Chemical Industries. Ltd. Pressure sensitive adhesive film with barrier layer
GB2221470A (en) * 1985-12-27 1990-02-07 Fsk Kk Adhesive sheet for semiconductor wafer processing
EP0439258A2 (en) * 1990-01-12 1991-07-31 Asahi Denka Kogyo Kabushiki Kaisha Actinic radiation-reactive pressure-sensitive adhesive composition

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101515564B (zh) * 2008-02-18 2011-07-27 日东电工株式会社 具备切割膜和芯片焊接膜的膜

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EP0622833B1 (en) 1999-03-31
CA2122278A1 (en) 1994-10-29
EP0622833A1 (en) 1994-11-02
DE69417463T2 (de) 1999-08-19
JPH07135189A (ja) 1995-05-23
JP3410202B2 (ja) 2003-05-26
CA2122278C (en) 2005-04-12
CN1101367A (zh) 1995-04-12
US6297076B1 (en) 2001-10-02
DE69417463D1 (de) 1999-05-06
KR100284989B1 (ko) 2001-03-15
MY115305A (en) 2003-05-31
TW245825B (zh) 1995-04-21

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