CN1080928C - 半导体器件的平整方法 - Google Patents

半导体器件的平整方法 Download PDF

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Publication number
CN1080928C
CN1080928C CN96123330A CN96123330A CN1080928C CN 1080928 C CN1080928 C CN 1080928C CN 96123330 A CN96123330 A CN 96123330A CN 96123330 A CN96123330 A CN 96123330A CN 1080928 C CN1080928 C CN 1080928C
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CN
China
Prior art keywords
impurity
aforementioned
semiconductor device
flatted membrane
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN96123330A
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English (en)
Chinese (zh)
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CN1159076A (zh
Inventor
朴仁玉
郑永硕
金义式
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of CN1159076A publication Critical patent/CN1159076A/zh
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Publication of CN1080928C publication Critical patent/CN1080928C/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Chemical Vapour Deposition (AREA)
CN96123330A 1995-11-20 1996-11-20 半导体器件的平整方法 Expired - Fee Related CN1080928C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950042291A KR100262400B1 (ko) 1995-11-20 1995-11-20 반도체 소자의 평탄화방법
KR42291/95 1995-11-20

Publications (2)

Publication Number Publication Date
CN1159076A CN1159076A (zh) 1997-09-10
CN1080928C true CN1080928C (zh) 2002-03-13

Family

ID=19434734

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96123330A Expired - Fee Related CN1080928C (zh) 1995-11-20 1996-11-20 半导体器件的平整方法

Country Status (6)

Country Link
JP (1) JP2799858B2 (ja)
KR (1) KR100262400B1 (ja)
CN (1) CN1080928C (ja)
DE (1) DE19648082C2 (ja)
GB (1) GB2307344B (ja)
TW (1) TW442872B (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100256232B1 (ko) * 1997-06-30 2000-05-15 김영환 반도체소자의층간절연막형성방법
JP3229276B2 (ja) * 1998-12-04 2001-11-19 キヤノン販売株式会社 成膜方法及び半導体装置の製造方法
JP3824469B2 (ja) * 2000-04-03 2006-09-20 シャープ株式会社 固体撮像装置、及びその製造方法
KR100506054B1 (ko) * 2000-12-28 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US7226873B2 (en) * 2004-11-22 2007-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of improving via filling uniformity in isolated and dense via-pattern regions
KR20120098095A (ko) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 반도체장치 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237744A (ja) * 1990-02-14 1991-10-23 Matsushita Electron Corp 半導体装置の製造方法
JPH0469954A (ja) * 1990-07-11 1992-03-05 Toshiba Corp 半導体装置の製造方法
EP0519393A2 (en) * 1991-06-20 1992-12-23 Semiconductor Process Laboratory Co., Ltd. Method for planarizing a semiconductor substrate surface
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950006339B1 (ko) * 1991-11-19 1995-06-14 현대전자산업주식회사 표면결정성 석출물 발생방지를 위한 bpsg층 형성방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237744A (ja) * 1990-02-14 1991-10-23 Matsushita Electron Corp 半導体装置の製造方法
JPH0469954A (ja) * 1990-07-11 1992-03-05 Toshiba Corp 半導体装置の製造方法
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device
EP0519393A2 (en) * 1991-06-20 1992-12-23 Semiconductor Process Laboratory Co., Ltd. Method for planarizing a semiconductor substrate surface

Also Published As

Publication number Publication date
CN1159076A (zh) 1997-09-10
GB2307344A (en) 1997-05-21
TW442872B (en) 2001-06-23
DE19648082A1 (de) 1997-05-22
JPH1092826A (ja) 1998-04-10
DE19648082C2 (de) 2000-03-23
JP2799858B2 (ja) 1998-09-21
GB9624132D0 (en) 1997-01-08
GB2307344B (en) 2000-05-17
KR970030476A (ko) 1997-06-26
KR100262400B1 (ko) 2000-09-01

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Granted publication date: 20020313

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