GB2307344A - Method for planarization of semicondoctor device - Google Patents

Method for planarization of semicondoctor device Download PDF

Info

Publication number
GB2307344A
GB2307344A GB9624132A GB9624132A GB2307344A GB 2307344 A GB2307344 A GB 2307344A GB 9624132 A GB9624132 A GB 9624132A GB 9624132 A GB9624132 A GB 9624132A GB 2307344 A GB2307344 A GB 2307344A
Authority
GB
United Kingdom
Prior art keywords
layer
accordance
planarization
aver
thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9624132A
Other versions
GB2307344B (en
GB9624132D0 (en
Inventor
In-Ok Park
Yung-Seok Chung
Eui-Sik Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB9624132D0 publication Critical patent/GB9624132D0/en
Publication of GB2307344A publication Critical patent/GB2307344A/en
Application granted granted Critical
Publication of GB2307344B publication Critical patent/GB2307344B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Chemical Vapour Deposition (AREA)

Description

2307344 METHOD FOR PLANARIZATION OF SEMICONDUCTOR DEVICE
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to a method for the nlanarization of a semiconductor device, and more paricularly to a method canable of preventing dopants from precipitatncr during the flow nrocess of the deposited layer for the planarization.
n -- 1. - Description of the Related Art 7n the tra.nsis:ors, passive devices such as resistors, and a multilayer interconnection structure on the substrate are required. In the formation of the active device and passive device, the substrate surface can become uneven. Due to the high densification and high i=egration of the semiconductor device in recenz vears, the unevenness of the substrate surface has become conspicuous, and therefore more of a croblem. It becomes more difficult to form a highly precise fine oattern. In addition short of the nterco-.-inection and the like are also!-able to occur. To solve these - oroblems the techniaue for flattening the substrate surface s reauired.
Conventionally, a layer C.L insular_ing mar-erJ.a; such as sil---cn cxide is anclied over such uneven surfaces, to nermit, the ..or7nar-on of a more finely patterned layer onto the surface of a semiconductor devices, active devices such as i BAD ORIGINAL A0 non-planarized layer. This silicon dioxide layer, however, tends to conform to the underlying topography resulting in the creation of a nor-planar or st:enped surface. Acccrd-csl,;, it: is very difficulr to form the more finely patterned ajer on the uneven surface using a general lithography process.
Thus, there provided a glass material such as spin on glass (SOG), and a material containing boron and/or phosphorous such as boronhosr)hosilicate glass (3PSG), phosphosilicate glass (PSG) and bcrosilicate glass(3SW1) to be used for the formation of a p'anai:i-Jzed layer.
Amona these 1 avers for the planarization, a BPSG layer having boron concentration at 3-5 w-,; and phosr)horous concentration at 3-5 w?---'j 1s denosited on the substrate having the semiconductor devices ac a low temperature of 400-4500C. Then, a thermal flow process is performed at a temperature of 800-8500C, -immediately following the dewsition whereby a planarized surface is obtained. At this tme, as boron concentration in BPSG increases, the flow teT,r)erar-ure decreases. The dlegree of the planarizationare also z)ror)crt-onal to boron and phosphorous concentrar ions. in addition S:P5G clavs role in removing the topology existing, for example, between a gate electrode and a first metal -nterconnect-4o.-..
Re-.:-e--r--iJna to _Fig. i, a method for the clanar--'zaz-Jon between a =-lec::--ode and a firs-- --,iea7- inte--c7,n.nec-t-on using SPSCaccordlinz -o the conventional art, is described.
A zaze oxide 3, a aate elec--rode, and 'unction reQions are in and on a wafer i w-,--'-, field oxide 2 for the
1 1 BAD ORIGINAL isolation of a device using a conventional method. Afterwards, sidewall spacer 6 are formed at both sides of the gate electrode 4 and then an inter-level insulating layer 7 such as silicon dioxide i S formed on the silicon wafer 1 by a chemical vapor denos-i--icn(CVD) method. Next, in order to even the overall surface topology due to the field oxide 2 and the gate electrode 4, a BPSG '1,a-,,,er 8 is formed on the inter-level insulating layer 7 by either plasma enhanced chemical vapor deposition (PECVD) or atmospheric cressure chemical vapor deposition(APCVD). As described abcve, it is -,-)referable that the concentration of boron and r)hosiDhorous c=tained in BP5G laver 8 be 3.5-5.0 wt-6 to achieve a more planar
22 7 = The wafer 1 on which BPSG layer 8 is -formed, is loaded to a d i ffu s i o n furnace maintaining atmospheric pressure and a temmerature of 750- 8500C. Afterwards, the temDerature of the diffusion furnace is elevated to 800-8500C, and nitrogen(N2) gas is sunnlied to he diffusion furnace. Under the above -ment ioned thermal annealing process for the Allow of the deposited BPSG layer 8, proceeds for 2060 minutes, whereby SPSG 7aver 8 is planarized. Lastly, the temperature of the diffusion furn.ace lowers to 650-8001C, and the wafer 1 is unloaded from the diffusion furnace.
Not shown -'n FJa. 1, a second insulating!aver is then formed c,- the planarized BPSG3 layer of the wafer 1, and predetermined 2crz:-s-.s Ssecond insular-ing!aver, BP5G layer, and -first -nsu-au-na laver are etched to expose the underlying juncticn 3 BAD ORIGINAL j10 reaions, thereby forming contact holes. Afterwards, metal interconnects are formed to electrically conzacr with junction recions.
Then, boron and phosphorous atoms doped in 3PSGi layer 8 dif.fuse outwards from the surface during the flow process because off the high flow temperature. Due to the above -ment ioned facts, d---'::fused boron and phosphorous atoms are gathered to the surface ot: B p S G layer 8, and thereby the surface thereof becomes over-saturated. Afterwards, when the wafer 1 is unloaded to the outside, the atoms gathered at the surface of the BPSC- layer 8 is nrecipitated to -crystal from the abrupt chancre on the sur-face - emnerauure, and from the moisture present the atmosphere. These -crec-z-4- -aued crystals aenerate not only crystal defects on the c-ir a pattern but also pattern defects such as notching. Moreover, it degrades the insulating property cf: BPSC-!aver 8.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the -present invention to zr,-v-de a method for the planarization of a semiconductor device capable of preventing the generation of: crystal defects by zrevent----ng dopants contained in EPS137 layer for the planarization Z from nrecinizating when a wafer, on which the SPSG!aver -'s for-ned, is unloaded f'rom a diffusion furnace ai::ter --'.,ie flow the deposited BP5G layer has been completed.
Another obect of this invention is to crevide a method 4t BAD ORIGINAL.4 v L he planarization o f a semiconductor device capable of p facilitating the patterning of a layer that is deposited on BP5G !a-..er.
L -e According to the present inven,on, a method 'or t.' p ana=zation cf: a semiconductor device comorises the scens of:
prcv-dna a having a to-pology is formed; forming an inter-level on!--.-ie semiconductor substrate.
semiconductor substrate on which a patterned!aver i-isulatng for-mina a laver for he n_anarization containing a dor)anci on::-',,e J-n-L-er-";_evel diffusina the donant contained in the layer for the n_anarization outward from the surface; and flowing the laver for e-ar,,ar-zar---'cn.
BRIEF DESCRIPTION OF THE DRAWINGS i -- Further ob-41ects and advantages of: the present invenzJon will L be acnareni: from the following description, reference b eing had i:- the accomnanving drawings wherein preferred embodiment of t h. e present invention are clearly shown. the drawinas: is a cross -secr- ona v-ew of a semiconductor device e=-a-nng a me--hod for planarization of the semiconductor dev-e t.-ie conventional art; and tzy 2E are cross - sect ional views of a semiconductor ining a method for planarization of the semiconductor ic an embodiment cf t--he uresen,: invention.
@AD ORIGNAL 0) DETAILED DESCRIPTION OF THE INVENTION
7-3 Referring to Fig. 2A, a field oxide 11 -'s formed by thermally growing predetermined portions of a silicon wafer 10. Afterwards, gaze oxide 12 is deposited on the wafer 10 to a thickness of i00 to 2C0 A and a polysilicon laver 13 containing dopants is then deposited on the gate oxide 12 by a chemical vapor deposition. Next, a photo-mask pattern(not shown) is formed on the polysilicon ",aver 13 using a conventional photo- lithography method, and a gate e-ectrode-14 is then formed by patterning the polysilicon layer 13 and the underlying- gate oxide 1-2 using the photo-mask pattern. - m,-,,ur-itv-dor)ed regions 15 are formed at both sides of the gate --"------rode 14 in the wafer iO using ion implantation method. Spacers are provided at both side walls of the gate electrode 14 for the - -ma t: i on of a metal oxide semiconductor field effect zransistor(MOSFE-,) having lightly doped drain (LDD) structure, where the snacers 16 are formed by anisocropic etching of silicon dioxide!aver deposited on MOSFET structure of Fig. 2A.
Referring to Fig. 2B, an insulating layer 1-7 such as silicon --c)xide layer is formed on whole surface of the resultant siructure of Fig. 2A using a chemical vapor deposition. Afterwards, an oxide laver Conzainina donants, for examnle, a BPSG laver 18, is on the insulating layer 17 at a demosition condition APC77D method.
method. in this caSE cf.' atmospheric pressure and a temperature ran( ge of 400-4500C usina it is possible to form r"-,e BPSG layer 18 using PECVD the BPSG!aver 18 contains a high BAD ORIGINAL jp 7 -- concentration of boron and phosphorous ions. Afterwards, the wafer 10 is loaded to a reactor chamber for low pressure chemical,,a=)or depos-J---,.- (LPCVD) whose inner pressure is maintained at mTorr, and a first thermal annealincr process is performed for approximately 60 minutes.
Referring o Fig. 2C, during the first hermal annealing, boron and phosphorous ions contained in the EPSG layer 18 d--,:fused outwards from the surface s the EPSG laver 18, a thereby surface concentration of the EP5G layer 18 is decreased .,--.Lused boron and phosphorous atoms are eliminated through an cutlet -f:rom the -reactor chamber to the outside of -he chamber a z...imu-na process.
A-=zer,war--.s, =he temperature of the reactor chamber rises to 350-9000C, and ihe inside of the react::)r is maintained at nicrocen a=mosr)here. Under the above-mentioned condition, a second thermal annealing process is performed for 20-40 minutes.
As a resuli, the BPSG layer 18 is flowed as shown in Fia. 2D, resu-L.7inc i.-:'-e z-"anar-za7-ion of the surface of the wafer 10 withcut the precipitation of do-cants taking place.
Referrinw:io Fig. 2E, in order to f,-.D.-m a passivation laver!9 EPSG lal;er 13, N,0 gas is supplied to the reactor chamber, and a thermal oxi-de is formed on BPSG laver 18 by a flow process and:hermal cx--'dazi'-)n at the same temperature. in the possible case:'-.at docants zrecJpit-ate from 3PSG laver 18 due to the abrupt iem.eera:ure change, the passivation layer --9 made of the thermal 2xde acts to prevent the generation of crystal defects when ihe 1 BAD ORIGINAL J0) t -, 1 C wa.;zer is unloaded from the reactor chamber.
After the formation of the passivation 'Layer 19 is completed, zne temuerature of the reactor chamber for L'-.::VD lowers to 680-72-1 C,-, 1-om the reactor chamber. At - and then the waf:er 10 is unloaded ft----s time, the -.':irst annealing process, the second annealing cr:cess and the passivation layer forming process are performed in same reactor chamber without vacuum break.
As described in the above, the present invention facilitates of a pattern that is formed durina a nrocess su'-se--uen:. to a formation mrocess of SPSG laver but also provides insulating property.
3ther features, advantages and embod-;menis of the inventicn herein will be readily ani::)aren7- to those exercising c------narv skill after reading the fcreacinc disclosures. In this ----ard, while siDecific embodiments c)f the invention have been il - do-=seribe,--' i_n considerable detail, variatIons and modif icat ions of em'-cd-iments can be effected without dezartina from the spiril an- z---p c-.c the ---vent--lon as descr-'-'---d and claimed.
8 1 BAD ORIGINAL

Claims (1)

  1. WHAT IS CLAIMED IS:
    2- i. A method for the planarization of a semiconductor device c:,--nr-sing the stens of:
    nrovidina a semi conductor substrate on which a patterned layer 'na-7ing topology is form.ed; forming an interlevel insulating layer on the semiconducz--r forming a interievel the donant contained 4. n the layer for the p- a:iar J-za7-'Lcn, outwards from the surface of the layer; and flowing the laver for the Planarizacion.
    layer for the planarization containing a dopant on nsular--na layer; 2. The method in accordance with claim i, wherein said layer -he n_anarzation is EPSG.
    m-he method n accordance with claim 1, wherein d-;f.":usion c -:.'=z)anes is nerformed by a thermal annealing process.
    The merhod in accordance with claim 1, wherein said s:;e- is pertormed for 50-70 minut-es at a temnerature cf:
    t.' - - and a pressure of 10-100 mTorr.
    --he me-hod in accrdar,,ce with claim, 1, wherein said flowina _s per.-:rme--; for 25-25 minutes at: a temnerature of 850-9000C.
    9 BAD ORIGINAL JR) 6. The method in accordance with claim 1, wherein both of said d-'---- 'using step and said flowing step are performed in the same c'--=T,ber without vacuum break.
    7. The method in accordance with clam 6, wheren both saJd siecs are Performe,-- in LP= chamber.
    8. The method -n accordance with cla-'-i 1-,-.'urther comerisinz :h=ster) of: a passivation layer on the flowed!aver for the -zation.
    -=nar- 0 7:
    9. The method in accordance wit,)- claim 8, wherein sa-'d,sacsvat'on!aver -'s.formed bv a thermal oxidation process.
    -1e metho-4 accordance wit' claim 8, wherein said thermal SxIdaz-on -.:)rocess Is performed at an atmosphere of N-0.
    The methcd n accordance with claim 5, where- a'! c.:: said =.;:us ing sren, sal flowing step and said formJncr step of pass-vat---n layer are performed in the same chamber without vacuum break.
    -1.
    The r-.e?--ho-- --'n accordance with claim 5, wherein all said steps are in --:-:ICVD cnamber.
    1 BAD ORIGINAL A
GB9624132A 1995-11-20 1996-11-20 Method for planarization of semiconductor device Expired - Fee Related GB2307344B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950042291A KR100262400B1 (en) 1995-11-20 1995-11-20 Method of planarization semiconductor device

Publications (3)

Publication Number Publication Date
GB9624132D0 GB9624132D0 (en) 1997-01-08
GB2307344A true GB2307344A (en) 1997-05-21
GB2307344B GB2307344B (en) 2000-05-17

Family

ID=19434734

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9624132A Expired - Fee Related GB2307344B (en) 1995-11-20 1996-11-20 Method for planarization of semiconductor device

Country Status (6)

Country Link
JP (1) JP2799858B2 (en)
KR (1) KR100262400B1 (en)
CN (1) CN1080928C (en)
DE (1) DE19648082C2 (en)
GB (1) GB2307344B (en)
TW (1) TW442872B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1006212A1 (en) * 1998-12-04 2000-06-07 Canon Sales Co., Inc. Film forming method
US6903322B2 (en) * 2000-04-03 2005-06-07 Sharp Kabushiki Kaisha Solid-state imaging device and method for producing the same

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100256232B1 (en) * 1997-06-30 2000-05-15 김영환 A method for forming interlayer dielectric layer in semiconductor device
KR100506054B1 (en) * 2000-12-28 2005-08-05 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
US7226873B2 (en) * 2004-11-22 2007-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of improving via filling uniformity in isolated and dense via-pattern regions
KR20120098095A (en) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 Method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0519393A2 (en) * 1991-06-20 1992-12-23 Semiconductor Process Laboratory Co., Ltd. Method for planarizing a semiconductor substrate surface
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237744A (en) * 1990-02-14 1991-10-23 Matsushita Electron Corp Manufacture of semiconductor device
JP2874972B2 (en) * 1990-07-11 1999-03-24 株式会社東芝 Method for manufacturing semiconductor device
KR950006339B1 (en) * 1991-11-19 1995-06-14 현대전자산업주식회사 Bpsg layer forming method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device
EP0519393A2 (en) * 1991-06-20 1992-12-23 Semiconductor Process Laboratory Co., Ltd. Method for planarizing a semiconductor substrate surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1006212A1 (en) * 1998-12-04 2000-06-07 Canon Sales Co., Inc. Film forming method
US6903322B2 (en) * 2000-04-03 2005-06-07 Sharp Kabushiki Kaisha Solid-state imaging device and method for producing the same

Also Published As

Publication number Publication date
CN1159076A (en) 1997-09-10
KR970030476A (en) 1997-06-26
KR100262400B1 (en) 2000-09-01
DE19648082C2 (en) 2000-03-23
CN1080928C (en) 2002-03-13
JP2799858B2 (en) 1998-09-21
GB2307344B (en) 2000-05-17
JPH1092826A (en) 1998-04-10
TW442872B (en) 2001-06-23
DE19648082A1 (en) 1997-05-22
GB9624132D0 (en) 1997-01-08

Similar Documents

Publication Publication Date Title
US5429988A (en) Process for producing high density conductive lines
US5578524A (en) Fabrication process of a semiconductor device with a wiring structure
US4839306A (en) Method of manufacturing a trench filled with an insulating material in a semiconductor substrate
US5711891A (en) Wafer processing using thermal nitride etch mask
US4641170A (en) Self-aligned lateral bipolar transistors
US4305974A (en) Method of manufacturing a semiconductor device
JPH021132A (en) Manufacture of integrated circuit structure
US5814545A (en) Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
US3986896A (en) Method of manufacturing semiconductor devices
US6291300B1 (en) Manufacturing method of semiconductor devices
US4879253A (en) Method for fabricating a semiconductor device using a BPSG layer containing high concentrations of phosphorus and boron
GB2307344A (en) Method for planarization of semicondoctor device
US4551906A (en) Method for making self-aligned lateral bipolar transistors
US5643824A (en) Method of forming nitride sidewalls having spacer feet in a locos process
US5506172A (en) Semiconductor processing method of forming an electrical interconnection between an outer layer and an inner layer
US6514803B1 (en) Process for making an amorphous silicon thin film semiconductor device
JP2812288B2 (en) Method for manufacturing semiconductor device
KR100350030B1 (en) Semiconductor device manufacturing method
JP2830705B2 (en) Method for manufacturing semiconductor device
JPH11121621A (en) Method of forming self-aligned contact hole
KR100257697B1 (en) Process for forming contacts
JPH08306783A (en) Method for making contact in semiconductor device
US6169026B1 (en) Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer
US5977608A (en) Modified poly-buffered isolation
JPH06112192A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20131120