KR970030476A - 반도체 소자의 bpsg 형성방법 - Google Patents

반도체 소자의 bpsg 형성방법 Download PDF

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Publication number
KR970030476A
KR970030476A KR1019950042291A KR19950042291A KR970030476A KR 970030476 A KR970030476 A KR 970030476A KR 1019950042291 A KR1019950042291 A KR 1019950042291A KR 19950042291 A KR19950042291 A KR 19950042291A KR 970030476 A KR970030476 A KR 970030476A
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bpsg
film
forming
treatment process
heat treatment
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KR1019950042291A
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KR100262400B1 (ko
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박인옥
정영석
김의식
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김주용
현대전자산업 주식회사
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Priority to KR1019950042291A priority Critical patent/KR100262400B1/ko
Priority to CN96123330A priority patent/CN1080928C/zh
Priority to DE19648082A priority patent/DE19648082C2/de
Priority to GB9624132A priority patent/GB2307344B/en
Priority to JP8324638A priority patent/JP2799858B2/ja
Priority to TW085114291A priority patent/TW442872B/zh
Publication of KR970030476A publication Critical patent/KR970030476A/ko
Priority to US09/065,982 priority patent/US6169026B1/en
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Publication of KR100262400B1 publication Critical patent/KR100262400B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

본 발명은 반도체 소자의 BPSG(borophoshporus silicate glass) 형성방법에 관한 것으로, 보다 구체적으로는 반도체 소자의 평탄화 절연막이 BPSG막의 결정 결함을 방지할 수 있는 반도체 소자의 BPSG 형성방법에 관한 것이다.
본 발명의 방법은 패턴이 구비된 반도체 기판 상부에 절연막을 형성하는 공정과; 상기 절연막 상부에 BPSG막을 저형성하는 공정과; 상기 형성된 BPSG막을 저온 저압하에서 장시간 열공정을 진행하는 1단계 열치리 공정과; 상기 1단계 열치된 BPSG막을 플로우시키기 위한 2단계 열처리 공정과; 상기 2단계 열처리된 BPSG막 상부에 보호막을 형성하기 위한 3단계 열처리 공정을 포함한다. 본 발명에 따르면, 반도체 소자의 평탄화 절연막인 BPSG 형성 공정시, 3단계의 열처리 공정에 의하여 BPSG막 표면의 결정 석출을 방지하므로써, 이후에 소자의 패턴 형성을 용이하게 하고, 또한 배선간의 불량을 방지하여 제품의 특성과 제조 수율을 향상시킬 수 있다.

Description

반도체 소자의 BPSG 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도(a) 내지 (d)는 본 발명에 따른 반도체 소자의 BPSG 형성방법을 성명하기 위한 도면.

Claims (7)

  1. 패턴이 구비된 반도체 기판 상부에 절연막을 형성하는 공정과; 상기 절연막 상부에 BPSG막을 형성하는 공정과; 상기 형성된 BPSG막을 저온 저압하에서 장시간 열공정을 진행하는 1단계 열처리 공정과; 상기 1단계 열처리된 BPSG막을 풀로우시키기 위한 2단계 열처리 공정과; 상기 2단계 열처리된 BPSG막 상부에 보호막을 형성하기 위한 3단계 열처리 공정을 포함하는 것을 특징으로 하는 반도체 소자의 BPSG 형성방법.
  2. 제1항에 있어서, 상기 BPSG막은 PECVD법 또는 APCVD법에 의해 형성되는 것을 특징으로 하는 반도체 소자의 BPSG 형성방법.
  3. 제1항에 있어서, 상기 1단계 열처리 공정은 반응로의 온도를 650 내지 750℃정도로 유지하고, 10 내지 100m Torr의 압력에서 1시간 이상의 열처리하는 것을 특징으로하는 반도체 소자의 BPSG 형성방법.
  4. 제3항에 있어서, 상기 2단계 열처리 공정은 반응로내를 질소 분위기로 조정하고, 반응로의 온도를 850 내지 900℃의 온도로 25 내지 35분정도 플로우 공정을 진행하는 것을 특징으로 하는 반도체 소자의 BPSG 형성방법.
  5. 제4항에 있어서, 상기 3단계 열처리 공정은 반응로내에 N2O가스를 주입하여 BPSG막 표면에 보호막을 형성하는 것을 특징으로 하는 반도제 소자의 BPSG 형성방법.
  6. 제1항 또는 제5항에 있어서, 상기 보호막은 열산화막인 것을 특징으로 하는 반도체 소자의 BPSG 형성방법.
  7. 제1항에 있어서, 상기 3단계 열처리 공정이 진행되는 반응로는 LPCVD장비인 것을 특징으로 하는 반도체소자의 BPSG 형성방법.
KR1019950042291A 1995-11-20 1995-11-20 반도체 소자의 평탄화방법 KR100262400B1 (ko)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019950042291A KR100262400B1 (ko) 1995-11-20 1995-11-20 반도체 소자의 평탄화방법
CN96123330A CN1080928C (zh) 1995-11-20 1996-11-20 半导体器件的平整方法
DE19648082A DE19648082C2 (de) 1995-11-20 1996-11-20 Verfahren zur Einebnung einer Halbleitereinrichtung
GB9624132A GB2307344B (en) 1995-11-20 1996-11-20 Method for planarization of semiconductor device
JP8324638A JP2799858B2 (ja) 1995-11-20 1996-11-20 半導体デバイスの平坦化方法
TW085114291A TW442872B (en) 1995-11-20 1996-11-20 Method for planarization of semiconductor device
US09/065,982 US6169026B1 (en) 1995-11-20 1998-04-24 Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950042291A KR100262400B1 (ko) 1995-11-20 1995-11-20 반도체 소자의 평탄화방법

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Publication Number Publication Date
KR970030476A true KR970030476A (ko) 1997-06-26
KR100262400B1 KR100262400B1 (ko) 2000-09-01

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JP (1) JP2799858B2 (ko)
KR (1) KR100262400B1 (ko)
CN (1) CN1080928C (ko)
DE (1) DE19648082C2 (ko)
GB (1) GB2307344B (ko)
TW (1) TW442872B (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100256232B1 (ko) * 1997-06-30 2000-05-15 김영환 반도체소자의층간절연막형성방법
KR100506054B1 (ko) * 2000-12-28 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3229276B2 (ja) * 1998-12-04 2001-11-19 キヤノン販売株式会社 成膜方法及び半導体装置の製造方法
JP3824469B2 (ja) * 2000-04-03 2006-09-20 シャープ株式会社 固体撮像装置、及びその製造方法
US7226873B2 (en) * 2004-11-22 2007-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of improving via filling uniformity in isolated and dense via-pattern regions
KR20120098095A (ko) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 반도체장치 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237744A (ja) * 1990-02-14 1991-10-23 Matsushita Electron Corp 半導体装置の製造方法
JP2874972B2 (ja) * 1990-07-11 1999-03-24 株式会社東芝 半導体装置の製造方法
US5268333A (en) * 1990-12-19 1993-12-07 Samsung Electronics Co., Ltd. Method of reflowing a semiconductor device
JP2538722B2 (ja) * 1991-06-20 1996-10-02 株式会社半導体プロセス研究所 半導体装置の製造方法
KR950006339B1 (ko) * 1991-11-19 1995-06-14 현대전자산업주식회사 표면결정성 석출물 발생방지를 위한 bpsg층 형성방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100256232B1 (ko) * 1997-06-30 2000-05-15 김영환 반도체소자의층간절연막형성방법
KR100506054B1 (ko) * 2000-12-28 2005-08-05 주식회사 하이닉스반도체 반도체 소자의 제조 방법

Also Published As

Publication number Publication date
CN1159076A (zh) 1997-09-10
GB2307344A (en) 1997-05-21
KR100262400B1 (ko) 2000-09-01
DE19648082C2 (de) 2000-03-23
CN1080928C (zh) 2002-03-13
JP2799858B2 (ja) 1998-09-21
GB2307344B (en) 2000-05-17
JPH1092826A (ja) 1998-04-10
TW442872B (en) 2001-06-23
DE19648082A1 (de) 1997-05-22
GB9624132D0 (en) 1997-01-08

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