CN107533974A - 低应力低氢型lpcvd氮化硅 - Google Patents

低应力低氢型lpcvd氮化硅 Download PDF

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CN107533974A
CN107533974A CN201680028363.3A CN201680028363A CN107533974A CN 107533974 A CN107533974 A CN 107533974A CN 201680028363 A CN201680028363 A CN 201680028363A CN 107533974 A CN107533974 A CN 107533974A
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silicon nitride
nitride layer
microelectronic component
substrate
grid
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CN107533974B (zh
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N·S·德拉斯
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Texas Instruments Inc
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Abstract

在所描述的示例中，一种微电子器件(102)包含高性能氮化硅层，此氮化硅层的化学计量在2原子百分比(at％)内，具有低应力为600MPa到1000MPa，并且具有小于5原子百分比的低氢含量，由LPCVD工艺形成。LPCVD工艺使用氨气NH3和二氯甲硅烷DCS气体，其比率为4比6，压力为150毫托至250毫托，并且温度为800℃至820℃。

Description

低应力低氢型LPCVD氮化硅
技术领域
本发明通常涉及微电子器件，且更具体地，涉及在微电子器件中的氮化硅层。
背景技术
在微电子器件中，期望形成化学计量的氮化硅层，其同时具有低于1000兆帕(MPa)的低应力(stress)和小于5原子百分比(at％)的低氢含量。这种薄膜将用于各种微电子应用中。通过等离子体增强化学气相沉积(PECVD)形成的氮化硅薄膜可具有低应力但是具有15at％以上的高氢含量，其能引起可靠性问题和差的抗蚀刻性。通过低压化学气相沉积(LPCVD)形成的薄膜具有低氢气含量但是具有1000MPa以上的高应力，其能引起器件性能问题。
发明内容
在描述的示例中，微电子器件包含高性能氮化硅层，其化学计量在2原子百分比(at％)以内，具有600MPa至1000MPa的低应力，并且具有小于5at％的低氢含量。通过LPCVD工艺形成高性能氮化硅层。LPCVD工艺使用氨气和二氯甲硅烷气体，其比率为4比6，压力为150毫托至250毫托，且温度为800℃至820℃。
附图说明
图1描述在微电子器件上形成高性能氮化硅的示例过程中的LPCVD炉(furnace)，并且图1A为在图1的炉内的微电子器件上形成的氮化硅层的扩展视图。
图2是具有高性能氮化硅层的示例半导体器件的横截面图。
图3A和图3B是图2的半导体器件的横截面图，在形成的关键阶段中描述的。
图4是具有高性能氮化硅层的示例集成电路的横截面图。
图5A和图5B是图4的集成电路的横截面图，在制造的关键阶段中描述的。
图6A和图6B是具有高性能氮化硅层的示例微机电系统(MEMS)器件的横截面图，在制造的关键阶段中描述的。
具体实施方式
附图不按照比率绘制。一些动作(act)可能以不同的顺序发生和/或与其他的动作或事件同时发生。并非所有说明的动作或事件都需要根据示例实施例来实现方法。
通过LPCVD工艺形成高性能氮化硅层，其化学计量在2原子百分比以内，具有600MPa到1000MPa的低应力，并且具有小于5原子百分比的低氢含量。LPCVD工艺使用氨气和二氯甲硅烷气体，其比率为4比6，压力为150毫托到250毫托，且温度为800℃到820℃。没有预期通过公开的工艺条件提供化学计量、低应力和低氢含量的组合，而该组合在LPCVD工艺研究中发现。针对本公开的目的，化学计量的氮化硅具有3:4的硅：氮的原子比。
图1描述在微电子器件上形成高性能氮化硅的示例过程中的LPCVD炉。LPCVD炉100包含(hold)在舟(boat)104中的衬底(例如半导体晶片)上的微电子器件102。舟104包含在LPCVD炉100的反应室106中。通过放置在反应室106周围的LPCVD炉100的加热元件108加热反应室106至800℃到820℃的温度。以4：6的比率将氨气(NH3)和二氯甲硅烷(DCS)气体引进到反应室106。在反应室106内部的压力通过排气系统110(例如包括排气泵和可调节排气阀的结合)维持在150毫托到250毫托。如图1A的扩展视图中所示，通过氨气中的氮与二氯甲硅烷中的硅的反应，在微电子器件102上形成高性能氮化硅层112。高性能氮化硅层112的形成继续进行，直到达到所需厚度。随后，停止氨气和二氯甲硅烷的气流，并且从LPCVD炉100中提取微电子器件102。
通过维持温度在800℃到820℃，氨气和二氯甲硅烷的比率为4比6，以及150毫托至250毫托的压力的高性能氮化硅层112的形成有利地提供在2％以内的硅：氮原子比，其具有3:4的比率，600MPa到1000MPa的低应力，和小于5原子百分比的低氢含量。通过参照图1所描述的工艺形成的高性能氮化硅层112可具有2.0到2.1的折射率。此外，高性能氮化硅层112可具有大于12兆伏每厘米(MV/cm)的介电击穿强度，这可有利地促进微电子器件102的更高的可靠性。增加氨气和二氯甲硅烷的比率降低化学计量和介电击穿强度，这可能不利地导致较低的可靠性。减小氨气和二氯甲硅烷的比率不利地增大应力。减小温度和增加压力也不利地增大应力。
图2是具有高性能氮化硅层的示例半导体器件的横截面图。在半导体衬底202(例如堆叠的氮化镓和氮化铝镓外延层，且可能地其他的Ⅲ-Ⅴ层)上形成半导体器件200。在衬底202上布置氮化镓的盖层(cap layer)204。在半导体器件200的氮化镓场效应晶体管(GaNFET)的栅极208的两侧上以及源极210和漏极212之间的盖层204上布置高性能氮化硅层206。栅极208可与高性能氮化硅层206部分重叠。例如，高性能氮化硅层206可能是10纳米到20纳米厚。
在衬底202上，在源极210和漏极212中布置触点金属216。围绕触点金属216在栅极208和高性能氮化硅层206上方布置场板介电层218。源极金属220与源极210中的触点金属216电连接，并且与栅极208重叠，并中途延伸到场板介电层218上方的漏极212，以为GaNFET 214提供场板。漏极金属222与漏极212中的触点金属216电连接。可以形成附加的介电层和金属层以提供与GaN FET 214的低电阻连接。
高性能氮化硅层206的低应力与具有高应力的氮化硅层的GaN FET相比有利地改善GaN FET 214中的开态(on-state)电流。高性能氮化硅层206的低氢含量与具有高氢含量的氮化硅层的GaN FET相比有利地减小电荷陷阱(trapping)和改善GaN FET 214的可靠性。
图3A和图3B是图2的半导体器件的横截面图，在形成的关键阶段中描述的。参照图3A，通过外延工艺在衬底202上形成盖层204。可移除盖层204的一部分和衬底202，以为GaNFET 214提供横向隔离边界224。通过LPCVD工艺在盖层204上形成高性能氮化硅层206，如参考图1所述。在高性能氮化硅层206上方形成蚀刻掩膜226来覆盖图2中完成的GaN FET 214的高性能氮化硅层206的区域。蚀刻掩膜226可包括通过光刻工艺形成的光刻胶，并且也可能包括抗反射层。
参考图3B，含氟(F)的反应离子刻蚀(RIE)过程228将在由蚀刻掩膜226暴露处的高性能氮化硅层206移除。可调整在RIE过程228中的反应气体流量和压力，以在高性能氮化硅层206上提供斜边/倾斜边缘，如图3B中描述的。随后，移除蚀刻掩膜226，例如通过灰化工艺。半导体器件200的制造被继续用于提供图2的结构。参照图3A和图3B中描述的方法有利地提供了具有低应力和低氢含量的期望性能的图案化高性能氮化硅层206。
图4是具有高性能氮化硅层的示例集成电路的横截面图。在半导体衬底402如硅晶片上形成集成电路400。集成电路400包括p-沟道金属氧化物半导体(PMOS)晶体管404和/或n-沟道金属氧化物半导体(NMOS)晶体管406。在衬底402中布置场氧化物408来横向隔离PMOS晶体管404和NMOS晶体管406。
在n型阱410中布置PMOS晶体管404，其在场氧化物408下面延伸。PMOS晶体管404包括在n型阱410上的栅极介电层412和在栅极介电层412上的栅极414。在栅极414的横向表面上布置偏移隔离层(offset spacer)416。在栅极414的两侧上在n型阱410中布置p型源极和漏极区418。源极和漏极区418包括源极/漏极扩展420和临近栅极414的深源极/漏极区422，源极/漏极扩展420在栅极414下方延伸。
在偏移隔离层416上邻近栅极414布置栅极侧壁隔离层424。栅极侧壁隔离层424包括具有低应力和低氢含量的高性能氮化硅的一个或更多个层。在源极和漏极区418上邻近栅极侧壁隔离层424以及可能在栅极414上布置金属硅化物426。栅极侧壁隔离层424在栅极介电层412正下方的沟道层和深源极/漏极区422之间，及在沟道层和源极/漏极区418上的金属硅化物426之间提供横向分离。栅极侧壁隔离层424中的高性能氮化硅可在半导体衬底402的10纳米以内。栅极侧壁隔离层424的低应力可有利地减小沟道层中的应力，并且因此改善PMOS晶体管404的开态电流和/或关态电流。栅极侧壁隔离层424的低氢含量有利地改善PMOS晶体管404的可靠性。
类似地，在p型阱428内布置NMOS晶体管406，其在场氧化物408下面延伸。NMOS晶体管406包括在p型阱428上的栅极介电层430和在栅极介电层430上的栅极432。在栅极432的横向表面上布置偏移隔离层434。在栅极432的两侧上在p型阱428内布置n型源极和漏极区436。源极和漏极区436包括源极/漏极扩展438和临近栅极432的深源极/漏极区440，源极/漏极扩展438在栅极432下方延伸。邻近栅极432布置栅极侧壁隔离层442，栅极侧壁隔离层442包括一个或更多个高性能氮化硅层。PMOS晶体管404的栅极侧壁隔离层424和NMOS晶体管406的栅极侧壁隔离层424可能由于同时形成而具有相同的层结构。邻近栅极侧壁隔离层442在源极和漏极区436上，也可能在栅极432上布置金属硅化物444。与参考PMOS晶体管404描述的类似，NMOS晶体管可以从栅极侧壁隔离层442的低应力和低氢含量获得优势。
图5A和图5B是图4的集成电路的横截面图，在制造的关键阶段中描述的。参照图5A，通过使用PMOS晶体管404的栅极414和偏移隔离层416作为注入掩膜将p-型掺杂剂注入到n-型阱410中形成p-型源极/漏极扩展420，使得源极/漏极扩展420不完全在栅极414下延伸。类似地，通过使用NMOS晶体管406的栅极432和偏移隔离层434作为注入掩膜将n-型掺杂剂注入到p-型阱428中形成n-型源极/漏极扩展438，使得源极/漏极扩展438不完全在栅极432下延伸。随后将衬底402退火以激活注入的掺杂剂。
高性能氮化硅层450在PMOS晶体管404的栅极414、偏移隔离层416、源极/漏极扩展420上和在NMOS晶体管406的栅极432、偏移隔离层434、源极/漏极扩展438上形成。通过如参照图1描述的LPCVD工艺形成高性能氮化硅层450，其至少部分提供如图5A中描述的共形层，使得在偏移隔离层416和434的垂直表面上的高性能氮化硅层450的厚度足以分别形成图4的栅极侧壁隔离层424和442。
参照图5B，含氟(F)的各向异性RIE过程452移除图5A中的在PMOS晶体管404的栅极414和源极/漏极扩展420的水平表面上、以及NMOS晶体管406的栅极432和源极/漏极扩展438上的高性能氮化硅层450，留下的高性能氮化硅层450来形成PMOS晶体管404的偏移隔离层416的垂直表面上的栅极侧壁隔离层424和形成NMOS晶体管406的偏移隔离层434的垂直表面上的栅极侧壁隔离层442。LPCVD过程的共形方面形成高性能氮化硅层450，使得在没有光刻操作的条件下形成栅极侧壁隔离层424和442，这样有利地减少集成电路400的制造成本和复杂性。
图6A和图6B是具有高性能氮化硅层的示例微机电系统(MEMS)器件的横截面图，在制造的关键阶段中描述的。参照图6A，在硅衬底602(例如单晶硅晶片)中形成MEMS器件600。在衬底602中形成腔604，其以悬臂式元件606的形式在腔604上方留下衬底602的材料，例如穿孔膜(perforated membrane)606。穿孔膜606可以是传感器(如热传感器或麦克风)的部分，或可以是致动器(如扬声器)的部分。可期望将穿孔膜606与衬底602的邻近区608部分隔离。在穿孔膜606、腔604的内部表面和衬底602的邻近区608上形成高性能氮化硅层610。通过参考如图1所描述的LPCVD工艺形成高性能氮化硅层610，此高性能氮化硅层具有低应力和低氢含量，其提供至少部分共形层，使得高性能氮化硅层610覆盖如图6A所描述的穿孔膜606所有暴露的表面。由于通过穿孔膜606进入腔604受限制，高性能氮化硅层610在腔604外侧的穿孔膜606的顶部表面上比在面对腔604的穿孔膜606的底部表面上更厚。高性能氮化硅层610的低应力有利地降低由于在穿孔膜606的顶部和底部表面上的不等厚度造成的穿孔膜606的形变。
参照图6B，在邻近穿孔膜606的区608中从衬底602的一部分移除高性能氮化硅层610。将MEMS器件600浸没在晶体学湿法刻蚀溶液612中，例如氢氧化钾溶液，其沿着衬底602的晶面将在由高性能氮化硅层610暴露的区域中的硅从衬底602移除，来形成邻近穿孔膜606的隔离腔614。高性能氮化硅层610的低氢含量以期望的厚度有利地提供对晶体学湿法刻蚀溶液612的抗蚀刻性。接着冲洗和干燥MEMS器件600。高性能氮化硅层610可留在已完成的MEMS器件600中的适当位置或者可在随后的制造过程中被移除。
在权力要求的范围内，在描述的实施例中修改是可能的，并且其他实施例也是可能的。

Claims (20)

1.一种微电子器件，其包括：
衬底；以及
布置在所述衬底上的氮化硅层，所述氮化硅层具有以下特性：硅：氮原子比在2％以内，其比率为3:4；应力为600兆帕至1000兆帕即600MPa至1000MPa；并且氢含量小于5原子百分比。
2.根据权利要求1所述的微电子器件，其中所述氮化硅层小于25纳米厚。
3.根据权利要求1所述的微电子器件，其中所述氮化硅层具有的折射率是2.0至2.1。
4.根据权利要求1所述的微电子器件，其中所述氮化硅层具有的介电击穿强度大于12兆伏每厘米即12MV/cm。
5.根据权利要求1所述的微电子器件，其中所述微电子器件包括半导体材料，并且所述氮化硅层是10纳米以内的所述半导体材料。
6.根据权利要求1所述的微电子器件，其中所述半导体材料包括Ⅲ-Ⅴ半导体材料。
7.根据权利要求1所述的微电子器件，其中所述微电子器件包括氮化镓场效应晶体管即GaN FET。
8.根据权利要求7所述的微电子器件，其中所述氮化硅层接触Ⅲ-Ⅴ半导体材料并且接触所述GaN FET的栅极。
9.根据权利要求1所述的微电子器件，其中所述微电子器件包括n-沟道金属氧化物半导体晶体管即NMOS晶体管，其中第一栅极侧壁隔离层邻近所述NMOS晶体管的第一栅极，并且所述第一栅极侧壁隔离层包括所述氮化硅层。
10.根据权利要求9所述的微电子器件，其中所述微电子器件包括p-沟道金属氧化物半导体晶体管即PMOS晶体管，其中第二栅极侧壁隔离层邻近所述PMOS晶体管的第二栅极，并且所述第二栅极侧壁隔离层包括所述氮化硅层。
11.根据权利要求1所述的微电子器件，其中所述微电子器件是包含悬臂式元件的微机电系统器件即MEMS器件，并且所述氮化硅层布置在所述悬臂式元件的顶部表面上和所述悬臂式元件的底部表面上。
12.一种形成微电子器件的方法，其包括：
提供衬底；
将所述衬底放置在低压化学气相沉积炉即LPCVD炉中；
在所述LPCVD炉中将所述衬底加热至800℃到820℃的温度；
以4比6的比率和150毫托至250毫托的压力将氨气和二氯甲硅烷气体提供至反应室，以在所述衬底上形成氮化硅层；并且
从所述LPCVD炉中移除所述衬底。
13.根据权利要求12所述的方法，其包括：
在所述氮化硅层上形成蚀刻掩膜；
通过反应离子刻蚀过程即RIE过程用氟自由基将由所述蚀刻掩膜暴露的所述氮化硅层移除；以及
随后移除所述蚀刻掩膜。
14.根据权利要求13所述的方法，包括形成至少部分覆盖所述氮化硅层的导电元件。
15.根据权利要求14所述的方法，其中导电元件为GaN FET的栅极，并且所述氮化硅层布置在所述衬底上的盖层上。
16.根据权利要求12所述的方法，其中形成所述氮化硅层作为共形层，并且所述方法包括通过各向异性RIE过程用氟自由基将所述氮化硅层从所述衬底的水平表面移除，留下所述衬底的垂直表面上的所述氮化硅层。
17.根据权利要求16所述的方法，其中所述微电子器件是包含NMOS晶体管的集成电路，且所述氮化硅层在所述NMOS晶体管的栅极上形成，并且其中在所述各向异性RIE过程后剩下的所述氮化硅层提供邻近所述NMOS晶体管的所述栅极的栅极侧壁隔离层。
18.根据权利要求12所述的方法，其中所述微电子器件是包含悬臂式元件的MEMS器件，且所述氮化硅层形成为共形层，以在所述悬臂式元件的顶部表面上和所述悬臂式元件的底部表面上形成。
19.根据权利要求12所述的方法，其中所述氮化硅层在湿法刻蚀过程中保护所述衬底，其中将在由所述氮化硅层暴露的区域中的材料从所述衬底移除。
20.一种形成微电子器件的方法，其包括：
提供包括氮化镓的衬底；
在所述衬底上形成氮化镓的盖层；
把所述衬底放在LPCVD炉中；
在所述LPCVD炉中将所述衬底加热至800℃到820℃的温度；
以4比6的比率和150毫托至250毫托的压力将氨气和二氯甲硅烷气体提供至反应室，以在所述盖层上形成氮化硅层，所述氮化硅层有以下特性：硅：氮原子比在2％以内，其比率为3:4；应力为600兆帕至1000兆帕即600MPa至1000MPa；并且氢含量小于5原子百分比；
从所述LPCVD炉中移除所述衬底；
在所述氮化硅层上形成蚀刻掩膜；
通过反应离子刻蚀过程即RIE过程用氟自由基将由所述蚀刻掩膜暴露的所述氮化硅层移除；
随后移除所述蚀刻掩膜；并且
在所述氮化硅层的部分之间且部分重叠所述氮化硅层的所述部分的所述盖层上形成GaN FET的栅极。
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