CN111370306A - 晶体管的制作方法及全包围栅极器件结构 - Google Patents

晶体管的制作方法及全包围栅极器件结构 Download PDF

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CN111370306A
CN111370306A CN201811602315.8A CN201811602315A CN111370306A CN 111370306 A CN111370306 A CN 111370306A CN 201811602315 A CN201811602315 A CN 201811602315A CN 111370306 A CN111370306 A CN 111370306A
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channel region
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CN111370306B (zh
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秦晓珊
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Smic Ningbo Co ltd Shanghai Branch
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Smic Ningbo Co ltd Shanghai Branch
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Priority to PCT/CN2019/117797 priority patent/WO2020134669A1/zh
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Abstract

一种晶体管的制作方法及全包围栅极的器件结构，包括：基底由下至上依次包括底层衬底、绝缘层和顶层衬底；在顶层衬底形成源极区和漏极区，在源极区和漏极区之间形成沟道区，源极区至漏极区的方向为第一方向，垂直第一方向为第二方向；在第二方向上，沟道区两侧形成贯穿顶层衬底的孔；通过孔刻蚀孔下方及沟道区下方的绝缘层，以形成空腔，空腔与孔连通；形成栅极结构，覆盖所述沟道区上表面、所述孔和所述空腔靠近沟道区的壁面，所述栅极结构包括栅介质层及覆盖所述栅介质层的栅极，从而在沟道区的两侧及上下表面形成全包围的栅极结构，增加栅极对沟道的控制能力，提高击穿电压，同时提高电流Ids，简化MOS晶体管的栅极绝缘层的生长工艺。

Description

晶体管的制作方法及全包围栅极器件结构
技术领域
本发明涉及半导体技术领域，更具体地，涉及一种晶体管的制作方法及全包围栅极的器件结构。
背景技术
MOS晶体管的沟道可以有高的击穿电压，并且有高的电流Ids。如果提高沟道长度，可以提高击穿电压，但是会降低电流Ids。为了克服这一矛盾，现有技术中采用首先在沟道区的上表面生成上栅介质和上栅电极，之后在沟道区的下表面生成背栅介质和背栅电极，该结构被称为双栅电极结构，需要生长两次栅介质层，制造工艺复杂，导致产能较底，不利于器件的大批量生产。
因此，有必要提供一种制造工艺简单、便于大批量生产的基于SOI基底的全包围栅极器件结构及其制作方法。
发明内容
本发明的目的是进一步简化MOS晶体管的栅介质层生长工艺，同时保证沟道可以有高的击穿电压，并且有高的电流Ids。
为了实现上述目的，提出一种晶体管的制作方法，包括如下步骤：
提供基底，所述基底由下至上依次包括底层衬底、绝缘层和顶层衬底；
在所述顶层衬底形成源极区和漏极区，在所述源极区和漏极区之间形成沟道区，所述源极区至漏极区的方向为第一方向，垂直所述第一方向为第二方向；
在垂直于所述第一方向和所述第二方向的第三方向上，所述沟道区两侧形成贯穿所述顶层衬底的孔；
通过所述孔刻蚀所述孔下方及所述沟道区下方的绝缘层，以形成空腔，所述空腔与所述孔连通；
形成栅极结构，覆盖所述沟道区上表面、所述孔和所述空腔靠近沟道区的壁面，所述栅极结构包括栅介质层及覆盖所述栅介质层的栅极。
可选地，形成所述孔的方法包括：
在所述基底表面形成图形化的掩模层，定义出所述孔的位置；
以所述图形化的掩模层为掩模，刻蚀所述基底以形成所述孔。
可选地，所述形成空腔的方法包括：
可选地，以所述图形化的掩模层为掩模，刻蚀所述绝缘层以形成所述空腔。
可选地，所述刻蚀包括湿法刻蚀或干法刻蚀。
可选地，所述绝缘层为氧化硅。
可选地，所述湿法刻蚀使用的溶液为浓度为10％-20％的HF。
可选地，所述栅介质层包括氧化层。
可选地，通过热氧化或原子层沉积，形成所述氧化层。
可选地，所述栅极的形成方法包括：
在所述栅极介质层表面形成栅极电极层；
图形化所述栅极电极层，形成所述栅极。
可选地，所述栅极材料为多晶硅或金属。
可选地，还包括，还包括，当所述栅极材料为多晶硅时，对所述栅极电极层进行原位掺杂。
可选地，还包括：对所述栅极的顶面进行金属化生成金属硅化物。
可选地，形成所述栅极结构后，还包括：在所述孔内填充绝缘材料。
根据本发明的另一方面，提出一种全包围栅极的器件结构，包括：
形成在所述基底的顶层衬底中的源极区、漏极区以及在所述源极区、漏极区之间的沟道区；
形成在沟道区两侧的贯穿所述顶层衬底的孔；
形成在所述沟道区下方的空腔，所述孔与所述空腔连通；
形成在所述沟道区上表面、所述孔和所述空腔靠近沟道区的壁面的栅极结构。
可选地，所述栅极结构包括栅介质层及覆盖所述栅介质层的栅极。
可选地，所述栅极的材料为多晶硅或金属。
可选地，还包括：形成在所述栅极顶面的金属硅化物。
可选地，所述孔内填充有绝缘材料。
本发明的有益效果在于：在SOI的硅顶层的沟道区两侧形成孔，在沟道区下方形成与孔相通的空腔，在沟道区的上下表面和两侧形成全包围的栅极结构，通过全包围的栅极结构，增加栅极对沟道的控制能力，提高击穿电压，同时提高电流Ids，简化MOS晶体管的栅极绝缘层的生长工艺，便于大批量生产。
本发明的装置具有其它的特性和优点，这些特性和优点从并入本文中的附图和随后的具体实施方式中将是显而易见的，或者将在并入本文中的附图和随后的具体实施方式中进行详细陈述，这些附图和具体实施方式共同用于解释本发明的特定原理。
附图说明
通过结合附图对本发明示例性实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显，其中，在本发明示例性实施例中，相同的附图标记通常代表相同部件。
图1根据本发明的一个实施例的晶体管的制作方法的流程图。
图2根据本发明的一个实施例的全包围栅极器件结构的俯视图。
图3(A)～图3(E)分别是根据本发明的一个实施例的全包围栅极器件结构的A-A向不同阶段的结构示意图。
具体实施方式
下面将参照附图更详细地描述本发明。虽然附图中显示了本发明的优选实施例，然而应该理解，可以以各种形式实现本发明而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了使本发明更加透彻和完整，并且能够将本发明的范围完整地传达给本领域的技术人员。
如图1所示，根据本发明第一实施例的晶体管的制作方法，该制作方法包括如下步骤：
步骤1：参见图3(A)所示，提供基底，基底由下至上依次包括底层衬底101、绝缘层102和顶层衬底103；
具体地，基底为SOI基底，SOI基底的形成方法包括：第一步，在室温的环境下对底层衬底101的上表面进行热氧化，形成氧化硅绝缘层，并在绝缘层102上注入一定剂量的氢离子；第二步，常温条件下，底层衬底101与顶层衬底103键合；第三步，低温退火使注入氢离子形成气泡使绝缘层102上部的部分顶层衬底103剥离，然后高温退火增强未剥离的顶层衬底103和底层衬底101之间的键合力度；第四步，对未剥离的顶层衬底103表面进行平坦化处理。
通过离子注入和退火剥离的方式在绝缘层102之下的底层衬底101中形成应力引发区，该应力引发区为在顶层衬底103中制造半导体器件的沟道区201提供了有利应力，有助于提升半导体器件的性能。应力引发区形成在底层衬底101内，并延伸至顶层衬底103内，应力引发区的上平面不高于绝缘层102的下平面。
作为一个示例，参见图3(A)所示，在顶层衬底103的氧化层上形成作为掩膜材料的SiN介质层，利用光刻技术将图形转移到SiN介质层上，用于在顶层衬底103表面形成图形化的掩模层105。
作为一个示例，绝缘层102的材料为晶体或者非晶体氧化物、氮化物或其任意组合，通常选用SiO2。
作为一个示例，顶层衬底103和底层衬底101的材料为单晶硅、Ge或Ⅲ-Ⅴ族化合物(如SiC、砷化镓、砷化铟或磷化铟等)。
参考图2和图3(A)中箭头方向所示，步骤2：在顶层衬底103形成源极区302和漏极区303，在源极区302和漏极区303之间形成沟道区304，源极区302至漏极区303的方向为第一方向X，垂直第一方向X为第二方向Y。
具体地，源极区302、漏极区303和沟道区304，可以由光刻、离子注入、扩散和/或其他合适工艺的方法形成。
可选地，通过光刻工艺在源极区、漏极区和沟道区形成光刻胶图样，以盖住和限定相应的源极区域，使用光刻胶图样作为刻蚀掩膜进行刻蚀露出硅层，移除已用过的光刻胶图样，再向顶层衬底103中的源极区和漏极区注入P型或N型掺杂物或杂质，然后可以采用激光退火、闪光退火等工艺，以激活源/漏延伸区中的掺杂，现有技术中有多种工艺方法可供选择用于形成源极区、漏极区和沟道区。
步骤3：参见图2、图3(A)和3(B)中箭头方向所示，在垂直于第一方向X和第二方向Y的第三方向Z上，沟道区304两侧形成贯穿顶层衬底103的孔201，通过孔201刻蚀孔201下方及沟道区下方的绝缘层102，以形成空腔202，空腔202与孔201连通。
作为可选方案，形成孔201的方法包括：在基底表面形成图形化的掩模层105，定义出孔201的位置；以图形化的掩模层105为掩模，刻蚀基底以形成孔201。
参考图3(A)所示，作为一个示例，通过干法刻蚀形成孔201。首先，在基底表面涂覆一层光刻胶薄膜，利用紫外光通过掩膜版照射到光刻胶薄膜，引起曝光区域的光刻胶发生化学反应；然后，通过显影技术溶解去除曝光区域或未曝光区域的光刻胶(前者称正性光刻胶，后者称负性光刻胶)，使掩膜版上的图形被复制到光刻胶薄膜上，利用刻蚀技术将图形转移到基底上，在基底表面形成图形化的掩模层105，并定义出孔201的位置。最后，在掩模层105上定义刻蚀的开口，将要形成开口的部分暴露出来，不需要形成开口的部分保护起来，通过刻蚀剂以图形化的掩模层105为掩模刻蚀基底以形成孔201。
作为可选方案，参考图3(B)所示，形成空腔202的方法包括：以图形化的掩模层105为掩模，刻蚀绝缘层102以形成空腔202。
作为可选方案，绝缘层102为氧化硅。
作为可选方案，刻蚀为湿法刻蚀或干法刻蚀。
作为一个示例，仍然参考图3(B)所示，通过湿法刻蚀工艺刻蚀空腔，利用HF溶液只刻蚀二氧化硅绝缘层，不刻蚀其他材料的这个特性，把HF溶液注入到孔201中，刻蚀孔201中已经暴露的二氧化硅部分，对绝缘层102的横向和纵向都会刻蚀，从而在沟道区下形成空腔202，其使用的溶液为浓度为10％-20％，刻蚀速率为
Figure BDA0001922814650000061
步骤4：参见图2和图3(C)所示，形成栅极结构，栅极结构覆盖沟道区304上表面。沟道区304两侧的孔201和下面的空腔202使得沟道区304两侧及下部的壁面露出，从而可以在沟道区304的两侧及上下表面形成全包围的栅极结构，栅极结构包括栅介质层203及覆盖栅介质层203的栅极305。通过全包围的栅极结构，增加栅极305对沟道的控制能力，提高击穿电压，同时提高电流Ids，简化MOS晶体管的栅极绝缘层的生长工艺。
仍然参见图2和图3(C)所示，作为可选方案，栅极305的形成方法包括：在栅极介质层203表面形成栅极电极层205；图形化栅极电极层205，形成栅极305。
作为可选方案，栅介质层203包括氧化层。
作为可选方案，通过热氧化或原子层沉积，形成氧化层作为栅极介质层203。
作为一个示例，参见图2和图3(C)所示，在沟道区304的两侧及上下表面形成全包围的栅极结构包括：通过热生长法在沟道区304的两侧及上下表面形成氧化层。例如，先利用热生长法在沟道区304的两侧及上下表面氧化形成氧化硅，氧化硅作为栅极介质层203。因为孔201和空腔202的存在，沟道区304为暴露区域，通过一次热生长，即可在沟道区304的两侧及上下表面氧化形成氧化层，氧化层的厚度在1nm～10nm之间。
在一个示例中，参见图3(C)所示，还可以通过原子层沉积的方式，形成具有高k栅介质的氧化层，通过高k栅介质可以在保证各项电参数比例关系的同时，增大栅极介质层203的物理厚度，从而降低栅漏电流、提高器件可靠性。
在一个示例中，参见图2和图3(C)所示，在栅极介质层203的表面沉积多晶硅，形成栅极电极层205。例如，通过气相沉积可以在孔201的侧面及空腔202的侧面沉积一层多晶硅，以及在沟道区304上表面沉积多晶硅。
在一个示例中，可以通过原子层沉积在孔201的侧面及空腔202的侧面沉积金属栅极，金属栅极不需要进行原位掺杂即可形成栅极电极接触区。
作为可选方案，多晶硅层的厚度
Figure BDA0001922814650000071
步骤5：还包括：当栅极材料为多晶硅时，对栅极电极层205进行原位掺杂，形成栅极电极接触区。
具体地，参见图3(C)所示，在栅极电极层205形成之后，可以进行退火以控制栅极电极层205的掺杂分布，用于调节器件的开启电压。
在一个实施中，参见图3(C)所示，可以采用瞬间退火工艺对半导体结构进行退火，例如在大约800～1100℃的高温下进行激光退火，退火还可以修复注入工艺对顶层衬底103、绝缘层102和底层衬底101的损伤。
步骤6：还包括：对栅极305的顶面进行金属化生成金属硅化物。
具体地，通过在栅极电极接触区进行金属化反应生成金属硅化物，以便于减少该器件的电阻。
金属化反应首先采用诸如物理溅射等方法将金属沉积在晶片上，然后经过稍低温度的第一次退火(600～700℃)，再经过温度稍高的第二次退火(800～900℃)使金属(Cu、Ti、Co和NiPt等)与直接接触的有源区和多晶硅栅的硅反应形成金属硅化物，减少栅极电极的接触电阻。
步骤7：参见图3(D)所示，形成栅极结构后，还包括：在孔201内填充绝缘材料204。
具体地，可以利用PVD或CVD沉积法在孔201中沉积氧化硅、氮化硅绝缘材料204等。
步骤9：参见图2、图3(D)和图3(E)所示，去掉沟道区304边界外部的栅极电极层205和沉积于其表面的绝缘材料204，以及去掉沉积于栅极305顶部的绝缘材料204，露出305。
作为一个示例，参见图2、图3(D)和图3(E)所示，通过刻蚀的工艺将掉沟道区304边界外部多余的栅极电极层205和沉积于其表面的绝缘材料204，同时将沉积于栅极305上部的绝缘材料204刻蚀掉，露出栅极305。
参见图2至和图3(E)所示，根据本发明第二实施例的全包围栅极的器件结构，包括：
形成在基底301的顶层衬底103中的源极区302、漏极区303以及在源极区302、漏极区303之间的沟道区304；形成在沟道区304两侧的贯穿顶层衬底103的孔201；形成在沟道区304下方的空腔202，孔201与空腔202连通；形成在沟道区304上表面、孔201和空腔202靠近沟道区304的壁面的栅极结构。
作为可选方案，栅极结构包括栅介质层203及覆盖栅介质层203的栅极305，栅极305的材料为多晶硅。
作为可选方案，还包括：形成在栅极305顶面的金属硅化物。
作为可选方案，孔201内填充有绝缘材料。
通过全包围的栅极结构，增加栅极对沟道的控制能力，提高击穿电压，同时提高电流Ids，简化MOS晶体管的栅极绝缘层的生长工艺，便于大批量生产。
以上已经描述了本发明的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。

Claims (18)

1.一种晶体管的制作方法，其特征在于，包括：
提供基底，所述基底由下至上依次包括底层衬底、绝缘层和顶层衬底；
在所述顶层衬底形成源极区和漏极区，在所述源极区和漏极区之间形成沟道区，所述源极区至漏极区的方向为第一方向，垂直所述第一方向为第二方向；
在垂直于所述第一方向和所述第二方向的第三方向上，所述沟道区两侧形成贯穿所述顶层衬底的孔；
通过所述孔刻蚀所述孔下方及所述沟道区下方的绝缘层，以形成空腔，所述空腔与所述孔连通；
形成栅极结构，覆盖所述沟道区上表面、所述孔和所述空腔靠近沟道区的壁面，所述栅极结构包括栅介质层及覆盖所述栅介质层的栅极。
2.根据权利要求1所述的晶体管的制作方法，其特征在于，形成所述孔的方法包括：
在所述基底表面形成图形化的掩模层，定义出所述孔的位置；
以所述图形化的掩模层为掩模，刻蚀所述基底以形成所述孔。
3.根据权利要求2所述的晶体管的制作方法，其特征在于，所述形成空腔的方法包括：
以所述图形化的掩模层为掩模，刻蚀所述绝缘层以形成所述空腔。
4.根据权利要求3所述的晶体管的制作方法，其特征在于，所述刻蚀包括湿法刻蚀或干法刻蚀。
5.根据权利要求3所述的晶体管的制作方法，其特征在于，所述绝缘层为氧化硅。
6.根据权利要求4所述的晶体管的制作方法，其特征在于，所述湿法刻蚀使用的溶液为浓度为10％-20％的HF。
7.根据权利要求1所述的晶体管的制作方法，其特征在于，所述栅介质层包括氧化层。
8.根据权利要求7所述的晶体管的制作方法，其特征在于，通过热氧化或原子层沉积，形成所述氧化层。
9.根据权利要求1所述的晶体管的制作方法，其特征在于，所述栅极的形成方法包括：
在所述栅极介质层表面形成栅极电极层；
图形化所述栅极电极层，形成所述栅极。
10.根据权利要求9所述的晶体管的制作方法，其特征在于，所述栅极材料为多晶硅或金属。
11.根据权利要求10所述的晶体管的制作方法，其特征在于，还包括，当所述栅极材料为多晶硅时，对所述栅极电极层进行原位掺杂。
12.根据权利要求9所述的晶体管的制作方法，其特征在于，还包括：对所述栅极的顶面进行金属化生成金属硅化物。
13.根据权利要求1所述的晶体管的制作方法，其特征在于，形成所述栅极结构后，还包括：在所述孔内填充绝缘材料。
14.一种全包围栅极器件结构，其特征在于，包括：
形成在所述基底的顶层衬底中的源极区、漏极区以及在所述源极区、漏极区之间的沟道区；
形成在沟道区两侧的贯穿所述顶层衬底的孔；
形成在所述沟道区下方的空腔，所述孔与所述空腔连通；
形成在所述沟道区上表面、所述孔和所述空腔靠近沟道区的壁面的栅极结构。
15.根据权利要求14所述的全包围栅极器件结构，其特征在于，所述栅极结构包括栅介质层及覆盖所述栅介质层的栅极。
16.根据权利要求14所述的全包围栅极器件结构，其特征在于，所述栅极的材料为多晶硅或金属。
17.根据权利要求15所述的全包围栅极器件结构，其特征在于，还包括：形成在所述栅极顶面的金属硅化物。
18.根据权利要求14所述的全包围栅极器件结构，其特征在于，所述孔内填充有绝缘材料。
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