CN110429024B - 层间绝缘层及薄膜晶体管的制备方法 - Google Patents

层间绝缘层及薄膜晶体管的制备方法 Download PDF

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CN110429024B
CN110429024B CN201910730276.8A CN201910730276A CN110429024B CN 110429024 B CN110429024 B CN 110429024B CN 201910730276 A CN201910730276 A CN 201910730276A CN 110429024 B CN110429024 B CN 110429024B
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film layer
layer
silicon nitride
nitride film
silicon oxide
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王明
赵策
宋威
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BOE Technology Group Co Ltd
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Abstract

本发明提供一种层间绝缘层及薄膜晶体管的制备方法，属于显示技术领域，其可解决现有的层间绝缘层抗击穿能力较差的问题。本发明的层间绝缘层的制备方法包括：利用第一反应性气体形成氧化硅膜层和利用第二反应性气体形成氮化硅膜层，以使所形成的氮化硅膜层中的氢含量小于或者等于氧化硅膜层中的氢含量。

Description

层间绝缘层及薄膜晶体管的制备方法
技术领域
本发明属于显示技术领域，具体涉及一种层间绝缘层及薄膜晶体管的制备方法。
背景技术
大尺寸有机发光二极管(organic light-emitting diode，OLED)显示产品中由于栅极与金属层的厚度较厚，其中间的层间绝缘层也同样相对较厚。目前一般采用沉积两层氧化硅膜层的方式形成较厚的层间绝缘层。
发明人发现现有技术中至少存在如下问题：氧化硅膜层硬度较硬，且介电常数较低，受到栅极和金属层的电压影响，容易被击穿，从而影响显示产品的显示效果。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种层间绝缘层及薄膜晶体管的制备方法。
解决本发明技术问题所采用的技术方案是一种层间绝缘层的制备方法，包括形成氧化硅膜层和氮化硅膜层的步骤；所述形成氧化硅膜层和氮化硅膜层的步骤，包括：
利用第一反应性气体形成氧化硅膜层和利用第二反应性气体形成氮化硅膜层，以使所形成的氮化硅膜层中的氢含量小于或者等于氧化硅膜层中的氢含量。
可选地，所述利用第一反应性气体形成氧化硅膜层，包括：
利用甲硅烷和一氧化二氮，沉积形成氧化硅膜层。
可选地，所述利用第二反应性气体形成氮化硅膜层，包括：
利用三硅胺和氮气，沉积形成氮化硅膜层。
可选地，所述氧化硅膜层中的氢含量为1％至2％；所述氮化硅膜层中的氢含量为1％至2％。
可选地，所述氮化硅膜层的介电常数高于所述氧化硅膜层的介电常数。
可选地，所述氧化硅膜层的厚度大于2500埃，所述氮化硅膜层的厚度大于2500埃。
解决本发明技术问题所采用的技术方案是一种薄膜晶体管的制备方法，该薄膜晶体管的制备方法包括：如上述的层间绝缘层的制备方法。
可选地，形成包括氧化硅膜层和氮化硅膜层组成的层间绝缘层之前，包括：
在基底上依次形成有源层、栅极绝缘层和栅极。
可选地，所述有源层包括氧化物有源层；
形成所述层间绝缘层的步骤包括：依次形成所述氧化硅膜层和所述氮化硅膜层。
可选地，形成包括氧化硅膜层和氮化硅膜层组成的层间绝缘层之后，包括：
通过构图工艺，形成贯穿于所述氧化硅膜层和所述氮化硅膜层的源极接触过孔和漏极接触过孔；
在所述氮化硅膜层上源极和漏极，使得所述源极通过所述源极接触过孔与所述有源层连接，所述漏极通过所述漏极接触过孔与所述有源层连接。
附图说明
图1为一种顶栅型薄膜晶体管的结构示意图；
图2为本发明实施例提供的一种层间绝缘层的结构示意图；
图3为本发明实施例提供的一种层间绝缘层的制备方法的流程图；
图4为本发明实施例提供的氢含量测试结果示意图；
图5为本发明实施例提供的一种薄膜晶体管的制备方法的流程图；
图6a-图6g为本发明实施例提供的一种薄膜晶体管的制备方法的示意图。
其中附图标记为：101-基底、102-有源层、103-栅极绝缘层、104-栅极、105-层间绝缘层、106-源极、107-漏极、108-源极接触过孔、109-漏极接触孔、201-氧化硅膜层、及202-氮化硅膜层。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
本发明实施例提供的层间绝缘层主要是以应用于薄膜晶体管中为例进行说明。其中，薄膜晶体管一般分为顶栅型薄膜晶体管和底栅型薄膜晶体管，在本实施例中是以顶栅型薄膜晶体管为例进行说明。图1为一种顶栅型薄膜晶体管的结构示意图，如图1所示，顶栅型薄膜晶体管包括：依次设置在基底101上的有源层102、栅极绝缘层103、栅极104、层间绝缘层105、同层设置的源极106和漏极107，源极106通过贯穿于层间绝缘层105的源极接触过孔108和与有源层102连接，漏极107通过贯穿于层间绝缘层105的漏极接触孔109与有源层102连接。在现有技术中，层间绝缘层105可以由氧化硅膜层和氮化硅膜层的双层结构的复合膜层组成，而对于这双层结构通常采用化学气相沉积、低温沉积等方式制备而成。采用上述方式形成的氮化硅膜层中，氢原子通常以Si-H、Si-O或N-H键的方式残留在膜层中，氢含量对层间绝缘层105的结构、应力、抗腐蚀性能具有很大的影响，同时，氢含量对于有源层102的稳定性具有极大影响。为解决该问题，目前主要采用沉积两层氧化硅膜层的方式制备层间绝缘层105，其中氧化硅膜层制备过程中的反应气体氢含量较低，可以降低对薄膜晶体管中有源层102稳定性的影响，但是两层氧化硅膜层的质地较硬且抗击穿能力较低，在实际应用中容易被击穿而造成的短路。为此本实施例提供以下方法制备一种氧化硅膜层和氮化硅膜层组成的双层结构的层间绝缘层及其薄膜晶体管。
在此需要说明的是，对于氧化硅膜层和氮化硅膜层的材料本身不含氢，而在本发明实施例中所谓的氧化硅膜层中的氢含量和氮化硅膜层中的氢含量指的是在各个膜层制备过程中采用的反应气体中的氢以Si-H、Si-O或N-H键的方式残留在膜层中的氢含量。
实施例一
图2为本发明实施例提供的一种层间绝缘层的结构示意图，如图2所示，该层间绝缘层由氧化硅膜层201和氮化硅膜层202组成。本发明实施例提供了的一种层间绝缘层的制备方法，可以用于制备如图2所示的层间绝缘层。该层间绝缘层的制备方法包括：利用第一反应性气体形成氧化硅膜层和利用第二反应性气体形成氮化硅膜层，以使所形成的氮化硅膜层中的氢含量小于或者等于氧化硅膜层中的氢含量。
在本发明实施例中，首先，可以利用第一反应气体形成一层氧化硅膜层201，一般情况下，形成的氧化硅膜层201中含有较低的氢含量，可以降低整体层间绝缘层105中氢含量对有源层102稳定性的影响。之后，在氧化硅膜层201上利用第二反应气体形成一层氮化硅膜层202，形成的氮化硅膜层202同样含有较低的氢含量，并且形成的氮化硅膜层202中的氢含量小于或者等于氧化硅膜层201中的氢含量。可以理解的是，用于形成的氧化硅膜层201中的氢含量一般较低，在本发明实施例中形成的氮化硅膜层202中的氢含量较形成的氧化硅膜层201中的氢含量更低，因此，可以保证形成的氮化硅膜层202中均含有较低的氢含量，从而整体的层间绝缘层105中含有较低的氢含量，进而可以降低对有源层102稳定性的影响。同时，由于氮化硅膜层202的材料特性，其质地较软，且介电常数较高，具有较高的抗击穿能力，因此，可以提高整体层间绝缘层的抗击穿能力，从而可以有效提高产品良率，进而提高显示产品的显示效果。
可以理解的是，利用本发明实施例提供的层间绝缘层的制备方法制备而成的层间绝缘层105中的氧化硅膜层201和氮化硅膜层202的层数可以均为一层，也可以均为多层，氧化硅膜层201和氮化硅膜层202均为多层时，二者交替形成，且整体层间绝缘层105的两外表面层至少一层为氧化硅膜层201。当然，也可以根据实际需要选择制备氧化硅膜层201和氮化硅膜层202的制备顺序。
本发明实施例中，以形成一层氧化硅膜层201和一层氮化硅膜层202的双层结构的层间绝缘层为例，对该层间绝缘层的制备方法进行具体说明。图3为本发明实施例提供的一种层间绝缘层的制备方法的流程图，如图3所示，该层间绝缘层的制备方法包括如下步骤：
S301，利用甲硅烷和一氧化二氮，沉积形成氧化硅膜层。
需要说明的是，可以利用甲硅烷和一氧化二氮作为反应气体，可以在温度为300摄氏度(℃)下，将甲硅烷和一氧化二氮按照对应的流速输入反应室，在压强为1.0托(Torr)的环境中，利用电场将甲硅烷和一氧化二氮气体分子电离成原子状态，各原子之间相互反应，从而沉积形成氧化硅膜层。可以理解的是，可以根据实际应用，调整甲硅烷和一氧化二氮气体的流速，以形成质地均匀的氧化硅膜层，其具体范围可以参照现有技术中形成氧化硅膜层的各反应气体的流速，在此不再列举。在本发明实施例中利用甲硅烷和一氧化二氮沉积形成的氧化硅膜层201中残留的氢含量较低，可以降低对有源层102的稳定性的影响。
S302，利用三硅胺和氮气，沉积形成氮化硅膜层。
需要说明的是，在现有技术中，可以利用甲硅烷、氨气和氮气三种反应气体，采用化学气相沉积的方式形成氮化硅膜层，然而，利用上述三种反应气体沉积形成氮化硅膜层的过程中，容易引入较多的氢，从而形成的氮化硅膜层中残留有较高的氢含量，较高的氢含量容易对有源层102的稳定性造成影响。为了减少形成的氮化硅膜层202中的氢含量，本发明实施例中可以利用三硅胺和氮气，可以在温度为250℃下，将三硅胺以3slm(升每分钟)至9slm的流速，和氮气以0.1slm至6slm的流速输入反应室，在压强为3torr的环境中，利用电场将三硅胺和氮气气体分子电离成原子状态，各原子之间相互反应，从而形成氮化硅膜层202。可以理解的是，可以根据实际应用，调整三硅胺和氮气气体的流速，以形成质地均匀的氮化硅膜层202。本发明实施例中利用三硅胺和氮气沉积形成的氮化硅膜层202，与现有技术中的利用甲硅烷、氨气和氮气沉积形成的氮化硅膜层202相比，利用本发明实施例提供的制备方法形成的氮化硅膜层202具有较低的氢含量，可以降低对有源层102的稳定性的影响。同时，形成的氮化硅膜层202质地较软，且介电常数较高，具有较高的抗击穿能力，因此，可以提高整体层间绝缘层105的抗击穿能力，从而提高显示产品的良率。其中，三硅胺的具体化学结构如下所示：
Figure BDA0002160301870000061
在此需要说明的是，步骤S301和S302的执行先后顺序，与该层间绝缘层制备的应用场景有关，例如在形成氧化物薄膜晶体管时，形成层间绝缘层在形成氧化物有源层之后，那么需要先执行步骤S301以形成氧化硅膜层，再执行步骤S302以形成氮化硅膜层；若形成层间绝缘层在形成氧化物有源层之前，那么需要先执行步骤S302以形成氧化硅膜层，再执行步骤S301以形成氮化硅膜层。
可选地，氧化硅膜层中的氢含量为1％至2％；氮化硅膜层中的氢含量为1％至2％。
在一个具体地例子中，图4为本发明实施例提供的氢含量测试结果示意图，如图4所示，本发明实施例提供的利用三硅胺和氮气形成的氮化硅膜层202中的氢含量为1.8％，利用甲硅烷和一氧化二氮形成的氧化硅膜层201中的氢含量为1.9％，而现有技术中利用甲硅烷、氨气和氮气形成的氮化硅膜层202中的氢含量为22％，因此，可以看出，利用本发明实施例提供的制备方法形成的氧化硅膜层201和氮化硅膜层202均具有较低的氢含量，从而，整体层间绝缘层105具有较低的氢含量，可以降低对于有源层102的稳定性的影响。
可选地，氮化硅膜层202的介电常数高于氧化硅膜层201的介电常数。
需要说明的是，介电常数为表征电介质或绝缘材料电性能的一个重要数据，膜层材料的介电常数越高，其抗击穿能力越强。在本发明实施例中，氮化硅膜层202的介电常数高于氧化硅膜层201的介电常数，因此，较高介电常数的氮化硅膜层可以提高整体层间绝缘层105的抗击穿能力，进而提高显示产品的良率。
可选地，氧化硅膜层201的厚度大于2500埃，氮化硅膜层202的厚度大于2500埃。
需要说明的是，氧化硅膜层201和氮化硅膜层202组成的双层或多层结构可以组成较厚的整体层间绝缘层105，以形成良好的绝缘效果，避免层间绝缘层105被两侧形成的电场击穿。一般层间绝缘层105的厚度大于5000埃，其中的氧化硅膜层的厚度可以大于2500埃，氮化硅膜层的厚度可以大于2500埃。也可以根据实际需要，形成氧化硅膜层201和氮化硅膜层202交替设置的多层结构的层间绝缘层105。可以理解的是，在实际应用中，氧化硅膜层201和氮化硅膜层202也可以为其他的厚度。
实施例二
本发明实施例将以顶栅型薄膜晶体管为例，结合附图对本发明提供的薄膜晶体管的制备方法进行进一步详细说明。其中的层间绝缘层105为由上述实施例提供的层间绝缘层的制备方法形成的双层结构的层间绝缘层105。图5为本发明实施例提供的一种薄膜晶体管的制备方法的流程图，如图5所示，该薄膜晶体管的制备方法包括如下步骤(其中步骤S502即上述实施例提供的层间绝缘层的制备方法的步骤)：
S501，在基底上依次形成有源层、栅极绝缘层和栅极。
在步骤S501中，可以采用一次构图工艺在基底101上形成有源层102、栅极绝缘层103和栅极104的图形。具体地，可以在制备过程中首先对基底101初始清洗，如图6a所示，可以在基底101上沉积一层有源层102的材料，有源层102的材料可以为半导体材料，具体可以为氧化铟锡或氧化铟锡等金属氧化物材料。然后，如图6b所示，在至少覆盖有源层102的位置处沉积栅极绝缘层103的材料，形成栅极绝缘层103。该栅极绝缘层103的材料可以为很薄的一层氧化硅材料，可以使得有源层102与其上的栅极104绝缘，避免栅极104电压对有源层102的造成影响。最后，如图6c，在栅极绝缘层103上沉积栅极104金属层，并在栅极104金属层上涂覆光刻胶，该栅极104的材料可以为铜等导体，可以通过对栅极104金属层曝光、显影、后烘、刻蚀、光刻胶剥离等步骤形成包括有源层102、栅极绝缘层103和栅极104图案。
S502，在栅极上形成包括氧化硅膜层和氮化硅膜层组成的层间绝缘层。
在步骤S502中，在栅极104上沉积一层氧化硅材料和一层氮化硅材料，形成包括氧化硅膜层201和氮化硅膜层202的双层结构的层间绝缘层105。该薄膜晶体管为氧化物薄膜晶体管时，其中的有源层102包括氧化物有源层，具体可以为氧化铟锌或氧化铟锡等金属氧化物。该薄膜晶体管为氧化物薄膜晶体管时，步骤S502具体可以包括如下子步骤：
S5021，利用甲硅烷和一氧化二氮，沉积形成氧化硅膜层。
具体地，如图6d所示，可以利用甲硅烷和一氧化二氮作为反应气体，在栅极104上沉积形成氧化硅膜层201，其中，利用甲硅烷和一氧化二氮形成的氧化硅膜层201中的氢含量较低，可以降低对氧化物有源层的稳定性的影响。
S5022，利用三硅胺和氮气，沉积形成氮化硅膜层。
具体地，如图6e所示，可以利用三硅胺和氮气作为反应气体，在氧化硅膜层201上沉积形成氮化硅膜层202，其中，利用三硅胺和氮气形成的氮化硅膜层202中的氢含量较低，可以降低对氧化物有源层的稳定性的影响。同时，形成的氮化硅膜层202质地较软，且介电常数较高，具有较高的抗击穿能力，因此，可以提高整体层间绝缘层105的抗击穿能力。
需要说明的是，薄膜晶体管为氧化物薄膜晶体管时，上述步骤S5021和步骤S5022的顺序为首先执行步骤S5021，形成覆盖栅极104的氧化硅膜层，再执行步骤S5022，在氧化硅膜层201上形成氮化硅膜层202。
S503，通过构图工艺，形成贯穿于氧化硅膜层和氮化硅膜层的源极接触过孔和漏极接触过孔。
具体的，如图6f所示，在氮化硅膜层202上涂覆光刻胶，通过曝光、显影、后烘后，对层间绝缘层105中的氧化硅膜层201和氮化硅膜层202进行刻蚀，并剥离光刻胶，形成与源极106对应的源极接触孔108，以及与漏极107对应的漏极接触过孔109。
S504，在氮化硅膜层上源极和漏极，使得源极通过源极接触过孔与有源层连接，漏极通过漏极接触过孔与有源层连接。
具体地，如图6g所示，在氮化硅膜层上沉积形成源极106和漏极107，源极106和漏极107均为金属层，由导电金属材料制成。源极106可以通过贯穿于氧化硅膜层201和氮化硅膜层202的源极接触孔108与有源层102连接，漏极107可以通过贯穿于氧化硅膜层201和氮化硅膜层202的漏极接触孔109与有源层102连接。至此，薄膜晶体管制备完成。可以在薄膜晶体管中预先形成栅线和数据线(图中未示出)，以方便该薄膜晶体管应用于阵列基板时的布线。其中，栅线与栅极104同层设置，栅线与栅极104电连接，可以采用相同的材料且在同一构图工艺中形成。数据线与源极106同层设置，数据线与源极106电连接，可以采用相同的材料且在同一构图工艺中形成。栅极104可以通过栅线输入栅极电压，源极106可以通过数据线输入数据电压，位于栅极104和源极106之间的层间绝缘层105可以使得栅极104与源极106绝缘，避免短路。在本发明实施例中，氮化硅膜层202可以提高整体层间绝缘层105的抗击穿能力，避免被栅极104与源极106或漏极107之间形成的电场击穿，从而提高显示产品良率，进而提高显示效果。同时，形成的氧化硅膜层201和氮化硅膜202层中的氢含量较低，可以避免整体层间绝缘层105中的氢含量对有源层102的稳定性的影响。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (9)

1.一种层间绝缘层的制备方法，包括形成氧化硅膜层和氮化硅膜层的步骤；其特征在于，所述形成氧化硅膜层和氮化硅膜层的步骤，包括：
利用第一反应性气体形成氧化硅膜层和利用第二反应性气体形成氮化硅膜层，以使所形成的氮化硅膜层中的氢含量小于或者等于氧化硅膜层中的氢含量；
所述利用第二反应性气体形成氮化硅膜层，包括：
利用三硅胺和氮气，沉积形成氮化硅膜层；所述氮化硅膜层中的氢含量为1％至2％；其中，反应温度为250℃以下，压强为3torr，三硅胺的流速为3slm至9slm，氮气的流速为0.1slm至6slm时，所述氮化硅膜层中的氢含量为1.8％。
2.根据权利要求1所述的层间绝缘层的制备方法，其特征在于，所述利用第一反应性气体形成氧化硅膜层，包括：
利用甲硅烷和一氧化二氮，沉积形成氧化硅膜层。
3.根据权利要求1所述的层间绝缘层的制备方法，其特征在于，所述氧化硅膜层中的氢含量为1％至2％。
4.根据权利要求1所述的层间绝缘层的制备方法，其特征在于，所述氮化硅膜层的介电常数高于所述氧化硅膜层的介电常数。
5.根据权利要求1所述的层间绝缘层的制备方法，其特征在于，所述氧化硅膜层的厚度大于2500埃，所述氮化硅膜层的厚度大于2500埃。
6.一种薄膜晶体管的制备方法，其特征在于，包括：如权利要求1-5任一项所述层间绝缘层的制备方法。
7.根据权利要求6所述的薄膜晶体管的制备方法，其特征在于，形成包括氧化硅膜层和氮化硅膜层组成的层间绝缘层之前，包括：
在基底上依次形成有源层、栅极绝缘层和栅极。
8.根据权利要求7所述的薄膜晶体管的制备方法，其特征在于，所述有源层包括氧化物有源层；
形成所述层间绝缘层的步骤包括：依次形成所述氧化硅膜层和所述氮化硅膜层。
9.根据权利要求8所述的薄膜晶体管的制备方法，其特征在于，形成包括氧化硅膜层和氮化硅膜层组成的层间绝缘层之后，包括：
通过构图工艺，形成贯穿于所述氧化硅膜层和所述氮化硅膜层的源极接触过孔和漏极接触过孔；
在所述氮化硅膜层上源极和漏极，使得所述源极通过所述源极接触过孔与所述有源层连接，所述漏极通过所述漏极接触过孔与所述有源层连接。
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700826A (zh) * 2004-05-20 2005-11-23 株式会社半导体能源研究所 发光元件和显示器件
CN1834288A (zh) * 2006-04-07 2006-09-20 中国科学院上海硅酸盐研究所 一种低温化学气相沉积制备氮化硅薄膜的方法
CN103022143A (zh) * 2011-09-27 2013-04-03 株式会社东芝 薄膜晶体管、用于制造该薄膜晶体管的方法、以及显示设备
CN104094418A (zh) * 2012-02-17 2014-10-08 应用材料公司 硅基太阳能电池的钝化薄膜堆叠
CN104285302A (zh) * 2012-05-10 2015-01-14 株式会社半导体能源研究所 半导体装置
CN107533974A (zh) * 2015-05-07 2018-01-02 德克萨斯仪器股份有限公司 低应力低氢型lpcvd氮化硅
CN109148596A (zh) * 2018-08-17 2019-01-04 武汉华星光电半导体显示技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN109920729A (zh) * 2019-03-27 2019-06-21 合肥鑫晟光电科技有限公司 一种显示基板的制备方法、显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200531253A (en) * 2003-09-19 2005-09-16 Koninkl Philips Electronics Nv Fuse structure for maintaining passivation integrity
JP4470023B2 (ja) * 2004-08-20 2010-06-02 レール・リキード−ソシエテ・アノニム・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード シリコン窒化物膜の製造方法
US7294581B2 (en) * 2005-10-17 2007-11-13 Applied Materials, Inc. Method for fabricating silicon nitride spacer structures
JP5394867B2 (ja) * 2009-09-17 2014-01-22 富士フイルム株式会社 ガスバリア膜およびガスバリアフィルム
KR101832361B1 (ko) * 2011-01-19 2018-04-16 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR102029286B1 (ko) * 2012-03-09 2019-10-07 버슘머트리얼즈 유에스, 엘엘씨 디스플레이 디바이스를 위한 배리어 물질
US8841665B2 (en) * 2012-04-06 2014-09-23 Electronics And Telecommunications Research Institute Method for manufacturing oxide thin film transistor
JP6224931B2 (ja) * 2012-07-27 2017-11-01 株式会社半導体エネルギー研究所 半導体装置
CN103887343B (zh) * 2012-12-21 2017-06-09 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
JP6232219B2 (ja) * 2013-06-28 2017-11-15 東京エレクトロン株式会社 多層保護膜の形成方法
WO2016076168A1 (ja) * 2014-11-11 2016-05-19 シャープ株式会社 半導体装置およびその製造方法
CN108028171A (zh) * 2015-09-18 2018-05-11 应用材料公司 氮化硅在高深宽比结构上的低温保形沉积
CN105609564B (zh) * 2016-03-14 2018-12-25 京东方科技集团股份有限公司 一种薄膜晶体管制造方法及薄膜晶体管
US20190067489A1 (en) * 2016-04-04 2019-02-28 Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.) Thin film transistor
US10468434B2 (en) * 2016-04-08 2019-11-05 Innolux Corporation Hybrid thin film transistor structure, display device, and method of making the same
JP6689140B2 (ja) * 2016-06-17 2020-04-28 東京エレクトロン株式会社 成膜方法およびｔｆｔの製造方法
KR102519120B1 (ko) * 2016-10-18 2023-04-06 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR20180046418A (ko) * 2016-10-27 2018-05-09 엘지디스플레이 주식회사 표시장치 및 그 제조방법
CN114975635A (zh) * 2017-05-31 2022-08-30 乐金显示有限公司 薄膜晶体管、包括其的栅极驱动器、以及包括该栅极驱动器的显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1700826A (zh) * 2004-05-20 2005-11-23 株式会社半导体能源研究所 发光元件和显示器件
CN1834288A (zh) * 2006-04-07 2006-09-20 中国科学院上海硅酸盐研究所 一种低温化学气相沉积制备氮化硅薄膜的方法
CN103022143A (zh) * 2011-09-27 2013-04-03 株式会社东芝 薄膜晶体管、用于制造该薄膜晶体管的方法、以及显示设备
CN104094418A (zh) * 2012-02-17 2014-10-08 应用材料公司 硅基太阳能电池的钝化薄膜堆叠
CN104285302A (zh) * 2012-05-10 2015-01-14 株式会社半导体能源研究所 半导体装置
CN107533974A (zh) * 2015-05-07 2018-01-02 德克萨斯仪器股份有限公司 低应力低氢型lpcvd氮化硅
CN109148596A (zh) * 2018-08-17 2019-01-04 武汉华星光电半导体显示技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN109920729A (zh) * 2019-03-27 2019-06-21 合肥鑫晟光电科技有限公司 一种显示基板的制备方法、显示装置

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