CN1819121A - 制作超高伸张应力膜以及应变硅晶体管的方法 - Google Patents

制作超高伸张应力膜以及应变硅晶体管的方法 Download PDF

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CN1819121A
CN1819121A CNA2005101288549A CN200510128854A CN1819121A CN 1819121 A CN1819121 A CN 1819121A CN A2005101288549 A CNA2005101288549 A CN A2005101288549A CN 200510128854 A CN200510128854 A CN 200510128854A CN 1819121 A CN1819121 A CN 1819121A
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nitride film
silicon nitride
stretching stress
making
hydrogen atom
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CN100431111C (zh
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陈能国
蔡腾群
黄建中
陈再富
洪文瀚
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United Microelectronics Corp
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Abstract

本发明披露一种制作超高伸张应力膜的方法，首先进行等离子体增强化学气相沉积工艺，于衬底的表面上沉积一过渡氮化硅膜，且该过渡氮化硅膜具有一第一氢原子浓度，接着对该过渡氮化硅膜进行UV照射工艺，将该过渡氮化硅膜的第一氢原子浓度降低至一第二氢原子浓度。

Description

制作超高伸张应力膜以及应变硅晶体管的方法
技术领域
本发明涉及一种半导体元件的制造方法，尤其涉及一种制作超高伸张应力膜以及应变硅(strained-silicon)晶体管的方法。
背景技术
随着半导体工艺进入到深亚微米时代，例如65纳米(nm)以下的工艺，对于MOS晶体管元件的驱动电流(drive current)的提升已显得日益重要。为了改善元件的效能，目前业界已发展出所谓的“应变硅(strained-silicon)技术”，其原理主要是使栅极沟道部分的硅晶格产生应变，使电荷在通过此应变的栅极沟道时的移动力增加，进而达到使MOS晶体管运作更快的目的。
基本上，硅晶格的应变可以藉由以下两种方式达到：第一种方式是利用形成在晶体管周围的应力薄膜，例如沉积在多晶硅栅极上的应力膜(polystressor)或者在硅化金属层形成后才沉积的接触孔蚀刻停止层(contact etchstop layer，CESL)，此方式又被称作“工艺诱发应变(process-induced strain)”；另一种方式则是直接利用应变硅晶片进行元件的制作。后者的应变硅晶片的作法是在晶格常数比硅大的半导体基材上成长出应变硅层。目前，大部分晶片制造业者都是采用前者来进行元件效能的改善与提升，而且主要是利用具有伸张应力(tensile stress)的氮化硅膜来改善NMOS元件的效能。如本领域技术人员所知，伸张应力可以提升电子的移动力，相反的，压缩应力(compressive stress)则可以提升空穴的移动力。
如本领域技术人员所知，若氮化硅膜的伸张应力值越高，则越能够提升NMOS晶体管的驱动电流，因此在晶体管元件的工艺上，业者无不希望能将氮化硅膜的伸张应力值制作的越高越好。更明确的说，根据业界对先进工艺所做的需求规划，目前65纳米工艺对于高伸张应力的氮化硅膜至少需要1.5GPa，而未来在进入下一代的45纳米工艺时，对于高伸张应力的氮化硅膜则至少需要到1.8GPa以上。然而，以目前的等离子体增强化学气相沉积(PECVD)技术水准，最多也仅能做出1.2GPa的伸张应力氮化硅膜，明显不足。
由此可知，该技术领域中亟需要一种制作超高伸张应力膜的方法，藉以应用在下一代的应变硅(strained-silicon)晶体管的工艺中。
发明内容
本发明的主要目的即在提供一种制作超高伸张应力膜的方法，藉以应用在下一代的应变硅晶体管的工艺中。
本发明的另一目的是提供一种应变硅晶体管，其中采用具有超高伸张应力膜作为工艺中的应力膜(poly stressor)或者接触孔蚀刻停止层(contactetch stop layer，CESL)。
根据本发明的优选实施例，本发明提供一种制作超高伸张应力氮化硅膜的方法，主要包括以下步骤：
(1)提供一衬底；
(2)进行一等离子体增强化学气相沉积(PECVD)工艺，于该衬底上沉积一过渡氮化硅膜，其中该过渡氮化硅膜具有一第一氢原子浓度；及
(3)进行一后处理步骤，将该过渡氮化硅膜内的该第一氢原子浓度降低至一第二氢原子浓度，藉此将该过渡氮化硅膜转变成该超高伸张应力氮化硅膜。
根据本发明的另一优选实施例，本发明提供一种制作应变硅晶体管的方法，主要包括以下步骤：
(1)提供一半导体衬底；
(2)于该半导体衬底上形成一栅极结构；
(3)于该栅极结构两侧的该半导体衬底上形成一漏极/源极区域；
(4)进行一等离子体增强化学气相沉积(PECVD)工艺，于该半导体衬底上沉积一过渡氮化硅膜，其中该过渡氮化硅膜具有一第一氢原子浓度，且该过渡氮化硅膜覆盖住该栅极结构以及该漏极/源极区域；及
(5)进行一后处理步骤，将该过渡氮化硅膜内的该第一氢原子浓度降低至一第二氢原子浓度，藉此将该过渡氮化硅膜转变成该超高伸张应力氮化硅膜。
根据本发明的另一优选实施例，本发明提供一种金属氧化物半导体(MOS)晶体管元件，包括：一半导体衬底；一栅极结构，设于该半导体衬底上；一漏极/源极区域，设于该栅极结构两侧的该半导体衬底中；一超高伸张应力氮化硅膜，覆盖在该栅极结构以及该漏极/源极区域上方，其中该超高伸张应力氮化硅膜的伸张应力值大于或等于1.5GPa；以及一层间介电膜，设于该超高伸张应力氮化硅膜的上方。
为了使本领域技术人员能更进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图。然而附图仅供参考与辅助说明用，并非用来对本发明加以限制。
附图说明
图1至图8绘示的是本发明优选实施例制作应变硅NMOS晶体管的方法的剖面示意图；
图9绘示的是经过后处理的氮化硅膜中的最终氢原子浓度与其伸张应力值之间的关系图；
图10绘示的是氮化硅膜中被移除的氢原子数量(ΔH)与所测得的伸张应力值之间的关系图；
图11绘示的是刚以PECVD沉积完成的氮化硅膜与经过UV后处理的氮化硅膜的傅立叶变换红外线光谱图(FTIR)；
图12至15绘示的是本发明另一优选实施例采应力膜工艺以制作MOS晶体管的方法的剖面示意图。
主要元件符号说明
10    半导体衬底             12    栅极结构
14    栅极氧化层             16    栅极电极层
18    间隙壁                 20    浅沟绝缘结构
26    轻掺杂源极/漏极区域    30    离子注入工艺
38    间隙壁                 40    离子注入工艺
46    重掺杂源极/漏极区域    52    硅化金属层
60    伸张应力氮化硅膜       62    超高伸张应力氮化硅膜
70    后处理步骤             80    层间介电层
82    接触孔开口
具体实施方式
请参阅图1至图8，其绘示的是本发明优选实施例制作应变硅NMOS晶体管的方法的剖面示意图。首先，如图1所示，提供一半导体衬底10，其上形成有一栅极结构12，且半导体衬底10上另提供有浅沟绝缘结构20，用来隔离元件。栅极结构12包括一栅极氧化层14、一栅极电极层16以及一间隙壁18。其中，栅极氧化层14可以是由二氧化硅所构成，栅极电极层16可以是由掺杂多晶硅所构成，但不限于此。
前述的半导体衬底10可以是硅衬底、硅覆绝缘(silicon-on-insulator，SOI)基材或者包括有外延层(epitaxial layer)的半导体基材。前述的外延层可以是由单晶硅外延或者由硅锗应变的外延层。
如图2所示，接着进行一离子注入工艺30，以于靠近间隙壁18的半导体衬底10中注入掺杂剂，形成轻掺杂源极/漏极区域26。
如图3所示，接着于栅极结构12两侧壁上形成氮化硅间隙壁38，其形成方式是先在半导体衬底10表面上沉积一氮化硅薄膜，然后利用各向异性干蚀刻技术回蚀刻该氮化硅薄膜。
接下来，如图4所示，完成间隙壁38之后，再进行一离子注入工艺40，于靠近间隙壁38的半导体衬底10中注入如砷或磷等掺杂剂，形成重掺杂源极/漏极区域46。随后，可继续进行一快速热处理(RTP)，将注入半导体衬底10内的掺杂剂加以活化，同时将离子注入工艺所产生在半导体衬底10表面上的损坏晶格加以修复。
如图5所示，接着进行一自对准硅化金属(self-aligned silicide or salicide)工艺，于漏极/源极区域46上以及栅极电极层16上各形成一硅化金属层52。自对准硅化金属工艺是先在半导体衬底10上溅镀沉积一金属层，例如钴或镍，然后再使金属层与下方的硅发生反应，最后去除未反应的金属层。
如图6所示，接下来进行一等离子体增强化学气相沉积(PECVD)工艺，在半导体衬底10上沉积一厚度约为500至1000埃左右的伸张应力氮化硅膜60。根据本发明的优选实施例，伸张应力氮化硅膜60的沉积是利用硅烷(silane)以及氨气(ammonia)作为主要的反应气体。此外，根据本发明的优选实施例，前述的PECVD工艺所使用的低频无线电频率功率(low-frequencyRF power)在50至2700瓦特(Watt)之间，高频无线电频率功率(high-frequencyRF power)在100至200瓦特(Watt)之间，优选小于150瓦特，而硅烷与氨气的流量比率(silane/ammonia ratio)则介于2至20之间。
根据本发明的优选实施例，伸张应力氮化硅膜60是在工艺参数的控制之下所形成具有特别的硅-氢键(Si-H)/氮-氢键(N-H)比例的氮化硅组成，其中伸张应力氮化硅膜60的硅-氢键(Si-H)/氮-氢键(N-H)比例可以在0.1至10之间，优选在1.0左右。本发明的特征之一在于伸张应力氮化硅膜60中硅-氢键的浓度约介于1E22至5E23atoms/cm3之间，伸张应力氮化硅膜60中氮-氢键的浓度约介于1E22至5E23atoms/cm3之间，而伸张应力氮化硅膜60中氢原子的总浓度约介于1E22至1E24atoms/cm3之间，优选为大于3E22atoms/cm3。伸张应力氮化硅膜60此时的应力值约介于0-1.2GPa左右。根据本发明，应使伸张应力氮化硅膜60中的氢原子总浓度在前述的范围中越高越好。
如图7所示，接着对伸张应力氮化硅膜60进行一后处理步骤70，进行伸张应力氮化硅膜60的熟化。后处理步骤70的目的在于将伸张应力氮化硅膜60中的氢原子浓度尽可能地降低。根据本发明的优选实施例，后处理步骤70可以是在真空环境下进行的紫外线照射熟化步骤(UV curingprocess)，其进行的温度约在300℃至1200℃之间，照射时间约为1至30秒之间。在其它实施例中，后处理步骤70也可以是快速热处理(RTP)工艺。在完成前述的紫外线照射熟化步骤之后，即形成一超高伸张应力氮化硅膜62。
根据本发明的优选实施例，经过后处理的氮化硅膜62具有的硅-氢键(Si-H)/氮-氢键(N-H)比例约介于0.1至10之间，优选为0.3左右。氮化硅膜62中的硅-氢键的浓度约介于1E18至5E22atoms/cm3之间，氮化硅膜62中氮-氢键的浓度约介于1E18至5E22atoms/cm3之间，而氮化硅膜62中氢原子总浓度约介于1E18至5E22atoms/cm3之间，优选为1E22atoms/cm3，更优选为5E21atoms/cm3以下。
如图8所示，接下来在氮化硅膜62上沉积一层间介电(inter-layerdielectric，ILD)膜80，例如硅氧膜。然后，利用光刻以及蚀刻工艺，在ILD膜80以及氮化硅膜62中形成接触孔开口82，暴露出部分形成在漏极/源极区域46上的硅化金属层52。
请参阅图9，经过实验的证实，经过后处理的氮化硅膜62若其氢原子浓度可以降低至1E22atoms/cm3以下，所测得的伸张应力值即可以提高至1.6GPa左右。图10绘示的是氮化硅膜中被移除的氢原子数量(ΔH)与所测得的伸张应力值之间的关系图，如图10所示，经过实验的证实，若被移除的氢原子数量(ΔH)越多，氮化硅膜62的伸张应力值可以越高，此亦为本发明的重点。根据本发明的优选实施例，若要得到较高的伸张应力值，则ΔH建议应大于1E22atoms/cm3，甚至建议应大于1.4E22atoms/cm3。本发明的特点在于后处理步骤前、后的氢原子浓度的改变会造成伸张应力氮化硅膜60内原子排列的改变，然后造成挤压的现象，才会产生如此高应力的结果。
请参阅图11，其绘示的是刚以PECVD沉积完成的氮化硅膜与经过UV后处理的氮化硅膜的傅立叶变换红外线光谱图(FTIR)，其中显示氮化硅膜在经过UV后处理之后的硅-氢键(Si-H)的浓度与氮-氢键(N-H)的浓度同时下降许多。本发明利用UV后处理，藉由将氮化硅膜的硅-氢键(Si-H)与氮-氢键(N-H)同时打断，降低氢原子浓度，藉此提高氮化硅膜的伸张应力。
如前述，本发明的超高伸张应力氮化硅膜也可以应用在多晶硅栅极上的应力膜工艺。请参阅图12至15，其绘示的是本发明另一优选实施例采用应力膜工艺以制作MOS晶体管的方法的剖面示意图。首先，如图12所示，提供一半导体衬底10，其上形成有一栅极结构12，且半导体衬底10上另提供有浅沟绝缘结构20，用来隔离元件。栅极结构12包括一栅极氧化层14、一栅极电极层16以及一间隙壁18。其中，栅极氧化层14可以是由二氧化硅所构成，栅极电极层16可以是由掺杂多晶硅所构成，但不限于此。
同样的，前述的半导体衬底10可以是硅衬底、硅覆绝缘(SOI)基材或者包括有外延层的半导体基材。前述的外延层可以是由单晶硅外延或者由硅锗应变的外延层。
如图13所示，接着进行一离子注入工艺30，以于靠近间隙壁18的半导体衬底10中注入掺杂剂，形成掺杂源极/漏极区域26。
如图14所示，接下来进行一等离子体增强化学气相沉积(PECVD)工艺，在半导体衬底10上沉积一伸张应力氮化硅膜60，其覆盖住栅极结构12以及掺杂源极/漏极区域26。根据本发明的优选实施例，伸张应力氮化硅膜60的沉积是利用硅烷以及氨气作为主要的反应气体。此外，根据本发明的优选实施例，前述的PECVD工艺所使用的低频无线电频率功率在50至2700瓦特之间，高频无线电频率功率在100至200瓦特之间，优选小于150瓦特，而硅烷与氨气的流量比率(silane/ammonia ratio)则介于2至20之间。
根据本发明的优选实施例，伸张应力氮化硅膜60是在工艺参数的控制之下所形成具有特别的Si-H/N-H比例的氮化硅组成，其中伸张应力氮化硅膜60的Si-H/N-H比例可以在0.1至10之间，优选在1.0左右。本发明的特征之一在于伸张应力氮化硅膜60中硅-氢键的浓度约介于1E22至5E23atoms/cm3之间，伸张应力氮化硅膜60中氮-氢键的浓度约介于1E22至5E23atoms/cm3之间，而伸张应力氮化硅膜60中氢原子的总浓度约介于1E22至1E24atoms/cm3之间，优选为大于3E22atoms/cm3。伸张应力氮化硅膜60此时的应力值约介于0-1.2GPa左右。根据本发明，应使伸张应力氮化硅膜60中的氢原子总浓度在前述的范围中越高越好。
如图15所示，接着对伸张应力氮化硅膜60进行一后处理步骤70，进行伸张应力氮化硅膜60的熟化。后处理步骤70的目的在于将伸张应力氮化硅膜60中的氢原子浓度尽可能地降低。根据本发明的优选实施例，后处理步骤70可以是在真空环境下进行的紫外线照射熟化步骤(UV curingprocess)。在完成前述的紫外线照射熟化步骤之后，即形成一超高伸张应力氮化硅膜62。
根据本发明的优选实施例，经过后处理的氮化硅膜62具有的硅-氢键(Si-H)/氮-氢键(N-H)比例约介于0.1至10之间，优选为0.3左右。氮化硅膜62中的硅-氢键的浓度约介于1E18至5E22atoms/cm3之间，氮化硅膜62中氮-氢键的浓度约介于1E18至5E22atoms/cm3之间，而氮化硅膜62中氢原子总浓度约介于1E18至5E22atoms/cm3之间，优选为1E22atoms/cm3，更优选为5E21atoms/cm3以下。这层超高伸张应力氮化硅膜62在造成栅极沟道的应变之后，随后被去除。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (28)

1.一种制作超高伸张应力氮化硅膜的方法，包括：
提供一衬底；
进行一等离子体增强化学气相沉积工艺，于该衬底上沉积一过渡氮化硅膜，其中该过渡氮化硅膜具有一第一氢原子浓度；以及
进行一后处理步骤，将该过渡氮化硅膜内的该第一氢原子浓度降低至一第二氢原子浓度，藉此将该过渡氮化硅膜转变成该超高伸张应力氮化硅膜。
2.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该过渡氮化硅膜的沉积是利用硅烷以及氨气作为主要的反应气体。
3.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该等离子体增强化学气相沉积工艺所使用的低频无线电频率功率在50至2700瓦特之间，高频无线电频率功率在100至200瓦特之间。
4.如权利要求3所述的制作超高伸张应力氮化硅膜的方法，其中该高频无线电频率功率小于150瓦特。
5.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该后处理步骤包括一紫外线照射步骤。
6.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该第一氢原子浓度与该第二氢原子浓度之间的差值大于1E22atoms/cm3。
7.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该第一氢原子浓度是在1E22至1E24atoms/cm3之间。
8.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该第二氢原子浓度是在1E18至5E22atoms/cm3之间。
9.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该过渡氮化硅膜的硅-氢键/氮-氢键比例约为1.0。
10.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该超高伸张应力氮化硅膜的硅-氢键/氮-氢键比例约为0.3。
11.如权利要求1所述的制作超高伸张应力氮化硅膜的方法，其中该超高伸张应力氮化硅膜的伸张应力值大于或等于1.5GPa。
12.一种制作应变硅晶体管的方法，包括：
提供一半导体衬底；
于该半导体衬底上形成一栅极结构；
于该栅极结构两侧的该半导体衬底上形成一漏极/源极区域；
进行一等离子体增强化学气相沉积工艺，于该半导体衬底上沉积一过渡氮化硅膜，其中该过渡氮化硅膜具有一第一氢原子浓度，且该过渡氮化硅膜覆盖住该栅极结构以及该漏极/源极区域；以及
进行一后处理步骤，将该过渡氮化硅膜内的该第一氢原子浓度降低至一第二氢原子浓度，藉此将该过渡氮化硅膜转变成一超高伸张应力氮化硅膜。
13.如权利要求12所述的制作应变硅晶体管的方法，其中该过渡氮化硅膜的沉积是利用硅烷以及氨气作为主要的反应气体。
14.如权利要求12所述的制作应变硅晶体管的方法，其中该等离子体增强化学气相沉积工艺所使用的低频无线电频率功率在50至2700瓦特之间，高频无线电频率功率在100至200瓦特之间。
15.如权利要求14所述的制作应变硅晶体管的方法，其中该高频无线电频率功率小于150瓦特。
16.如权利要求12所述的制作应变硅晶体管的方法，其中该后处理步骤包括一紫外线照射步骤。
17.如权利要求12所述的制作应变硅晶体管的方法，其中该第一氢原子浓度与该第二氢原子浓度之间的差值大于1E22atoms/cm3。
18.如权利要求12所述的制作应变硅晶体管的方法，其中该第一氢原子浓度是在1E22至1E24atoms/cm3之间。
19.如权利要求12所述的制作应变硅晶体管的方法，其中该第二氢原子浓度是在1E18至5E22atoms/cm3之间。
20.如权利要求12所述的制作应变硅晶体管的方法，其中该过渡氮化硅膜的硅-氢键/氮-氢键比例约为1.0。
21.如权利要求12所述的制作应变硅晶体管的方法，其中该超高伸张应力氮化硅膜的硅-氢键/氮-氢键比例约为0.3。
22.如权利要求12所述的制作应变硅晶体管的方法，其中该超高伸张应力氮化硅膜的伸张应力值大于或等于1.5GPa。
23.一种金属氧化物半导体晶体管元件，包括：
一半导体衬底；
一栅极结构，设于该半导体衬底上；
一漏极/源极区域，设于该栅极结构两侧的该半导体衬底中；
一超高伸张应力氮化硅膜，覆盖在该栅极结构以及该漏极/源极区域上方，其中该超高伸张应力氮化硅膜的伸张应力值大于或等于1.5GPa；以及
一层间介电膜，设于该超高伸张应力氮化硅膜的上方。
24.如权利要求23所述的金属氧化物半导体晶体管元件，其中该栅极结构包括一栅极电极层以及一介于该栅极电极层与该半导体衬底之间的一栅极氧化层。
25.如权利要求23所述的金属氧化物半导体晶体管元件，其中该金属氧化物半导体晶体管元件还包括一硅化金属层，设于该栅极结构上以及该漏极/源极区域上。
26.一种金属氧化物半导体晶体管元件，包括：
一半导体衬底；
一栅极结构，设于该半导体衬底上；
一漏极/源极区域，设于该栅极结构两侧的该半导体衬底中；
一超高伸张应力氮化硅膜，覆盖在该栅极结构以及该漏极/源极区域上方，其中该超高伸张应力氮化硅膜的氢原子浓度小于1E22atoms/cm3；以及
一层间介电膜，设于该超高伸张应力氮化硅膜的上方。
27.如权利要求26所述的金属氧化物半导体晶体管元件，其中该栅极结构包括一栅极电极层以及一介于该栅极电极层与该半导体衬底之间的一栅极氧化层。
28.如权利要求26所述的金属氧化物半导体晶体管元件，其中该金属氧化物半导体晶体管元件还包括一硅化金属层，设于该栅极结构上以及该漏极/源极区域上。
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