WO2019109924A1 - Ldmos器件及其制备方法 - Google Patents

Ldmos器件及其制备方法 Download PDF

Info

Publication number
WO2019109924A1
WO2019109924A1 PCT/CN2018/119252 CN2018119252W WO2019109924A1 WO 2019109924 A1 WO2019109924 A1 WO 2019109924A1 CN 2018119252 W CN2018119252 W CN 2018119252W WO 2019109924 A1 WO2019109924 A1 WO 2019109924A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
trench
conductivity type
buried layer
doped region
Prior art date
Application number
PCT/CN2018/119252
Other languages
English (en)
French (fr)
Inventor
何乃龙
张森
张广胜
兰云
Original Assignee
无锡华润上华科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华科技有限公司 filed Critical 无锡华润上华科技有限公司
Priority to KR1020207016356A priority Critical patent/KR102333100B1/ko
Priority to US16/770,362 priority patent/US11309406B2/en
Priority to JP2020530563A priority patent/JP7079328B2/ja
Publication of WO2019109924A1 publication Critical patent/WO2019109924A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Definitions

  • the present invention relates to the field of LDMOS (Laterally Diffused Metal Oxide Semiconductor) technology, and in particular, to an LDMOS device and a method for fabricating the same.
  • LDMOS Laser Diffused Metal Oxide Semiconductor
  • the current LDMOS devices typically have a double resurf (double-reduced surface electric field) LDMOS device.
  • the double-reduced surface electric field LDMOS device reduces the double reduction by combining the polysilicon gate field/metal field plate with the P-doped region on the surface of the drift region.
  • Surface electric field LDMOS device surface electric field, resulting in high source-drain breakdown voltage (abbreviated as BV) and low on-resistance, but the current channel through the JFET region (PN junction field effect transistor region), JFET region size and doping
  • BV high source-drain breakdown voltage
  • JFET region PN junction field effect transistor region
  • the concentration limits the on-resistance of the LDMOS device.
  • the larger the JFET region size and the doping concentration the larger the on-resistance of the LDMOS device.
  • an LDMOS device and a method of fabricating the same are provided.
  • a method of preparing an LDMOS device comprising:
  • a source doping region is formed in the well region; the first conductivity type and the second conductivity type are opposite conductivity types.
  • An LDMOS device comprising: a substrate;
  • a first conductivity type doping region disposed on the substrate for use as a drift region
  • a source doped region disposed in the well region
  • a buried layer having a second conductivity type disposed in the first conductivity type doping region, one end extending to the trench;
  • the field oxide insulating layer structure is disposed above the top buried layer and has one end extending to the trench; the first conductive type and the second conductive type are opposite conductive types.
  • the bottom of the trench is lower than the bottom of the buried layer.
  • FIG. 1 is a schematic structural view of an LDMOS device in an embodiment
  • FIG. 2 is a schematic structural view of an LDMOS device in another embodiment
  • FIG. 3 is a flow chart showing a method of fabricating an LDMOS device in one embodiment.
  • FIG. 4 is a schematic structural view of an LDMOS device in a process of fabricating an LDMOS device in an embodiment
  • FIG. 5 is a schematic structural view of an LDMOS device in a process of fabricating an LDMOS device in another embodiment
  • Fig. 6 is a view showing the configuration of an LDMOS device in the process of fabricating an LDMOS device in still another embodiment.
  • the LDMOS device includes a substrate 10, a first conductive type doped region 11, a trench 12, a well region 13, a source doped region 14, a buried layer 15, and a field oxide insulating layer. Structure 16.
  • the first conductive type doped region 11 is disposed on the substrate 10 for use as a drift region
  • the trench 12 is formed on the first conductive type doped region 11, and the well region 13 is disposed under the trench 12, wherein the well region 13 Having a second conductivity type, the source doping region 14 is disposed in the well region 13, the buried layer 15 is disposed in the first conductivity type doping region 11, that is, in the drift region, and one end of the buried layer 15 extends to the trench
  • the trench 12, the buried layer 15 has a second conductivity type, the field oxide insulating layer structure 16, disposed above the buried layer 15, one end extending to the trench, the first conductivity type and the second conductivity type being opposite conductivity types.
  • the source doping region 14 may include a first conductivity type source doping region 141 and a second conductivity type source doping region 142 .
  • the first conductivity type and the second conductivity type are P-type and the other is N-type
  • the source doping region 14 includes a P-type source doping region and an N-type source doping region.
  • the first conductivity type is N-type
  • the second conductivity type corresponds to P-type
  • the substrate 10 is a P-type substrate
  • the drift region is an N-type drift region, and specifically may be an N-type drift region (N The -type represents a lightly doped concentration of N-type)
  • the well region 13 is a P-well
  • the buried layer 15 is a P-type buried layer.
  • the first conductivity type may also be a P type
  • the second conductivity type second conductivity type corresponds to an N type.
  • the substrate 10 is an N type substrate
  • the drift region is a P type drift region
  • the well region 13 is N.
  • the well, buried layer 15 is an N-type buried layer. .
  • the bottom of the trench 12 is lower than the bottom of the buried layer 15, such that the trench 12 is deeper than the buried layer 15, and the trench 12 can be further deeper than the PN formed by the buried layer 15 and the drift region. Knot.
  • a portion of the field oxide insulating layer structure 16 is disposed above the first conductive type doped region 11 , and the remaining field oxide insulating layer structure 16 is disposed above the buried layer 15 .
  • the LDMOS device further includes a gate oxide structure 17, a gate polysilicon 18 (strip structure in FIG. 2), and a gate terminal 19.
  • a gate oxide structure 17 is provided at the bottom of the trench 12, in the trench 12 near the sidewall of the buried layer 15, and the gate oxide structure 17 further extends to the portion of the field oxide insulating layer structure 16.
  • the gate oxide structure 17 covers a portion of the bottom of the trench 12, a side of the trench 12 adjacent to the buried layer 15, and a portion of the surface of the field oxide insulating layer structure 16.
  • the gate polysilicon 18 is disposed on the gate oxide structure 17, and the gate terminal 19 is electrically connected to the gate polysilicon 18.
  • the gate oxide structure 17 may also be disposed at the bottom of the trench 12 and the sidewall of the trench 12 adjacent to the buried layer 15.
  • the gate oxide structure 17 may not extend toward the surface of the field oxide insulating layer structure, and the gate oxide structure may be 17 covers a portion of the bottom of the trench 12 and a portion of the surface of the buried layer 15.
  • the LDMOS device further includes a source terminal 20, and the source terminal 20 is electrically connected to the first conductivity type source doping region 141 and the second conductivity type source doping region 142, respectively. connection.
  • the LDMOS device further includes a drain doping region 21 and a drain terminal 22, and the drain doping region 20 is disposed on the first conductive type doping region 11, and the drain doping is performed.
  • the region 21 and the source doping region 14 are separated by a field oxide insulating layer structure, the drain doping region 21 has a first conductivity type, and the drain terminal 22 is electrically connected to the drain doping region 21.
  • the above LDMOS device has a trench 12 and a well region 13 is disposed under the trench 12 such that the position of the well region 13 is adjusted downward, and since the buried layer 15 and the field oxide insulating layer structure 16 extend to the trench 12 Therefore, there is no first conductive type doped region between the buried layer 15 and the field oxide insulating layer structure 16, between the buried layer 15, the field oxide insulating layer structure 16 and the trench 12, so that the conductive channel does not pass In the JEFT region, the on-resistance of the LDMOS is able to get rid of the limitation of the JFET region, and can obtain a high on-off breakdown voltage while achieving a lower on-resistance.
  • the LDMOS device shown in FIG. 1 can be prepared by the method for preparing the LDMOS device in one embodiment.
  • the method for fabricating the LDMOS device can include the following steps:
  • a first conductive type doped region is formed on a substrate 10, a substrate 10 has a second conductivity type, and then a first conductive type doped region 11 is formed on the substrate 10 as a drift region, and then A buried layer 15 is formed in the drift region, and then a field oxide insulating layer structure 16 is formed on the buried layer 15, the substrate has a second conductivity type, and the wafer may have a structure as shown in FIG.
  • the implementation step of step S11 includes the steps of first forming a buried layer 15 in the first conductive type doped region 11, and then forming a field oxide on the buried layer 15.
  • the insulating layer structure 16 partially covers the buried layer 15.
  • the buried layer 15 is exposed below the field oxide insulating layer structure 16 near the subsequent trench.
  • a field oxide insulating layer structure 16 is formed on the buried layer 15 and the drift region, and the buried layer 15 encloses a bottom region of the field oxide insulating layer structure close to the source doped region (as shown in FIG. 4 left field oxidation oxide structure bottom area).
  • the step of forming the trench 12 on the first conductive type doped region 11 is to open the trench 12 at a position lower than the bottom of the buried layer, so that the first conductive
  • the bottom of the trench 12 formed on the type doped region 11 is lower than the bottom of the buried layer 15.
  • the bottom of the trench 12 formed may be further lower than the PN junction formed by the buried layer 15 and the drift region.
  • the step of forming a trench on the first conductive type doped region is performed by etching the field oxide insulating layer structure as a hard mask.
  • the drift region has field oxide insulating layer structures A and B, and the field oxide insulating layer structure A and the field oxide insulating layer structure B are arranged in a left-to-right direction (current direction), which is in this field.
  • a trench is formed on the drift region in the middle of the oxide insulating layer structure, and the field oxide insulating layer structure is used to separate the source doped region and the drain doped region, so the drift region on the left side of the field oxide insulating layer structure A and the field oxide insulating layer The drift region on the right side of structure B is used to form the drain doped region, and no trench is formed.
  • This step is to form a well region by ion implantation on the trench 12 in the structure of FIG. 5, as shown in FIG.
  • S14 forming a source doping region in the well region, as shown in FIG. 1 is a structure after forming a source doping region; the first conductivity type and the second conductivity type are opposite conductivity types.
  • the first conductivity type may be an N type, and the second conductivity type second conductivity type corresponds to a P type.
  • the step of forming a source doped region in the well region is to form a first conductive type source doped region and a second conductive type source doped region in the well region.
  • the first conductivity type source doping region is located closer to the buried layer.
  • the source terminal is led out on the source doped region of the first conductivity type and the source doped region of the second conductivity type.
  • the first conductive type source doped region may be an N-type source doped region, and correspondingly, the second conductive type source doped region is a P-type doped region.
  • the step after trenching is formed on the first conductive type doped region includes a step of forming the gate oxide structure 17, specifically in the bottom of the trench 12 and in the trench 12
  • the sidewall of the buried layer 15 forms a continuous gate oxide structure
  • the gate oxide structure 17 is formed to cover a portion of the bottom of the trench 12 and a portion of the surface of the buried layer 15.
  • the gate oxide structure 17 may further extend onto a portion of the surface of the field oxide insulating layer structure 16.
  • the gate oxide structure 17 is formed to cover a portion of the bottom of the trench 12, a sidewall of the trench 12 adjacent to the buried layer 15, and a portion of the surface of the field oxide insulating layer structure 16.
  • the sidewall of the trench 12 adjacent to the buried layer 15 is a trench right sidewall extending to the buried layer 15 and the field oxide insulating layer structure 16.
  • the current direction is from left to right. right.
  • gate polysilicon 18 is deposited over the gate oxide structure 17, and then the gate terminal 19 is led out at the gate polysilicon 18.
  • the step of forming the gate oxide structure 17 and the gate polysilicon 18 in this embodiment may be performed after the trench 12 is opened. Specifically, it may be performed after forming the well region and the source doping region.
  • the method for fabricating an LDMOS device further includes the steps of: forming a drain doping region 20 in the first conductivity type doping 11, and then drawing a drain terminal in the drain doping region 20. .
  • the drain doping region 20 and the source doping region 14 are separated by a field oxide insulating layer structure 16 having a first conductivity type; the current flowing from the source doping region of the first conductivity type into the drain Very doped area.
  • the position of the well region is adjusted downward (formed under the trench), and the buried layer and the field oxide insulating layer structure are formed because the buried layer and the field oxide insulating layer structure extend to the trench.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种LDMOS器件的制备方法，包括获取形成有第一导电类型掺杂区、且在第一导电类型掺杂区内形成有顶埋层、在顶埋层上形成有场氧化绝缘层结构的晶圆；在第一导电类型掺杂区上开设沟槽，沟槽延伸至顶埋层和场氧化绝缘层结构，从而将顶埋层去除掉一部分；注入第二导电类型离子、在沟槽下方形成阱区；在阱区内形成源极掺杂区；第一导电类型和第二导电类型为相反的导电类型。

Description

LDMOS器件及其制备方法 技术领域
本发明涉及LDMOS(Laterally Diffused Metal Oxide Semiconductor，横向扩散金属氧化物半导体)技术领域，尤其涉及一种LDMOS器件及其制备方法。
背景技术
目前的LDMOS器件，典型的有double resurf(双重降低表面电场)LDMOS器件，双重降低表面电场LDMOS器件是通过多晶硅栅极场板/金属场板结合漂移区表面的P型掺杂区来降低双重降低表面电场LDMOS器件的表面电场，从而得到高源漏击穿电压(简称BV)和低导通电阻，但是电流通道要经过JFET区域(PN结型场效应晶体管区域)，JFET区域的大小以及掺杂浓度会限制LDMOS器件的导通电阻，JFET区域的大小以及掺杂浓度越大，LDMOS器件的导通电阻越大，然而要保证较高的源漏击穿电压，就需要牺牲一定的导通电阻。
发明内容
基于此，提供一种LDMOS器件及其制备方法。
一种LDMOS器件的制备方法，包括：
获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆；
在所述第一导电类型掺杂区上开设沟槽，所述沟槽延伸至所述顶埋层和场氧化绝缘层结构，从而将所述顶埋层去除掉一部分；
注入第二导电类型离子、在所述沟槽下方形成阱区；
在所述阱区内形成源极掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
一种LDMOS器件，包括：衬底；
第一导电类型掺杂区，设于所述衬底上，用于作为漂移区；
沟槽，开设于所述第一导电类型掺杂区上；
阱区，具有第二导电类型，设于所述沟槽下方；
源极掺杂区，设于所述阱区内；
顶埋层，具有第二导电类型，设于所述第一导电类型掺杂区内，一端延伸至所述沟槽；以及
场氧化绝缘层结构，设于所述顶埋层上方，一端延伸至所述沟槽；所述第一导电类型和第二导电类型为相反的导电类型。
所述沟槽的底部低于所述顶埋层的底部。
本发明的一个或多个实施例的细节在下面的附图和描述中提出。本发明的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1为一个实施例中的LDMOS器件的结构示意图；
图2为另一个实施例中的LDMOS器件的结构示意图；
图3为一个实施例中的LDMOS器件的制备方法的流程示意图。
图4为一个实施例中的LDMOS器件的制备过程的LDMOS器件的结构示意图；
图5为另一个实施例中的LDMOS器件的制备过程的LDMOS器件的结构示意图；
图6为再一个实施例中的LDMOS器件的制备过程的LDMOS器件的结 构示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。
一个实施例中，请参阅图1，LDMOS器件包括衬底10、第一导电类型掺杂区11、沟槽12、阱区13、源极掺杂区14、顶埋层15以及场氧化绝缘层结构16。第一导电类型掺杂区11设于衬底10上，用于作为漂移区，沟槽12开设于第一导电类型掺杂区11上，阱区13设于沟槽12下方，其中阱区13具有第二导电类型，源极掺杂区14设于阱区13内，顶埋层15设于第一导电类型掺杂区11内，即漂移区内，且顶埋层15的一端延伸至沟槽12，顶埋层15具有第二导电类型，场氧化绝缘层结构16，设于顶埋层15上方，一端延伸至沟槽，第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，请参阅图1，源极掺杂区14可包括第一导电类型源极掺杂区141以及第二导电类型源极掺杂区142。其中，第一导电类型和 第二导电类型一个为P型，另一个为N型，源极掺杂区14则包括P型源极掺杂区和N型源极掺杂区。
例如，第一导电类型为N型，第二导电类型对应为P型，那么，相应地，衬底10是P型衬底，漂移区是N型漂移区具体可以是N-型漂移区(N-型代表轻掺杂浓度的N型)，阱区13是P阱，顶埋层15是P型顶埋层。第一导电类型也可为P型，第二导电类型第二导电类型对应为N型，那么，相应地，衬底10是N型衬底，漂移区是P型漂移区，阱区13是N阱，顶埋层15是N型顶埋层。。
在其中一个实施例中，沟槽12的底部低于顶埋层15的底部，使得沟槽12深于顶埋层15，沟槽12还可以进一步深于顶埋层15与漂移区形成的PN结。
在其中一个实施例中，请参阅图1，部分场氧化绝缘层结构16设于第一导电类型掺杂区11的上方，其余的场氧化绝缘层结构16设于顶埋层15上方。
在其中一个实施例中，请参阅图2，LDMOS器件还包括栅氧结构17、栅极多晶硅18(图2中条纹结构)以及栅极引出端19。在图2所示的实施例中，栅氧结构17设于沟槽12的底部、沟槽12中靠近顶埋层15的侧壁，栅氧结构17还进一步延伸至场氧化绝缘层结构16部分表面上。具体地，如图2所示，栅氧结构17覆盖沟槽12的部分底部、沟槽12中靠近顶埋层15的侧面以及场氧化绝缘层结构16的部分表面。栅极多晶硅18设于栅氧结构17上，栅极引出端19与栅极多晶硅18电连接。在其他实施例中，栅氧结构17也可以设于沟槽12的底部和沟槽12中靠近顶埋层15的侧壁，栅氧结构17可不向场氧化绝缘层结构表面延伸，栅氧结构17覆盖沟槽12的部分底部以及顶埋层15的部分表面。
在一个实施例中，请参阅图2，LDMOS器件还包括源极引出端20，源极引出端20分别与第一导电类型源极掺杂区141、第二导电类型源极掺杂区142电连接。
在一个实施例中，请参阅图2，LDMOS器件还包括漏极掺杂区21以及 漏极引出端22，漏极掺杂区20设于第一导电类型掺杂区11上，漏极掺杂区21和源极掺杂区14被场氧化绝缘层结构隔开，漏极掺杂区21具有第一导电类型，漏极引出端22与漏极掺杂区21电连接。
上述LDMOS器件，通过开设沟槽12，并将阱区13设于沟槽12下方，使得阱区13的位置向下调整，且由于顶埋层15和场氧化绝缘层结构16延伸至沟槽12，使得顶埋层15和场氧化绝缘层结构16之间，顶埋层15、场氧化绝缘层结构16和沟槽12之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的导通电阻的大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压同时得到更低的导通电阻。
还提出了一种制备LDMOS器件的制备方法。
一个实施例中的LDMOS器件的制备方法可制备出如图1所示的LDMOS器件，请参阅图3，该LDMOS器件的制备方法可包括以下步骤：
S11：获取形成有第一导电类型掺杂区11、且在第一导电类型掺杂区11内形成有顶埋层15、在顶埋层15上形成有场氧化绝缘层结构16的晶圆。
如图4所示，第一导电类型掺杂区是在衬底10上形成，衬底10具有第二导电类型，然后在衬底10上形成第一导电类型掺杂区11作为漂移区，然后在漂移区内形成顶埋层15，然后在顶埋层15上形成有场氧化绝缘层结构16，衬底具有第二导电类型，晶圆则可是如图4所示的结构。
在一个实施例中，如图4所示，步骤S11的实现步骤包括以下步骤：首先在所述第一导电类型掺杂区11内形成顶埋层15，然后在顶埋层15上形成场氧化绝缘层结构16，将顶埋层15部分覆盖，顶埋层15在靠近后续开设沟槽的位置处有一截从场氧化绝缘层结构16下方露出。如图4所示，本实施例是在顶埋层15和漂移区上形成场氧化绝缘层结构16，顶埋层15包住靠近源极掺杂区的场氧化绝缘层结构底部区域(如图4靠左的场氧化绝缘层结构底部区域)。
S12：在第一导电类型掺杂区上开设沟槽，沟槽延伸至顶埋层和场氧化绝 缘层结构从而将顶埋层去除掉一部分。
如图5椭圆圈中所示，顶埋层和场氧化绝缘层结构之间、顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，因此导电沟道不会经过JEFT区域。
在其中一个实施例中，如图5所示，在第一导电类型掺杂区11上开设沟槽12的步骤是在低于顶埋层的底部的位置开设沟槽12，使得在第一导电类型掺杂区11上形成的沟槽12的底部低于顶埋层15的底部。其他实施例中，形成的沟槽12底部还可以进一步低于顶埋层15与漂移区形成的PN结。
在其中一个实施例中，在第一导电类型掺杂区上开设沟槽的步骤，是以场氧化绝缘层结构为硬掩膜进行刻蚀。例如，如图5所示，漂移区上有场氧化绝缘层结构A和B，场氧化绝缘层结构A和场氧化绝缘层结构B按照从左往右方向(电流方向)排列，是在这个场氧化绝缘层结构中间的漂移区上形成沟槽，场氧化绝缘层结构用来隔开源极掺杂区和漏极掺杂区，故场氧化绝缘层结构A左边的漂移区和场氧化绝缘层结构B右边的漂移区是用于形成漏极掺杂区的，不会开设沟槽。
S13：注入第二导电类型离子、在沟槽12下方形成阱区。
本步骤是在图5的结构中的沟槽12上，以离子注入方式形成阱区，如图1所示是形成阱区后的结构。
S14：在阱区内形成源极掺杂区，如图1所示是形成源极掺杂区后的结构；第一导电类型和第二导电类型为相反的导电类型。其中，第一导电类型可为N型，第二导电类型第二导电类型对应为P型。
在其中一个实施例中，请参阅图1，在阱区内形成源极掺杂区的步骤是在阱区内形成第一导电类型源极掺杂区和第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离顶埋层更近。在所述阱区内形成源极掺杂区的步骤之后，在第一导电类型的源极掺杂区和第二导电类型源极掺杂区上引出源极引出端。第一导电类型源极掺杂区可为N型源极掺杂区，对应地，第二导电类型源极掺杂区为P型掺杂区。
在其中一个实施例中，请参阅图6，在第一导电类型掺杂区上开设沟槽之后的步骤包括栅氧结构17的形成步骤，具体是在沟槽12的底部和沟槽12中靠近顶埋层15的侧壁形成连续的栅氧结构，形成的栅氧结构17覆盖沟槽12部分底部以及顶埋层15的部分表面。在其他实施例中，请参阅图6，栅氧结构17还可以进一步延伸至场氧化绝缘层结构16的部分表面上。形成的栅氧结构17覆盖沟槽12部分底部、沟槽12中靠近顶埋层15的侧壁以及场氧化绝缘层结构16的部分表面。例如，如图6所示，该沟槽12中靠近顶埋层15的侧壁是延伸至顶埋层15和场氧化绝缘层结构16的沟槽右侧壁，图中电流方向为从左往右。
形成栅氧结构17之后，在栅氧结构17上淀积形成栅极多晶硅18，然后在栅极多晶硅18引出栅极引出端19。
本实施例形成栅氧结构17以及栅极多晶硅18的步骤可以在开设沟槽12之后执行。具体可以在形成阱区、源极掺杂区之后执行。
一个实施例中，请参阅图6，LDMOS器件的制备方法还包括以下步骤：在第一导电类型掺杂11内形成漏极掺杂区20，然后在漏极掺杂区20引出漏极引出端。漏极掺杂区20和源极掺杂区14被场氧化绝缘层结构16隔开，漏极掺杂区20具有第一导电类型；电流是从第一导电类型的源极掺杂区流入漏极掺杂区的。
上述LDMOS器件的制备方法，将阱区的位置向下调整(形成于沟槽下方)，且由于顶埋层和场氧化绝缘层结构延伸至沟槽，使得顶埋层和场氧化绝缘层结构之间，顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的导通电阻的大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压同时得到更低的导通电阻。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能组合都进行描述，然而只要这些技 术特征的组合不存在矛盾，都应当是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施例，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种LDMOS器件的制备方法，包括：
    获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆；
    在所述第一导电类型掺杂区上开设沟槽，所述沟槽延伸至所述顶埋层和场氧化绝缘层结构，从而将所述顶埋层去除掉一部分；
    注入第二导电类型离子、在所述沟槽下方形成阱区；以及
    在所述阱区内形成源极掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
  2. 根据权利要求1所述的方法，其特征在于，所述在所述第一导电类型掺杂区上开设沟槽的步骤，是以所述场氧化绝缘层结构为硬掩膜进行刻蚀。
  3. 根据权利要求1所述的方法，其特征在于，所述在所述第一导电类型掺杂区上开设沟槽的步骤，形成的沟槽底部低于所述顶埋层的底部。
  4. 根据权利要求1所述的方法，其特征在于，所述在所述第一导电类型掺杂区上开设沟槽的步骤，形成的沟槽底部低于所述顶埋层与所述第一导电类型掺杂区形成的PN结。
  5. 根据权利要求1所述的方法，其特征在于，所述获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆的步骤包括：
    在所述第一导电类型掺杂区内形成所述顶埋层；
    在所述顶埋层上形成所述场氧化绝缘层结构，将所述顶埋层部分覆盖，所述顶埋层在靠近所述沟槽的位置处有一截从所述场氧化绝缘层结构下方露出。
  6. 根据权利要求1所述的方法，其特征在于，所述第一导电类型是N型，所述第二导电类型是P型。
  7. 根据权利要求1所述的方法，其特征在于，在第一导电类型掺杂区上 开设沟槽之后的步骤包括：在所述沟槽的底部和所述沟槽中靠近顶埋层的侧壁形成连续的栅氧结构。
  8. 根据权利要求7所述的方法，其特征在于，所述栅氧结构还延伸至所述场氧化绝缘层结构的部分表面。
  9. 根据权利要求1所述的方法，其特征在于，所述在阱区内形成源极掺杂区的步骤是在所述阱区内形成第一导电类型源极掺杂区和第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离所述顶埋层更近。
  10. 根据权利要求9所述的方法，其特征在于，还包括：
    在所述第一导电类型掺杂内形成漏极掺杂区，所述漏极掺杂区和所述源极掺杂区被所述场氧化绝缘层结构隔开，所述漏极掺杂区具备第一导电类型。
  11. 一种LDMOS器件，包括：
    衬底；
    第一导电类型掺杂区，设于所述衬底上，用于作为漂移区；
    沟槽，开设于所述第一导电类型掺杂区上；
    阱区，具有第二导电类型，设于所述沟槽下方；
    源极掺杂区，设于所述阱区内；
    顶埋层，具有第二导电类型，设于所述第一导电类型掺杂区内，一端延伸至所述沟槽；
    场氧化绝缘层结构，设于所述顶埋层上方，一端延伸至所述沟槽；以及
    所述第一导电类型和第二导电类型为相反的导电类型。
  12. 根据权利要求11所述的LDMOS器件，其特征在于，其特征在于，所述沟槽的底部低于所述顶埋层的底部。
  13. 根据权利要求11所述的LDMOS器件，其特征在于，所述沟槽的底部低于顶所述埋层与漂移区形成的PN结。
  14. 根据权利要求11所述的LDMOS器件，其特征在于，还包括：
    栅氧结构，设于所述沟槽的底部和所述沟槽中靠近所述顶埋层的侧壁；所述栅氧结构覆盖沟槽的部分底部以及所述顶埋层的部分表面；
    栅极多晶硅，设于所述栅氧结构上；以及
    栅极引出端，与所述栅极多晶硅电连接。
  15. 根据权利要求14所述的LDMOS器件，其特征在于，所述栅氧结构还延伸至所述场氧化绝缘层结构的部分表面。
  16. 根据权利要求11所述的LDMOS器件，其特征在于，所述源极掺杂区包括第一导电类型源极掺杂区；
    第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离顶埋层更近；以及源极引出端，分别与所述第一导电类型源极掺杂区、第二导电类型源极掺杂区电连接。
  17. 根据权利要求16所述的LDMOS器件，其特征在于，还包括：
    漏极掺杂区，设于所述第一导电类型掺杂区上，所述漏极掺杂区和所述源极掺杂区被所述场氧化绝缘层结构隔开，所述漏极掺杂区具有第一导电类型；以及
    漏极引出端，与所述漏极掺杂区电连接。
  18. 根据权利要求11所述的LDMOS器件，其特征在于，部分所述场氧化绝缘层结构设于所述第一导电类型掺杂区的上方。
PCT/CN2018/119252 2017-12-06 2018-12-05 Ldmos器件及其制备方法 WO2019109924A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020207016356A KR102333100B1 (ko) 2017-12-06 2018-12-05 Ldmos 소자 및 그 제조 방법
US16/770,362 US11309406B2 (en) 2017-12-06 2018-12-05 Method of manufacturing an LDMOS device having a well region below a groove
JP2020530563A JP7079328B2 (ja) 2017-12-06 2018-12-05 Ｌｄｍｏｓデバイスの製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711278066.7A CN109888015A (zh) 2017-12-06 2017-12-06 Ldmos器件及其制备方法
CN201711278066.7 2017-12-06

Publications (1)

Publication Number Publication Date
WO2019109924A1 true WO2019109924A1 (zh) 2019-06-13

Family

ID=66751267

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/119252 WO2019109924A1 (zh) 2017-12-06 2018-12-05 Ldmos器件及其制备方法

Country Status (5)

Country Link
US (1) US11309406B2 (zh)
JP (1) JP7079328B2 (zh)
KR (1) KR102333100B1 (zh)
CN (1) CN109888015A (zh)
WO (1) WO2019109924A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244178B (zh) * 2020-01-15 2020-10-16 合肥晶合集成电路有限公司 扩散型场效应晶体管的形成方法
CN113903791A (zh) * 2021-12-09 2022-01-07 广州粤芯半导体技术有限公司 半导体器件及其制备方法
CN115132822A (zh) * 2022-05-19 2022-09-30 深圳基本半导体有限公司 一种ldmos器件及其制作方法和应用
CN115274858B (zh) * 2022-09-30 2023-01-17 北京芯可鉴科技有限公司 Ldmos器件、ldmos器件制造方法及芯片

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5777365A (en) * 1995-09-28 1998-07-07 Nippondenso Co., Ltd. Semiconductor device having a silicon-on-insulator structure
CN102468335A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
CN105428415A (zh) * 2015-11-16 2016-03-23 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3423230B2 (ja) 1998-11-26 2003-07-07 三洋電機株式会社 半導体装置の製造方法
KR100871550B1 (ko) * 2006-12-20 2008-12-01 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조방법
US7709908B2 (en) * 2007-08-10 2010-05-04 United Microelectronics Corp. High-voltage MOS transistor device
US7956412B2 (en) * 2007-12-04 2011-06-07 International Business Machines Corporation Lateral diffusion field effect transistor with a trench field plate
KR100947941B1 (ko) 2007-12-27 2010-03-15 주식회사 동부하이텍 반도체 소자 및 그 제조방법
US20110241114A1 (en) * 2010-04-02 2011-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage mos transistor
US8921937B2 (en) * 2011-08-24 2014-12-30 United Microelectronics Corp. High voltage metal-oxide-semiconductor transistor device and method of fabricating the same
US9171916B1 (en) * 2011-10-13 2015-10-27 Maxim Integrated Products, Inc. LDMOS with thick interlayer-dielectric layer
KR101755718B1 (ko) * 2011-11-22 2017-07-07 현대자동차주식회사 수평형 디모스 소자 및 그 제조 방법
DE102011087845B4 (de) * 2011-12-06 2015-07-02 Infineon Technologies Ag Laterales transistorbauelement und verfahren zu dessen herstellung
US9064894B2 (en) * 2012-08-08 2015-06-23 Globalfoundries Singapore Pte. Ltd. Stress enhanced high voltage device
US8912066B2 (en) * 2013-03-15 2014-12-16 Globalfoundries Singapore Pte. Ltd. Lateral double-diffused high voltage device
US9130033B2 (en) * 2013-12-03 2015-09-08 Vanguard International Semiconductor Corporation Semiconductor device and method for fabricating the same
US9318366B2 (en) 2014-01-06 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit having modified isolation structure
JP6339404B2 (ja) 2014-04-10 2018-06-06 旭化成エレクトロニクス株式会社 半導体装置の製造方法及び半導体装置
US9245952B2 (en) * 2014-05-12 2016-01-26 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor
JP2017073410A (ja) 2015-10-05 2017-04-13 株式会社日立製作所 半導体装置および半導体装置の製造方法
US9698260B1 (en) * 2015-12-31 2017-07-04 Globalfoundries Singapore Pte. Ltd. High voltage device with low Rdson
US10475784B2 (en) * 2017-05-30 2019-11-12 Vanguard International Semiconductor Corporation Semiconductor structure with a resistor and a transistor and method for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5378912A (en) * 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5777365A (en) * 1995-09-28 1998-07-07 Nippondenso Co., Ltd. Semiconductor device having a silicon-on-insulator structure
CN102468335A (zh) * 2010-11-19 2012-05-23 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
CN105428415A (zh) * 2015-11-16 2016-03-23 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法

Also Published As

Publication number Publication date
US11309406B2 (en) 2022-04-19
CN109888015A (zh) 2019-06-14
JP7079328B2 (ja) 2022-06-01
KR20200079318A (ko) 2020-07-02
KR102333100B1 (ko) 2021-12-02
JP2021506118A (ja) 2021-02-18
US20210175347A1 (en) 2021-06-10

Similar Documents

Publication Publication Date Title
TWI575718B (zh) 利用深擴散區在單片功率積體電路中製備jfet和ldmos電晶體
TWI524522B (zh) 帶有累積增益植入物之橫向雙擴散金屬氧化物半導體及其製造方法
US9117850B2 (en) Method and system for a gallium nitride vertical JFET with self-aligned source and gate
WO2019109924A1 (zh) Ldmos器件及其制备方法
WO2014196164A1 (ja) 炭化珪素半導体装置およびその製造方法
US9698248B2 (en) Power MOS transistor and manufacturing method therefor
JP2014135494A (ja) 二重並列チャネル構造を持つ半導体素子及びその半導体素子の製造方法
US9853099B1 (en) Double diffused metal oxide semiconductor device and manufacturing method thereof
US9614031B2 (en) Methods for forming a high-voltage super junction by trench and epitaxial doping
US20150340428A1 (en) Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
US20160172436A1 (en) Semiconductor device, termination structure and method of forming the same
JP4645705B2 (ja) 半導体装置及び半導体装置の製造方法
KR101964153B1 (ko) 절연 또는 반절연 ＳｉＣ 기판에 구현된 ＳｉＣ 반도체 소자 및 그 제조 방법
CN105140289A (zh) N型ldmos器件及工艺方法
JP2011124325A (ja) 半導体装置、及びその製造方法
CN105990434A (zh) 半导体装置及其制造方法
US20140183663A1 (en) Raised Source/Drain MOS Transistor and Method of Forming the Transistor with an Implant Spacer and an Epitaxial Spacer
CN109888010A (zh) 具有P型屏蔽层的AlGaN/GaN异质结垂直型场效应晶体管及其制作方法
US9780171B2 (en) Fabricating method of lateral-diffused metal oxide semiconductor device
US9728599B1 (en) Semiconductor device
JP2019165166A (ja) 炭化珪素半導体装置およびその製造方法
KR101262853B1 (ko) 반도체 소자 및 그 제조 방법
KR20110037030A (ko) 반도체 소자 및 그 제조 방법
JP6757678B2 (ja) 半導体装置及び半導体装置の製造方法
WO2020095412A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18887072

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020530563

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20207016356

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18887072

Country of ref document: EP

Kind code of ref document: A1