CN109888015A - Ldmos器件及其制备方法 - Google Patents

Ldmos器件及其制备方法 Download PDF

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CN109888015A
CN109888015A CN201711278066.7A CN201711278066A CN109888015A CN 109888015 A CN109888015 A CN 109888015A CN 201711278066 A CN201711278066 A CN 201711278066A CN 109888015 A CN109888015 A CN 109888015A
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conduction type
buried layer
region
groove
field oxide
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何乃龙
张森
张广胜
兰云
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CSMC Technologies Corp
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CSMC Technologies Corp
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Priority to CN201711278066.7A priority Critical patent/CN109888015A/zh
Priority to US16/770,362 priority patent/US11309406B2/en
Priority to PCT/CN2018/119252 priority patent/WO2019109924A1/zh
Priority to KR1020207016356A priority patent/KR102333100B1/ko
Priority to JP2020530563A priority patent/JP7079328B2/ja
Publication of CN109888015A publication Critical patent/CN109888015A/zh
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Abstract

本发明提供一种LDMOS器件及其制备方法，获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆；在所述第一导电类型掺杂区上开设沟槽，所述沟槽延伸至所述顶埋层和场氧化绝缘层结构从而将所述顶埋层去除掉一部分；注入第二导电类型离子、在所述沟槽下方形成阱区；在所述阱区内形成源极掺杂区；所述第一导电类型和第二导电类型为相反的导电类型，将阱区的位置向下调整，且由于顶埋层和场氧化绝缘层结构之间、顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，能够在获得高的源漏击穿电压同时得到更低的导通电阻。

Description

LDMOS器件及其制备方法
技术领域
本发明涉及LDMOS(Laterally Diffused Metal Oxide Semiconductor，横向扩散金属氧化物半导体)技术领域，尤其涉及一种LDMOS器件及其制备方法。
背景技术
目前的LDMOS器件，典型的有double resurf(双重降低表面电场)LDMOS，双重降低表面电场LDMOS是通过多晶硅栅极场板/金属场板结合漂移区表面的P型掺杂区来降低双重降低表面电场LDMOS器件的表面电场，从而得到高源漏击穿电压(简称BV)和低导通电阻，但是电流通道要经过JFET区域(PN结型场效应晶体管区域)，JFET区域的大小以及掺杂浓度会限制LDMOS器件的导通电阻，JFET区域的大小以及掺杂浓度越大，LDMOS器件的导通电阻越大，然而要保证较高的源漏击穿电压，就需要牺牲一定的导通电阻。
发明内容
基于此，提供一种LDMOS器件及其制备方法。
一种LDMOS器件的制备方法，包括以下步骤：
获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆；
在所述第一导电类型掺杂区上开设沟槽，所述沟槽延伸至所述顶埋层和场氧化绝缘层结构，从而将所述顶埋层去除掉一部分；
注入第二导电类型离子、在所述沟槽下方形成阱区；
在所述阱区内形成源极掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
一个实施例中，所述在所述第一导电类型掺杂区上开设沟槽的步骤，是以所述场氧化绝缘层结构为硬掩膜进行刻蚀。
一个实施例中，所述在所述第一导电类型掺杂区上开设沟槽的步骤，形成的沟槽底部低于所述顶埋层的底部。
一个实施例中，所述获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆的步骤包括：
在所述第一导电类型掺杂区内形成所述顶埋层；
在所述顶埋层上形成所述场氧化绝缘层结构，将所述顶埋层部分覆盖，所述顶埋层在靠近所述沟槽的位置处有一截从所述场氧化绝缘层结构下方露出。
一个实施例中，所述第一导电类型是N型，所述第二导电类型是P型。
上述LDMOS器件的制备方法，将阱区的位置向下调整(形成于沟槽下方)，且由于顶埋层和场氧化绝缘层结构延伸至沟槽，使得顶埋层和场氧化绝缘层结构之间、顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的导通电阻大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压的同时得到更低的导通电阻。
一种LDMOS器件，包括：衬底；
第一导电类型掺杂区，设于所述衬底上，用于作为漂移区；
沟槽，开设于所述第一导电类型掺杂区上；
阱区，具有第二导电类型，设于所述沟槽下方；
源极掺杂区，设于所述阱区内；
顶埋层，具有第二导电类型，设于所述第一导电类型掺杂区内，一端延伸至所述沟槽；
场氧化绝缘层结构，设于所述顶埋层上方，一端延伸至所述沟槽；所述第一导电类型和第二导电类型为相反的导电类型。
所述沟槽的底部低于所述顶埋层的底部。
一个实施例中，所述LDMOS器件还包括：
栅氧结构，设于所述沟槽的底部和所述沟槽靠近所述顶埋层的侧壁；所述栅氧结构覆盖沟槽的部分底部以及所述顶埋层的部分表面；
栅极多晶硅，设于所述栅氧结构上；以及
栅极引出端，与所述栅极多晶硅电连接。
一个实施例中，所述源极掺杂区包括第一导电类型源极掺杂区和第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离顶埋层更近；
所述的LDMOS器件还包括源极引出端，分别与所述第一导电类型源极掺杂区、第二导电类型源极掺杂区电连接。
一个实施例中，所述LDMOS器件还包括漏极掺杂区，设于所述第一导电类型掺杂区上，所述漏极掺杂区和所述源极掺杂区被所述场氧化绝缘层结构隔开，所述漏极掺杂区具有第一导电类型；以及，
漏极引出端，与所述漏极掺杂区电连接。
上述LDMOS器件，将阱区的位置向下调整，设于沟槽下方，且由于顶埋层和场氧化绝缘层结构延伸至沟槽，使得顶埋层和场氧化绝缘层结构之间，顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的源漏击穿电压的大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压同时得到更低的导通电阻。
附图说明
图1为一个实施例中的LDMOS器件的结构示意图；
图2为另一个实施例中的LDMOS器件的结构示意图；
图3为一个实施例中的LDMOS器件的制备方法的流程示意图。
图4为一个实施例中的LDMOS器件的制备过程的LDMOS器件的结构示意图；
图5为另一个实施例中的LDMOS器件的制备过程的LDMOS器件的结构示意图；
图6为再一个实施例中的LDMOS器件的制备过程的LDMOS器件的结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
一个实施例中，请参阅图1，LDMOS器件包括衬底10、第一导电类型掺杂区11、沟槽12、阱区13、源极掺杂区14、顶埋层15以及场氧化绝缘层结构16，第一导电类型掺杂区11设于衬底10上，用于作为漂移区，沟槽12开设于第一导电类型掺杂区11上，阱区13设于沟槽12下方，其中阱区13具有第二导电类型，源极掺杂区14设于阱区13内，顶埋层15设于第一导电类型掺杂区11内，即漂移区内，且顶埋层15的一端延伸至沟槽12，顶埋层15具有第二导电类型，场氧化绝缘层结构16，设于顶埋层15上方，一端延伸至沟槽，第一导电类型和第二导电类型为相反的导电类型。其中，请参阅图1，源极掺杂区14可包括第一导电类型源极掺杂区141以及第二导电类型源极掺杂区142。
其中，第一导电类型可为N型，第二导电类型对应为P型，那么衬底10是P型衬底，漂移区是N型漂移区具体可以是N-型漂移区(N-型代表轻掺杂浓度的N型)，阱区13是P阱，顶埋层15是P型顶埋层。
第一导电类型也可为P型，第二导电类型第二导电类型对应为N型，源极掺杂区14则包括P型源极掺杂区和N型源极掺杂区。
在一个实施例中，沟槽12的底部低于顶埋层15的底部，使得沟槽12深于顶埋层15，沟槽12还可以深于顶埋层15与漂移区形成的PN结。
在一个实施例中，请参阅图1，部分场氧化绝缘层结构16设于第一导电类型掺杂区11的上方，其余的场氧化绝缘层结构16设于顶埋层15上方。
在一个实施例中，请参阅图2，LDMOS器件还包括栅氧结构17、栅极多晶硅18(图2中条纹结构)以及栅极引出端19。在图2所示的实施例中，栅氧结构17设于沟槽12的底部、沟槽12中靠近顶埋层15的侧壁以及场氧化绝缘层结构16部分表面，栅氧结构17覆盖沟槽12的部分底部、沟槽12中靠近顶埋层15的侧面以及场氧化绝缘层结构16的部分表面。栅极多晶硅18设于栅氧结构17上，栅极引出端19与栅极多晶硅18电连接。在其他实施例中，栅氧结构17设于沟槽12的底部和沟槽12中靠近顶埋层15的侧壁，栅氧结构17覆盖沟槽12的部分底部以及顶埋层15的部分表面。
在一个实施例中，请参阅图2，LDMOS器件还包括源极引出端20，源极引出端20分别与第一导电类型源极掺杂区141、第二导电类型源极掺杂区142电连接。
在一个实施例中，请参阅图2，LDMOS器件还包括漏极掺杂区21以及漏极引出端22，漏极掺杂区20设于第一导电类型掺杂区11上，漏极掺杂区21和源极掺杂区14被场氧化绝缘层结构隔开，漏极掺杂区21具有第一导电类型，漏极引出端22与漏极掺杂区21电连接。
上述LDMOS器件，通过开设沟槽12，并将阱区13设于沟槽12下方，使得阱区13的位置向下调整，且由于顶埋层15和场氧化绝缘层结构16延伸至沟槽12，使得顶埋层15和场氧化绝缘层结构16之间，顶埋15、场氧化绝缘层结构16和沟槽12之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的导通电阻的大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压同时得到更低的导通电阻。
基于上述实例中的LDMOS器件，还提出了一种LDMOS器件的制备方法。
一个实施例中的LDMOS器件的制备方法可制备出如图1所示的LDMOS器件，请参阅图3，该LDMOS器件的制备方法可包括以下步骤：
S11：获取形成有第一导电类型掺杂区11、且在第一导电类型掺杂区11内形成有顶埋层15、在顶埋层15上形成有场氧化绝缘层结构16的晶圆。
如图4所示，第一导电类型掺杂区是在衬底10上形成，衬底10具有第二导电类型，然后在衬底10上形成第一导电类型掺杂区11作为漂移区，然后在漂移区内形成顶埋层15，然后在顶埋层15上形成有场氧化绝缘层结构16，衬底具有第二导电类型，晶圆则可是如图4所示的结构。
在一个实施例中，如图4所示，步骤S11的实现步骤包括以下步骤：首先在所述第一导电类型掺杂区11内形成顶埋层15，然后在顶埋层15上形成场氧化绝缘层结构16，将顶埋层15部分覆盖，顶埋层15在靠近后续开设沟槽的位置处有一截从场氧化绝缘层结构16下方露出。如图4所示，本实施例是在顶埋层15和漂移区上形成场氧化绝缘层结构16，顶埋层15包住靠近源极掺杂区的场氧化绝缘层结构底部区域(如图4靠左的场氧化绝缘层结构底部区域)。
S12：在第一导电类型掺杂区上开设沟槽，沟槽延伸至顶埋层和场氧化绝缘层结构从而将顶埋层去除掉一部分。如图5椭圆圈中所示，顶埋层和场氧化绝缘层结构之间、顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，因此导电沟道不会经过JEFT区域。
在一个实施例中，如图5所示，在第一导电类型掺杂区11上开设沟槽12的步骤是在低于顶埋层的底部的位置开设沟槽12，使得在第一导电类型掺杂区11上形成的沟槽12的底部低于顶埋层15的底部，沟槽12还可以深于顶埋层15与漂移区形成的PN结。
在一个实施例中，在第一导电类型掺杂区上开设沟槽的步骤，是以场氧化绝缘层结构为硬掩膜进行刻蚀。如图5所示，漂移区上有两个场氧化绝缘层结构A和B，场氧化绝缘层结构A和场氧化绝缘层结构B按照从左往右方向(电流方向)排列，是在这个场氧化绝缘层结构中间的漂移区上形成沟槽，场氧化绝缘层结构用来隔开源极掺杂区和漏极掺杂区，故场氧化绝缘层结构A左边的漂移区和场氧化绝缘层结构B右边的漂移区是用于形成漏极掺杂区的，不会开设沟槽。
S13：注入第二导电类型离子、在沟槽12下方形成阱区。
本步骤是在图5的结构中的沟槽12上，以离子注入方式形成阱区，如图1所示是形成阱区后的结构。
S14：在阱区内形成源极掺杂区，如图1所示是形成源极掺杂区后的结构；第一导电类型和第二导电类型为相反的导电类型。其中，第一导电类型可为N型，第二导电类型第二导电类型对应为P型。
在一个实施例中，请参阅图1，在阱区内形成源极掺杂区的步骤是在阱区内形成第一导电类型源极掺杂区和第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离顶埋层更近；在所述阱区内形成源极掺杂区的步骤之后，在第一导电类型的源极掺杂区和第二导电类型源极掺杂区上引出源极引出端。第一导电类型源极掺杂区可为N型源极掺杂区，对应地，第二导电类型源极掺杂区为P型掺杂区。
一个实施例中，请参阅图6，在第一导电类型掺杂区上开设沟槽之后的步骤包括栅氧结构17的形成步骤：在沟槽12的底部和沟槽12中靠近顶埋层15的侧面形成连续栅氧结构，栅氧结构17覆盖沟槽12部分底部以及顶埋层15的部分表面。在其他实施例中，栅氧结构17的形成步骤包括：在沟槽12的底部、沟槽12中靠近顶埋层15的侧壁以及场氧化绝缘层结构16的部分表面上形成连续栅氧结构；栅氧结构17覆盖沟槽12部分底部、沟槽12中靠近顶埋层15的侧壁以及场氧化绝缘层结构16的部分表面；如图6所示，该沟槽12的侧壁是延伸至顶埋层和场氧化绝缘层结构的沟槽右侧壁，图中电流方向为从左往右。
形成栅氧结构17之后，在栅氧结构17上淀积形成栅极多晶硅18，然后在栅极多晶硅18引出栅极引出端19。
本实施例形成栅氧结构以及栅极多晶硅的步骤可以在开设沟槽之后执行，具体可以在形成阱区、源极掺杂区之后执行。
一个实施例中，请参阅图6，LDMOS器件的制备方法还包括以下步骤：在第一导电类型掺杂11内形成漏极掺杂区20，漏极掺杂区20和源极掺杂区14被场氧化绝缘层结构16隔开，漏极掺杂区20具有第一导电类型；电流是从第一导电类型的源极掺杂区流入漏极掺杂区的；然后在漏极掺杂区20引出漏极引出端。
上述LDMOS器件的制备方法，将阱区的位置向下调整(形成于沟槽下方)，且由于顶埋层和场氧化绝缘层结构延伸至沟槽，使得顶埋层和场氧化绝缘层结构之间，顶埋层、场氧化绝缘层结构和沟槽之间不存在第一导电类型掺杂区，这样导电沟道就不经过JEFT区域，LDMOS的导通电阻的大小能够摆脱JFET区域的限制，能够在获得高源漏击穿电压同时得到更低的导通电阻。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能组合都进行描述，然而只要这些技术特征的组合不存在矛盾，都应当是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施例，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种LDMOS器件的制备方法，其特征在于，包括以下步骤：
获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆；
在所述第一导电类型掺杂区上开设沟槽，所述沟槽延伸至所述顶埋层和场氧化绝缘层结构，从而将所述顶埋层去除掉一部分；
注入第二导电类型离子、在所述沟槽下方形成阱区；
在所述阱区内形成源极掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
2.根据权利要求1所述的LDMOS器件的制备方法，其特征在于，所述在所述第一导电类型掺杂区上开设沟槽的步骤，是以所述场氧化绝缘层结构为硬掩膜进行刻蚀。
3.根据权利要求1所述的LDMOS器件的制备方法，其特征在于，所述在所述第一导电类型掺杂区上开设沟槽的步骤，形成的沟槽底部低于所述顶埋层的底部。
4.根据权利要求1、2或3所述的LDMOS器件的制备方法，其特征在于，所述获取形成有第一导电类型掺杂区、且在所述第一导电类型掺杂区内形成有顶埋层、在所述顶埋层上形成有场氧化绝缘层结构的晶圆的步骤包括：
在所述第一导电类型掺杂区内形成所述顶埋层；
在所述顶埋层上形成所述场氧化绝缘层结构，将所述顶埋层部分覆盖，所述顶埋层在靠近所述沟槽的位置处有一截从所述场氧化绝缘层结构下方露出。
5.根据权利要求1、2或3所述的LDMOS器件的制备方法，其特征在于，所述第一导电类型是N型，所述第二导电类型是P型。
6.一种LDMOS器件，其特征在于，包括：
衬底；
第一导电类型掺杂区，设于所述衬底上，用于作为漂移区；
沟槽，开设于所述第一导电类型掺杂区上；
阱区，具有第二导电类型，设于所述沟槽下方；
源极掺杂区，设于所述阱区内；
顶埋层，具有第二导电类型，设于所述第一导电类型掺杂区内，一端延伸至所述沟槽；
场氧化绝缘层结构，设于所述顶埋层上方，一端延伸至所述沟槽；
所述第一导电类型和第二导电类型为相反的导电类型。
7.根据权利要求6所述的LDMOS器件，其特征在于，其特征在于，所述沟槽的底部低于所述顶埋层的底部。
8.根据权利要求6或7所述的LDMOS器件，其特征在于，还包括：
栅氧结构，设于所述沟槽的底部和所述沟槽靠近所述顶埋层的侧壁；所述栅氧结构覆盖沟槽的部分底部以及所述顶埋层的部分表面；
栅极多晶硅，设于所述栅氧结构上；以及
栅极引出端，与所述栅极多晶硅电连接。
9.根据权利要求6或7所述的LDMOS器件，其特征在于，所述源极掺杂区包括第一导电类型源极掺杂区和第二导电类型源极掺杂区，第一导电类型源极掺杂区所在位置离顶埋层更近；
所述的LDMOS器件还包括源极引出端，分别与所述第一导电类型源极掺杂区、第二导电类型源极掺杂区电连接。
10.根据权利要求9所述的LDMOS器件，其特征在于，还包括漏极掺杂区，设于所述第一导电类型掺杂区上，所述漏极掺杂区和所述源极掺杂区被所述场氧化绝缘层结构隔开，所述漏极掺杂区具有第一导电类型；以及，
漏极引出端，与所述漏极掺杂区电连接。
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CN115132822A (zh) * 2022-05-19 2022-09-30 深圳基本半导体有限公司 一种ldmos器件及其制作方法和应用
CN115274858A (zh) * 2022-09-30 2022-11-01 北京芯可鉴科技有限公司 Ldmos器件、ldmos器件制造方法及芯片
CN115274858B (zh) * 2022-09-30 2023-01-17 北京芯可鉴科技有限公司 Ldmos器件、ldmos器件制造方法及芯片

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