CN107146802B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN107146802B
CN107146802B CN201710017739.7A CN201710017739A CN107146802B CN 107146802 B CN107146802 B CN 107146802B CN 201710017739 A CN201710017739 A CN 201710017739A CN 107146802 B CN107146802 B CN 107146802B
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semiconductor device
insulating film
film
conductor
conductive
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CN107146802A (zh
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福田夏树
岡嶋睦
大贺淳
田中利治
山口豪
高木刚
小村政则
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明涉及一种半导体装置及其制造方法。实施方式的半导体装置具有：积层体，具有经由层间绝缘膜而积层的多个第1导电膜；第1导电体，与所述积层体相接且在积层方向延伸；以及多个第1绝缘膜，与所述多个第1导电膜为同一层，配置于所述第1导电体与所述多个第1导电膜之间，且所述第1导电体具有沿着1个第1绝缘膜及1个第1导电膜上而突出的突出部，且所述突出部的侧面与所述1个第1导电膜的上表面接触。

Description

半导体装置及其制造方法
相关申请
本申请享受以美国临时专利申请62/301,903号(申请日：2016年3月1日)及美国专利申请15/074,338号(申请日：2016年3月18日)为基础申请的优先权。本申请通过参照这些基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
作为替代以低成本且大容量著称的闪存的半导体装置的一种，有将可变电阻膜使用于存储单元的可变电阻型存储器(ReRAM：Resistance RAM)。ReRAM因能够构成交叉点型的存储单元阵列，所以能够实现与闪存相同的大容量化。另外，为谋求更加大容量化，还在开发相对于半导体基板在垂直方向排列选择配线即位线的所谓VBL(Vertical Bit Line：垂直位线)构造的ReRAM。
发明内容
本发明的实施方式提供一种实现通过接触区域的小空间化而缩减芯片尺寸、且降低导通孔形成时的工艺难度的半导体装置及其制造方法。
实施方式的半导体装置具有：积层体，具有经由层间绝缘膜而积层的多个第1导电膜；第1导电体，与所述积层体相接且在积层方向延伸；以及多个第1绝缘膜，与所述多个第1导电膜为同一层，配置于所述第1导电体与所述多个第1导电膜之间，且所述第1导电体具有沿着1个第1绝缘膜及1个第1导电膜上而突出的突出部，所述突出部的侧面与所述1个第1导电膜的上表面接触。
附图说明
图1是表示第1实施方式的半导体装置的功能区块的图。
图2是表示所述第1实施方式的半导体装置的存储单元阵列的电路图。
图3是表示所述第1实施方式的半导体装置的存储单元阵列的概略立体图。
图4是表示所述第1实施方式的半导体装置的存储单元阵列的接触区域的概略构造的立体图。
图5是表示所述第1实施方式的半导体装置的存储单元阵列的接触区域的剖视图。
图6～13是说明所述第1实施方式的半导体装置的存储单元阵列的接触区域的制造步骤的剖视图。
图14是表示第2实施方式的半导体装置的存储单元阵列的接触区域的剖视图。
图15～18是说明所述第2实施方式的半导体装置的存储单元阵列的接触区域的制造步骤的剖视图。
具体实施方式
以下，一边参照附图，一边针对实施方式的半导体装置及其制造方法进行说明。
[第1实施方式]
首先，针对第1实施方式的半导体装置的整体构成进行说明。此外，以下虽以使用包含可变电阻元件的存储单元的三维构造的半导体装置为例进行说明，但以下说明的全部实施方式，也包括使用包含电荷蓄积膜的存储单元的情况等，且也可应用于具有三维构造的其他半导体装置。
图1是表示本实施方式的半导体装置的功能区块的图。
本实施方式的半导体装置如图1所示，具备：存储单元阵列1、行译码器2、列译码器3、上位区块4、电源5及控制电路6。
存储单元阵列1具有相互交叉的多条字线WL(导电膜)及多条位线BL(导电膜)以及配置于它们的交叉部的多个存储单元MC。行译码器2在存取动作时选择字线WL。列译码器3在存取动作时选择位线BL，且包含控制存取动作的驱动器。上位区块4选择存储单元阵列1中成为存取对象的存储单元MC。上位区块4对于行译码器2、列译码器3赋予行地址、列地址。电源5在数据的写入/读出时，产生对应于各个动作的特定的电压的组合，且供给至行译码器2及列译码器3。控制电路6按照来自外部的指令，进行对上位区块4发送地址等控制，另外，进行电源5的控制。
接下来，针对存储单元阵列1进行说明。
图2是本实施方式的半导体装置的存储单元阵列的电路图，图3是该半导体装置的存储单元阵列的概略立体图。
存储单元阵列1如图2所示，除所述字线WL、位线BL及存储单元MC外，还具有选择晶体管STR、全局位线GBL及选择栅极线SG。
存储单元阵列1如图3所示，具有位线BL相对于半导体基板SS的主平面垂直延伸的所谓VBL(Vertical Bit Line：垂直位线)构造。即，字线WL在Y方向及Z方向(积层方向)排列成矩阵状，且沿X方向延伸。位线BL在X方向及Y方向排列成矩阵状，且沿Z方向延伸。且，存储单元MC配置于字线WL及位线BL的交叉部。从这些点来看，存储单元MC在X方向、Y方向及Z方向排列成三维矩阵状。
存储单元MC如图2所示，包含可变电阻元件VR。可变电阻元件VR基于施加电压而在高电阻状态及低电阻状态间转换。存储单元MC根据该可变电阻元件VR的电阻状态而非易失性地存储数据。可变电阻元件VR通常存在从高电阻状态(复位状态)转换为低电阻状态(设置状态)的设置动作与从低电阻状态(设置状态)转换为高电阻状态(复位状态)的设置动作。另外，可变电阻元件VR有只在刚制造后需要的成形动作。该成形动作是在可变电阻元件VR内局部地形成电流易流通的区域(纤丝路径)的动作。成形动作是对可变电阻元件VR的两端施加比在设置动作及复位动作时使用的施加电压更高的电压而执行。
选择晶体管STR配置于位线BL的下端及全局位线GBL间。全局位线GBL如图3所示排列于X方向，且在Y方向延伸。各全局位线GBL共通地与沿Y方向排列的多个选择晶体管STR的一端连接。
选择晶体管STR由作为栅极发挥功能的栅极线SG控制。选择栅极线SG排列于Y方向，且在X方向延伸。排列于X方向的多个选择晶体管STR由作为它们的栅极发挥功能的1条选择栅极线SG一并控制。另一方面，在图3的情况下，在Y方向排列的多个选择晶体管STR由个别设置的选择栅极线SG独立地控制。
接着，针对存储单元阵列1与半导体基板上的周边电路的连接构造，以字线WL与周边电路的连接构造为例进行说明。以下，在存储单元阵列1之中，将配置与周边电路的连接配线的区域称为“接触区域1b”。此外，以下，虽使用存储单元阵列1具有字线WL＜0＞～＜3＞的例子进行说明，但以下说明的实施方式并不限定于此。
图4是表示本实施方式的半导体装置的存储单元阵列的接触区域的概略构造的立体图。
与存储单元MC连接的各字线WL＜i＞(i＝0～3)如图4所示，经由两个导通孔Z1＜i＞(导电体)及Z0＜i＞(导电体)而与配置于半导体基板上的周边电路(未图示)电连接。各字线WL＜i＞在接触区域1b中，具有用以与导通孔Z1＜i＞接触的接触部分WLb＜i＞。各导通孔Z1＜i＞在Z方向延伸，且以贯通接触部分WLb＜i＞的方式形成。在各导通孔Z1＜i＞，形成有至少在朝向X方向的两侧面突出的突出部Z1b＜i＞。导通孔Z1＜i＞通过该突出部Z1b＜i＞的一个侧面即底面与接触部分WLb＜i＞的上表面接触，而与字线WL＜i＞接触。另一方面，各导通孔Z0＜i＞配置于半导体基板及最下层的字线WL＜0＞间，在底面与周边电路电连接。且，因导通孔Z1＜i＞的底面与Z0＜i＞的上表面接触，所以字线WL＜i＞与周边电路电连接。
此处，因各字线WL＜i＞在Z方向积层，所以在配置导通孔Z1＜i＞时，需要注意导通孔Z1＜i＞与字线WL＜i＞以外的字线WL＜j＞(j＝i以外的0～3)的干涉。
从这点来说，在本实施方式中，将字线WL＜i＞的接触部分WLb＜i＞形成于从比所述字线WL＜i＞更上层的字线WL＜u＞(u＝i～3)的配置区域伸出的位置。在图4的例子的情况下，在Z方向积层的多条字线WL的端部形成为阶梯状，将阶梯的相当于台阶的部分作为接触部分WLb发挥功能。由此，能够避免导通孔Z1＜i＞与上层字线WL＜u＞的干涉。
然而，仅凭这样无法避免导通孔Z1＜i＞与字线WL＜l＞(l＝0～i-1)的干涉。
因此，在本实施方式中，进而将字线WL与周边电路的连接构造予以如下设定。
图5是本实施方式的半导体装置的存储单元阵列的接触区域的剖视图。图5是以图4所示的一点链线及虚线所示的范围a101～a104的剖视图。
存储单元阵列1具有：层间绝缘膜102，将导通孔Z0与在X方向上相邻的导通孔Z0间绝缘；蚀刻终止膜103，配置于导通孔Z0及层间绝缘膜102上；层间绝缘膜104及字线WL，交替地配置于蚀刻终止膜103上；层间绝缘膜106，配置于从Z方向观察的各部位(以范围a101～a104所示的位置)的最上层的字线WL＜i＞(i＝0～3)上；以及层间绝缘膜107，配置于层间绝缘膜106上。此处，导通孔Z0例如由氮化钛(TiN)形成。层间绝缘膜102、104及107例如由氧化硅(SiO2)形成。蚀刻终止膜103例如由氧化金属形成。字线WL例如由氮化钛(TiN)形成。层间绝缘膜106以与层间绝缘膜104及107不同的材料形成，例如由氮化硅(SiN)形成。
另外，存储单元阵列1具有在Z方向延伸且至少从层间绝缘膜106上表面抵达字线WL＜i＞底面的导通孔Z1＜i＞。在图5的情况下，导通孔Z1＜i＞从层间绝缘膜107的上表面抵达导通孔Z0＜i＞的上表面。导通孔Z1＜i＞贯通所接触的字线WL＜i＞的接触部分WLb＜i＞。在各导通孔Z1＜i＞的侧面与字线WL＜0＞～＜i＞的侧面之间配置有绝缘膜109，两者不接触。绝缘膜109以与层间绝缘膜106不同的材料形成，例如由氧化硅(SiO2)形成。另外，各导通孔Z1＜i＞在与层间绝缘膜106相同高度上具有向X方向两侧突出的突出部Z1b＜i＞。该突出部Z1b＜i＞具有在X方向上超过绝缘膜109而抵达接触部分WLb＜i＞的宽度，其底面与接触部分WLb＜i＞及绝缘膜109接触。即，通过所述存储单元阵列1的接触区域1b的连接构造，导通孔Z1＜i＞与字线WL＜i＞接触，另一方面，与下层的字线WL＜l＞绝缘。
接下来，针对存储单元阵列1的接触区域1b的制造步骤进行说明。
图6～13是说明本实施方式的半导体装置的存储单元阵列的接触区域的制造步骤的剖视图。
首先，在各导电膜101＜i＞(i＝0～3)及层间绝缘膜102上成膜蚀刻终止膜103。各导电膜101＜i＞例如以氮化钛(TiN)形成，且作为导通孔Z0＜i＞发挥功能。蚀刻终止膜103例如以氧化金属形成，在后续步骤的形成孔122时，成为用以抑制对于导电膜101过度蚀刻的膜。接着，在蚀刻终止膜103上交替积层多个层间绝缘膜104及导电膜105。此处，层间绝缘膜104例如以氧化硅(SiO2)形成。导电膜105例如由氮化钛(TiN)形成，且作为字线WL发挥功能。接着，如图6所示，在存储单元阵列1的接触区域1b中，将多个导电膜105形成为阶梯状。由此，在各导电膜105＜i＞，形成接触部分105b＜i＞。
接着，在包含导电膜101＜0＞～＜3＞的积层导电膜上成膜层间绝缘膜106。该层间绝缘膜106与各接触部分105b＜i＞接触。层间绝缘膜106以相对于层间绝缘膜104以及后续步骤中形成的层间绝缘膜107及绝缘膜109的材料可取得蚀刻的选择比的材料形成。在层间绝缘膜104、107及绝缘膜109以氧化硅(SiO2)形成的情况下，例如以氮化硅(SiN)形成。接着，在层间绝缘膜106上，成膜层间绝缘膜107。此处，层间绝缘膜107例如以氧化硅(SiO2)形成。接着，如图7所示，在层间绝缘膜107上成膜具有导通孔Z1的图案的抗蚀剂膜121。
接着，如图8所示，通过使用抗蚀剂膜121的各向异性蚀刻，在各接触部分105b＜i＞的位置，形成从层间绝缘膜107上表面抵达蚀刻终止膜103上表面的孔122＜i＞。
接着，如图9所示，通过使用抗蚀剂膜121的各向异性蚀刻，持续挖进各孔122＜i＞，直至穿通蚀刻终止膜103而露出导电膜101＜i＞的上表面为止。此外，在图8及图9所示的步骤时，也能够同时形成多个孔122。
接着，如图10所示，利用经由孔122＜i＞的等向性蚀刻，选择性地去除在孔122＜i＞的侧面露出的导电膜105＜0＞～＜i＞的端部(图10中以虚线表示的部位105e)。
接着，在去除抗蚀剂膜121后，如图11所示，对图10所示的部位105e埋入绝缘膜109。绝缘膜109例如以氧化硅(SiO2)形成。
接着，如图12所示，利用经由孔122＜i＞的等向性蚀刻，选择性地去除在孔122＜i＞的侧面露出的层间绝缘膜106的端部，直至各部位最上层的导电膜105＜i＞的上表面露出为止。由此，在孔122＜i＞的侧面，形成用于配置与接触部分105b＜i＞接触的导通孔Z1＜i＞的突出部Z1b＜i＞的部位106e。
最后，如图13所示，在对孔122＜i＞埋入导电膜108＜i＞后，利用CMP(ChemicalMechanical Polishing，化学机械抛光)等，将导电膜108＜i＞的上表面平坦化。导电膜108＜i＞例如以氮化钛(TiN)形成，且作为导通孔Z1＜i＞发挥功能。由此，如图5所示，形成与字线WL＜i＞和导通孔Z0＜i＞接触的导通孔Z1＜i＞。
通过以上制造步骤，形成图5所示的存储单元阵列1的接触区域1b的连接构造。
接下来，使用比较例，针对本实施方式的效果进行说明。
此处使用的比较例的半导体装置经由从字线抵达上层配线的第1导通孔(相当于本实施方式的导通孔Z1)、通过字线的配置区域外而从上层配线抵达第3导通孔(相当于本实施方式的导通孔Z0)的第2导通孔以及从第2导通孔抵达周边电路的第3导通孔，将各字线与周边电路电连接。此外，第1导通孔不具有相当于本实施方式的突出部Z1b的部分，其底面与字线的上表面直接接触。在比较例的情况下，通过使从字线抵达周边电路的电流路径暂时迂回至上层配线，而避免下层字线与导通孔的干涉。
在比较例的情况下，每1条字线需要3个导通孔。尤其，相对于存储单元阵列的接触区域，为配置第2导通孔而需要额外空间，因此会导致芯片尺寸增大。
从这点来说，在本实施方式的情况下，相对于1条字线WL配置两个导通孔Z1及Z0即可，在从Z方向观察的情况下，只要准备配置1个导通孔的区域即可。即，根据本实施方式，与比较例相比，能够将用于配置导通孔的空间抑制为一半以下。
另外，在比较例的情况下，如上所述，因第1导通孔的底面与字线的上表面直接接触，所以在形成配置第1导通孔的孔(相当于本实施方式的122)时，必须将该孔的底面对准字线的上表面。此处，当考虑形成与高度不同的多条字线接触的多个第1导通孔的情况时，配置这些第1导通孔的多个孔具有各不相同的深度。因此，如果想要同时形成这些孔，那么会因较深的孔的蚀刻的影响，而有将较浅的孔过度蚀刻的担忧。尤其在严重的情况下，还能想到孔不仅贯穿要与第1导通孔接触的字线、甚至抵达更下层的字线的情况。
从这点来说，在本实施方式的情况下，不仅能够使多个导通孔Z1的底面位置一致，进而还具有以各导通孔Z1＜i＞贯穿字线WL＜0＞～＜i＞为前提的接触构造。因此，在同时形成多个孔122的情况下，能够排除如比较例在形成深度不同的孔时过度蚀刻的风险。
由以上，根据本实施方式，能够提供一种实现通过接触区域的小空间化而缩减芯片尺寸、且降低导通孔形成时的工艺难度的半导体装置及其制造方法。
[第2实施方式]
首先，关于第2实施方式，针对存储单元阵列1与半导体基板上的周边电路的连接构造，以字线WL与周边电路的连接构造为例进行说明。
图14是本实施方式的半导体装置的存储单元阵列的接触区域的剖视图。图14为导通孔Z1＜3＞周边的剖视图。
本实施方式的导通孔Z1＜i＞(i＝0～3，图14的情况下为i＝3)具有只在朝X方向的侧面的其中一个形成的突出部Z1b＜i＞，且只在X方向的一侧与字线WL＜i＞接触。
在第1实施方式的情况下，突出部Z1b＜i＞虽以包围导通孔Z1＜i＞整个周围的方式形成，但在如本实施方式般突出部Z1b＜i＞只形成于导通孔Z1＜i＞周围一部分的情况下，仍然能够与字线WL＜i＞接触。即，根据本实施方式，即使为字线WL＜i＞具有未包围导通孔Z1＜i＞整个周围的形状的接触部分WLb＜i＞的情况下，也与第1实施方式同样地，能够实现导通孔Z1＜i＞与字线WL＜i＞的接触。
接下来，针对存储单元阵列1的接触区域1b的制造步骤进行说明。
图15～18是说明本实施方式的半导体装置的存储单元阵列的接触区域的制造步骤的剖视图。
首先，在作为导通孔Z1＜i＞(i＝0～3，图15～18的情况下为i＝3)发挥功能的导电膜201＜i＞(相当于图6的101)与层间绝缘膜202(相当于图6的102)上，形成包含蚀刻终止膜203(相当于图6的103)、多个层间绝缘膜204(相当于图6的104)、作为多条字线WL发挥功能的多个导电膜205(相当于图6的105)以及层间绝缘膜206(相当于图7的106)的积层体。此处，层间绝缘膜206以相对于层间绝缘膜204以及在后续步骤中形成的层间绝缘膜207(相当于图7的107)及绝缘膜209(相当于图11的109)的材料可取得蚀刻的选择比的材料形成。接着，在导电膜201＜i＞的位置去除层间绝缘膜204、导电膜205及层间绝缘膜206的端部后，在导电膜201＜i＞、层间绝缘膜202及层间绝缘膜206上成膜层间绝缘膜207。接着，如图15所示，在层间绝缘膜207上成膜具有导通孔Z1＜i＞的图案的抗蚀剂膜221。
接着，如图16所示，利用使用抗蚀剂膜221的各向异性蚀刻，在导电膜205的端部在侧面显露的位置，形成从层间绝缘膜206的上表面抵达至导电膜201＜i＞的上表面的孔222＜i＞。
接着，利用经由孔222＜i＞的等向性蚀刻，选择性地去除在孔222＜i＞的侧面露出的导电膜205＜0＞～＜i＞的端部。接着，如图17所示，对该去除的部位埋入绝缘膜209。
接着，如图18所示，利用经由孔222＜i＞的等向性蚀刻，选择性地去除在孔222＜i＞的侧面露出的层间绝缘膜206的端部，直至导电膜205＜i＞的上表面露出为止。由此，在孔222＜i＞的侧面的其中一个，形成配置与接触部分205b＜i＞接触的导通孔Z1＜i＞的突出部Z1b＜i＞的部位206e。
接着，剥离抗蚀剂膜221。最后，在对孔222＜i＞埋入作为导通孔Z1＜i＞发挥功能的导电膜后，利用CMP等，将该导电膜的上表面平坦化。由此，如图14所示，形成与字线WL＜i＞及导通孔Z0＜i＞接触的导通孔Z1＜i＞。
通过以上制造步骤，形成图14所示的存储单元阵列1的接触区域1b的连接构造。
以上，根据本实施方式，即使在以导通孔周围的一部分与存储单元阵列的配线接触的情况下，也能够获得与第1实施方式相同的效果。
[其他]
以上已说明本发明的若干实施方式，但这些实施方式为作为示例而提出，并非意图限定发明的范围。这些新颖的实施方式能够以其他各种方式实施，能够在不脱离发明主旨的范围内，进行各种省略、替换及变更。这些实施方式及其变化均包含在发明范围及主旨内，且包含在权利要求书所记载的发明及其等效的范围内。

Claims (20)

1.一种半导体装置，具有：
积层体，具有经由层间绝缘膜而积层的多个第1导电膜；
第1导电体，与所述积层体相接且在积层方向延伸；以及
多个第1绝缘膜，与所述多个第1导电膜为同一层，配置于所述第1导电体与所述多个第1导电膜之间；
所述第1导电体具有沿着1个第1绝缘膜及1个第1导电膜上突出的突出部，且所述突出部的侧面与所述1个第1导电膜的上表面接触；且
由与所述第1绝缘膜不同的材料构成的第2绝缘膜配置在所述积层体的1个第1导电膜上，且配置于与所述第1导电体的突出部同一层。
2.根据权利要求1所述的半导体装置，其还包括：
第3绝缘膜，由与所述第1绝缘膜相同的材料构成，配置于比所述第2绝缘膜以及所述突出部更上层。
3.根据权利要求1所述的半导体装置，其具有：
第2导电膜，在所述积层方向延伸；以及
多个存储单元，配置于所述多个第1导电膜及所述第2导电膜的交叉部。
4.根据权利要求1所述的半导体装置，其中
所述第1导电体在从所述积层方向观察的特定位置，与配置于最上层的所述第1导电膜接触。
5.根据权利要求1所述的半导体装置，其具有：
第2导电体，配置于所述积层方向的半导体基板及所述多个第1导电膜间，且所述第1导电体在其底面与所述第2导电体的上表面接触。
6.根据权利要求1所述的半导体装置，其
具有多个所述第1导电体，且
特定的第1导电体及其他第1导电体与不同的第1导电膜接触。
7.根据权利要求6所述的半导体装置，其中
所述多个第1导电膜形成为各第1导电膜的端部构成1个台阶的阶梯状，且所述多个第1导电体与形成为所述阶梯状的所述多个第1导电膜的端部接触。
8.根据权利要求6所述的半导体装置，其中
所述多个第1导电体在相同的所述积层方向的位置具有底面。
9.根据权利要求1所述的半导体装置，其中
所述第1导电体在朝向与所述积层方向交叉的方向的两侧面具有所述突出部。
10.根据权利要求1所述的半导体装置，其中
所述第1导电体仅在朝向与所述积层方向交叉的方向的侧面的其中一个具有所述突出部。
11.根据权利要求1所述的半导体装置，其中
所述第1导电体的突出部在朝向所述积层方向的侧面，与一所述第1绝缘膜的上表面接触。
12.一种半导体装置的制造方法，其是：
形成包含经积层的多个第1导电膜的积层体，
在1个所述第1导电膜上成膜第1绝缘膜，
形成至少从所述第1绝缘膜的上表面至特定的第1导电膜的底面为止在积层方向延伸的孔，
去除在所述孔的侧面露出的所述多个第1导电膜的端部，
在经去除的所述多个第1导电膜的端部的部位，埋入包含与所述第1绝缘膜不同材料的多个第2绝缘膜，
在所述第1绝缘膜及所述多个第2绝缘膜之中，将在所述孔的侧面露出的所述第1绝缘膜的端部选择性地去除，直至所述第1导电膜的上表面露出为止，形成沿着1个所述第2绝缘膜及1个所述第1导电膜上而突出的突出部，
将第1导电体埋入所述孔。
13.根据权利要求12所述的半导体装置的制造方法，其中
在形成所述孔之前，形成第3绝缘膜，所述第3绝缘膜由与所述第2绝缘膜相同的材料构成，且配置于比所述第1绝缘膜以及所述突出部更上层。
14.根据权利要求12所述的半导体装置的制造方法，其中
在形成所述积层体之前，在所述积层方向的半导体基板与形成所述积层体的位置之间成膜第2导电体，且
在形成所述孔时，持续挖进所述积层体，直至所述第2导电体的上表面在所述孔的底部露出为止。
15.根据权利要求14所述的半导体装置的制造方法，其中
在成膜所述第2导电体后，且在形成所述积层体之前，在所述第2导电体上成膜蚀刻终止膜。
16.根据权利要求12所述的半导体装置的制造方法，其中
在形成所述积层体后，且在成膜所述第1绝缘膜之前，从所述积层方向观察，对特定的第1导电膜，形成从比所述特定的第1导电膜更上层的第1导电膜的配置区域伸出的第1部分。
17.根据权利要求16所述的半导体装置的制造方法，其中
在形成所述孔时，在所述第1部分从所述孔的朝向与所述积层方向交叉的方向的两侧面露出的位置，形成所述孔。
18.根据权利要求16所述的半导体装置的制造方法，其中
在形成所述孔时，在所述第1部分从所述孔的朝向与所述积层方向交叉的方向的侧面的其中一个露出的位置，形成所述孔。
19.根据权利要求16所述的半导体装置的制造方法，其中
在成膜所述第1绝缘膜时，以与所述多个第1导电膜的第1部分接触的方式，成膜所述第1绝缘膜。
20.根据权利要求16所述的半导体装置的制造方法，其中
在形成所述孔时，同时形成在所述积层方向上具有相同深度的多个所述孔。
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