CN107134444A - 在半导体器件中集成电容器的方法及对应器件 - Google Patents
在半导体器件中集成电容器的方法及对应器件 Download PDFInfo
- Publication number
- CN107134444A CN107134444A CN201610829735.4A CN201610829735A CN107134444A CN 107134444 A CN107134444 A CN 107134444A CN 201610829735 A CN201610829735 A CN 201610829735A CN 107134444 A CN107134444 A CN 107134444A
- Authority
- CN
- China
- Prior art keywords
- conductive
- lead frame
- conductive layer
- dielectric layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000007639 printing Methods 0.000 claims description 9
- 239000007921 spray Substances 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000000463 material Substances 0.000 description 17
- 238000005516 engineering process Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000010949 copper Substances 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007711 solidification Methods 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- WWTBZEKOSBFBEM-SPWPXUSOSA-N (2s)-2-[[2-benzyl-3-[hydroxy-[(1r)-2-phenyl-1-(phenylmethoxycarbonylamino)ethyl]phosphoryl]propanoyl]amino]-3-(1h-indol-3-yl)propanoic acid Chemical compound N([C@@H](CC=1C2=CC=CC=C2NC=1)C(=O)O)C(=O)C(CP(O)(=O)[C@H](CC=1C=CC=CC=1)NC(=O)OCC=1C=CC=CC=1)CC1=CC=CC=C1 WWTBZEKOSBFBEM-SPWPXUSOSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229940126208 compound 22 Drugs 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- YCKOAAUKSGOOJH-UHFFFAOYSA-N copper silver Chemical compound [Cu].[Ag].[Ag] YCKOAAUKSGOOJH-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49589—Capacitor integral with or on the leadframe
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49586—Insulating layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
在一个实施例中,一种在半导体器件中集成电容器的方法包括:提供用于半导体器件的引线框,该引线框包括一个或多个导电区域;在该导电区域或多个导电区域上形成介电层;在介电层上形成导电层,因而形成包括被层夹在导电区域与导电层之间的介电层的一个或多个电容器;以及通过在半导体裸片与导电层之间提供电接触而将半导体裸片布置到引线框上。
Description
技术领域
本说明书涉及半导体器件。
一个或多个实施例可适用于在半导体器件中,例如在集成电路的金属引线框中集成电容器。
一个或多个实施例可以适用于使用倒装芯片技术在金属引线框封装中集成电容器。
背景技术
在半导体器件中集成电容(电容器)已经是深入调查和实验的课题。在半导体器件中,例如在集成电路的金属引线框中集成电容(电容器)可涉及使用各种技术。这些的示例是在US 2003/0011050 A1中公开的方案(其涉及使用专用的两层引线框)或在US 2010/0230784 A1中公开的方案(其展示了电容器电极(罩)的最大面积和在其之间的距离方面的某些限制)。
发明内容
不管现有技术活动,提供可能使用标准引线框可被应用至诸如举例而言倒装芯片封装之类的封装的改进方案将会是理想的,倒装芯片封装包括诸如焊料凸块、铜柱、或所谓的柱形凸块(包括诸如金、银或铜之类的材料)之类的特征。
根据一个或多个实施例,一种方法包括:
形成电容器,其中形成该电容器包括:
在引线框的导电区域上形成介电层,
在所述介电层上形成导电层,其中形成导电层包括在所述导电区域与所述导电层之间层夹所述介电层,以及
将半导体裸片布置到所述引线框上并且将所述半导体裸片电连接到所述导电层。
一个或多个实施例可涉及对应的半导体器件,例如集成电路。
一个或多个实施例针对一种半导体器件,其包括:
包括导电区域的引线框,
形成在所述导电区域上的介电层,
形成在所述介电层上的导电层,所述介电层被层夹在所述导电区域与所述导电层之间,所述导电区域、介电区域以及导电层形成集成在所述器件中的电容器,以及
被布置到所述引线框上并且被连接到所述导电层的半导体裸片。
权利要求是如本文提供的一个或多个实施例的技术公开的组成部分。
一个或多个实施例使得可能在半导体器件中集成高电容值而不依靠例如附接到引线框的离散电容。
一个或多个实施例使得可能使用标准封装过程,而同时保持在(多个)电容与器件之间的互连短路。
在一个或多个实施例中,由于凸块提供了主要贡献,寄生效应可以被减小。
一个或多个实施例通过使得其可能例如制造具有(多个)集成的电容的半导体器件,而允许追求封装最小化,这些半导体器件与没有这些(多个)电容的器件具有相同大小(例如,单个裸片)。
一个或多个实施例可以被应用至基于有机和/或陶瓷的封装技术,这可能通过使用焊接掩膜开口作为具有由于薄节点轮廓引起比标准有机预浸材料更有效的方案的能力的腔体。
一个或多个实施例可以被应用至各种技术,诸如四方扁平无引线(QFN)、四方扁平封装(QFP)、薄型小尺寸封装(TSOP)。
一个或多个实施例可以包括由薄膜或喷印而制造的介电材料和/或例如由网印基于微颗粒(铜银)或喷印分配的纳米颗粒(诸如铜、银、碳)的低温烧结的复合材料和其他导电材料而制造的导电材料层。
附图说明
现在将纯粹以示例的方式参照附图对一个或多个实施例进行描述,其中:
图1至图11例举了在一个或多个实施例中的各种步骤,其中图2、4、6、8和11各自表示沿着图1的线II-II、图3的线IV-IV、图5的线VI-VI、图7的线VIII-VIII和图10的线XI-XI的横截面示图,
图12例举了在一个或多个实施例中介电层对导电层尺寸公差,
图13例举了一个或多个实施例的可能的特征,
图14至图25进一步例举了可能的实施例,其中图17、19、23和25各自表示沿着图16的线XVII-XVII、图18的线XIX-XIX、图22的线XXIII-XXIII和图24的线XXV-XXV的横截面示图,
图26至图34进一步例举了实施例的可能的特征,其中图29和31各自表示沿着图28的线XXIX-XXIX和图30的线XXXI-XXXI的横截面示图。
将要理解的是,为了清楚的目的,各种附图可以不以相同的比例重现。
具体实施方式
在随后的说明书中,说明了一个或多个具体细节,旨在提供该公开的实施例的示例的深度理解。实施例可以由一个或多个具体细节或利用其他方法、部件、材料等获得。在其他情况下,已知的结构、材料或操作未被详细说明或描述,使得将不会模糊实施例的某些方面。
在本说明书的框架中对“实施例”或“一个实施例”的参考旨在指示相对于实施例的特定配置、结构、特性在至少一个实施例中是遵从的。因此,可能在本说明书中一点或多点出现的诸如“在实施例中”或“在一个(或多个)实施例中”之类的短语并不必涉及一个或相同的实施例。而且,如关于任何附图例举的特定的构造、结构或特性可以与如可能在其他附图中例举的一个或多个实施例中任何其他相当的方式结合。
本文使用的参考仅出于方便而被提供且因此并不限定实施例的范围或保护的程度。
如这里所列举的一个或多个实施例可通过例如借助倒装芯片(FC)技术而被应用到制造半导体器件(例如,集成电路)中,该倒装芯片技术例如在制造四方扁平无引线(QFN)集成电路中使用。
如在图1中示意性表示的,一个或多个实施例可以涉及提供金属(例如铜)引线框10,其具有例如通过已知手段设置在其上的选择性电镀部件12。
在一个或多个实施例(例如见图2的横截面示图)中,引线框10可以包括中央(可能是凹进的或低陷的)部分14,其例如是四边形/方形的。
在一个或多个实施例中,凹进部分14可以被蚀刻(通过任何标准蚀刻过程)至引线框10的厚度的大约一半,例如至50微米的深度(50·10-6m)。
图3和图4例举了在部分14处的介电层16的形成。
在一个或多个实施例中,介电层16可以包括由其间的间隙分开的多个部分。
在如本文例举的一个或多个实施例中,介电层16可以包括以方形矩阵状布置而被布置并且由交叉状间隙图案分开的四块“地”。应当以其他方式理解,这种布置仅是示例性的而不是强制性的。
用于制造介电层16的技术例如可以包括网印或喷印,可能接着诸如UV固化之类的固化。
用于在一个或多个实施例中使用的示例性介电材料可以包括由ResearchTriangle Park,NC,USA的DuPont Microcircuit Materials以商标名DuPont 5018销售的可UV固化的介电材料。这样的材料适用于以20+/-10微米(20+/-10·10-6m)的厚度被印刷。
用于在一个或多个实施例中使用的另一示例性介电材料可以包括由Big BeaverRoad,Troy,MI,USA的Toray以商标名RAYBRIDTM销售的可喷印的材料。
这样的材料可以以6+/-2微米(6+/-10·10-6m)的厚度被喷印。
图5和图6例举了在(多个)介电层16上的导电层18的可能形成。
在一个或多个实施例中,导电层18可以包括网印的导电层。
用于在一个或多个实施例中使用的示例性导电材料可以包括由Ormet Circuits,Inc.,Nancy Ridge Drive,San Diego CA,USA以商标名Ormet DAP 689销售的材料。
这样的导电层18可以以25+/-10微米(25+/-10·10-6m)的厚度被网印。
在其中区域14被凹进的一个或多个实施例中,区域14可以容纳介电层16和导电层18。
图7和图8例举了将设置有电接触焊盘(在附图中不可见)的半导体芯片或裸片20安装到图5和图6的组件上的可能性,该芯片或裸片被适配为:
-经由第一电连接件20a被连接到引线框10中的引线,并且
-经由一个或多个第二电连接件20b被连接到由层夹在引线框主体10(例如,腔体14的底表面)与(多个)导电层18之间的介电层16形成的(多个)电容器。
连接件20a、20b可以由各种技术形成。
适用于一个或多个实施例的连接技术可以包括倒装附接技术(例如,Sn/Ag/Cu或SAC凸块),可能包括回流焊(例如,在260℃峰值温度)以烧结导电层18并且回流SAC凸块。
图9至图11例举了是诸如封装模制复合物(PMC)之类的封装材料22以任何已知技术被模制到图7和图8中所示的组件上以完成半导体器件,该过程可能包括在背表面处蚀刻引线框12。
图12是例举了可能维度的介电层16对导电层18尺寸公差的示意性平面图(以微米单位表示:1微米=10-6m)。
图12也例举了电连接件20b的可能供给的示例(功率或信号电容连接件)。
图13通过与例如在图5中所示的示例性交叉状布置直接的对比而一般性地例举了在制造介电层16和/或导电层18的形状和/或表面中的多方面自由度。
图14至25例举了应用在前述中例举的概念以制造(例如,倒装)电容器,其被适配为通过触点连接到外接地GND。
例如,图14例举了通过在其上例如通过喷印形成介电层126(图15)而在引线框10中利用/配置引线中的一个引线(例如,放大的电镀焊盘120)的可能性,导电层128可以例如通过网印而被形成在介电层126上。可能产生的布置在图17的横截面示图中被例举。
在之前关于层16和18例举的相同材料可以被用于制造介电层126和导电层128以形成包括层夹在导电层128与焊盘120之间的介电层126的电容器。
图18例举了将半导体裸片20安装到图17的组件上的可能性,除了到向内定位在引线框10的裸片焊盘集合200的一组连接件(在附图中未示出)之外,半导体裸片20可以包括到导电层128的一个或多个连接件20b,即是到包括层夹在导电层128与引线框10的焊盘120之间的介电层126的电容器的一个或多个连接件20b。
图19和图20的序列例举了通过将设置在裸片20上的(多个)凸块浸在层128的未烧结的或未固化的材料(待被随后烧结或固化)中或通过将(较小的)凸块耦合到导电层128的已经烧结或固化的材料中而提供连接件20b(功率或信号电容连接件)的可能性。
在图19和图20中例举的两个选项提供了控制凸块“高度”(图19中的H指示)的可能性。
图21例举了将封装模制复合物22模制到因而制造的结构上,接着背部蚀刻(图22至图23)并且可能用介电喷印背部密封。
如在图23的横截面示图中例举的,背部蚀刻可以制造在包括电容器焊盘120的引线框与包括裸片焊盘集合200的内部分之间的机械分离(以及因而的电绝缘)。背部密封可以对应地导致形成在两部分之间的绝缘介电材料24:例如见图25。
图25还例举了将电容器焊盘120连接到接地GND的可能性,使得包括被层夹在导电层128与焊盘120之间的介电层126的电容器可以(经由连接件20b)被连接在裸片20与接地GND之间。
图26至图34例举了一个或多个实施例,其中在之前例举的相同准则可以被应用至不同类型的引线框,例如冲压的或穿透蚀刻的引线框10,其可能布置在带T上以包含模制。
从图26至图34,对应于已经在以上讨论的部件或元件的部件或元件用相同的附图标记指示,因而不必在本文中重复对其的具体描述。
简言之,图26和图27的序列例举了在引线框10的一个或多个部件14(例如,选择性电镀的)上介电层16的提供(例如,通过网印或喷印,可能使用在以上考虑的相同示例性材料)。再次,区域14的中央位置以及其可能的根据所示的交叉状图案的分区仅仅是示例性的而不是强制性的。
图28例举了提供(例如,通过网印,可能出于该目的通过在上文中例举的相同材料)导电层18到介电层16上的可能性,因而导致图29中例举的结构。
这样的结构再次展示了包括层夹在导电(例如,铜)裸片焊盘10与相似导电层18之间的介电层16的电容器。
图30至图32再次例举了将IC裸片20安装到图29的结构上的可能性,该IC裸片20设置有电连接件(例如凸块)20b以用于与导电层18电接触。
在一个或多个实施例中,裸片20可以被安装到静态未固化的导电层18上,例如利用相继的表面安装(SMT)回流以及在一个步骤(“一次性”)中执行的导电材料烧结。此外,控制如在图19和图20中例举的凸块高度H的能力将再次存在。
图33和图34例举了封装22被模制到图30至图32的结构上,其中图34例举了背部蚀刻以暴露针对产生的半导体器件的导电接触区域的可能结果。
在不损害根本原理的前提下,细节和实施例可以相对于已经仅通过示例的方式公开的做出变化,甚至显著地变化,而不脱离保护范围。
以上描述的各种实施例可以被组合以提供进一步的实施例。参考以上的具体描述,可以对实施例做出这些和其他变化。通常,在以下权利要求书中,使用的术语不应当被解释为对权利要求书限制为本说明书和权利要求书中公开的特定实施例,但应当被解释为包括连同权利要求书所要求的等效的全部范围一起的所有可能的实施例。相应地,权利要求书并不被说明书所限制。
Claims (20)
1.一种方法,包括:
形成电容器,其中形成所述电容器包括:
在引线框的导电区域上形成介电层,以及
在所述介电层上形成导电层,其中形成所述导电层包括在所述导电区域与所述导电层之间层夹所述介电层,以及
将半导体裸片布置到所述引线框上并且将所述半导体裸片电连接到所述导电层。
2.根据权利要求1所述的方法,其中形成所述介电层包括网印或喷印。
3.根据权利要求1所述的方法,其中形成所述导电层包括通过网印提供所述导电层。
4.根据权利要求1所述的方法,包括烧结或固化所述介电层和所述导电层中的至少一层。
5.根据权利要求1所述的方法,其中将所述半导体裸片电连接到所述导电层包括形成与所述半导体裸片和所述导电层接触的至少一个凸块。
6.根据权利要求1所述的方法,其中将所述半导体裸片布置到所述引线框上包括将所述半导体裸片放置为与处于未烧结或未固化状态的所述导电层电接触,并且所述方法进一步包括:
烧结或固化所述导电层。
7.根据权利要求1所述的方法,包括从以下中选择所述导电区域:
所述引线框的中央区域,以及
所述引线框的周边区域,其中层夹所述介电层包括在所选择的导电区域与所述导电层之间层夹所述介电层。
8.根据权利要求1所述的方法,包括:
选择所述导电区域作为所述引线框的周边区域,以及
i)连接所述引线框的所述周边区域至接地,和/或
ii)在所述周边区域与所述引线框的中央区域之间提供电绝缘。
9.根据权利要求1所述的方法,其中所述导电区域是所述引线框的凹进区域,所述凹进区域容纳所述介电层和所述导电层。
10.根据权利要求1所述的方法,包括将电绝缘层模制到被布置到所述引线框上的所述半导体裸片上。
11.一种半导体器件,包括:
引线框,包括导电区域,
介电层,形成在所述导电区域上,
导电层,形成在所述介电层上,所述介电层被层夹在所述导电区域与所述导电层之间,所述导电区域、介电区域以及导电层形成集成在所述器件中的电容器,以及
半导体裸片,被布置到所述引线框上并且被电连接到所述导电层。
12.根据权利要求11所述的半导体器件,进一步包括与所述半导体裸片和所述导电层接触的至少一个导电凸块。
13.根据权利要求11所述的半导体器件,其中所述导电区域是所述引线框的中央区域。
14.根据权利要求11所述的半导体器件,其中所述导电区域是所述引线框的周边区域,所述半导体器件进一步包括:
在所述引线框的中央区域与所述周边区域之间的电绝缘。
15.根据权利要求11所述的半导体器件,其中所述导电区域是所述引线框的凹进区域,所述凹进区域容纳所述介电层和所述导电层。
16.根据权利要求11所述的半导体器件,进一步包括被模制到所述半导体裸片上的电绝缘层。
17.一种方法,包括:
形成电容器,其中形成所述电容器包括:
在引线框的导电区域上形成介电层,以及
在所述介电层上形成导电层,其中形成所述导电层包括在所述导电区域与所述导电层之间层夹所述介电层;
在形成所述电容器之后,将半导体裸片布置到所述引线框上;以及
将所述半导体裸片电连接到所述导电层。
18.根据权利要求17的方法,其中:
形成所述介电层包括将所述介电层直接印刷到所述引线框的所述导电区域上;并且
形成所述导电层包括将所述导电层直接印刷到所述介电层上。
19.根据权利要求17所述的方法,其中将所述半导体裸片电连接到所述导电层包括形成与所述半导体裸片和所述导电层接触的至少一个凸块。
20.根据权利要求17所述的方法,其中将所述半导体裸片布置到所述引线框上包括将所述半导体裸片放置为与处于未烧结或未固化状态的所述导电层电接触,并且所述方法进一步包括烧结或固化所述导电层。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITUB2016A001121A ITUB20161121A1 (it) | 2016-02-26 | 2016-02-26 | Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo |
IT102016000020111 | 2016-02-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107134444A true CN107134444A (zh) | 2017-09-05 |
CN107134444B CN107134444B (zh) | 2020-07-10 |
Family
ID=55969425
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610829735.4A Active CN107134444B (zh) | 2016-02-26 | 2016-09-18 | 在半导体器件中集成电容器的方法及对应器件 |
CN201621061462.5U Active CN206059388U (zh) | 2016-02-26 | 2016-09-18 | 半导体器件 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201621061462.5U Active CN206059388U (zh) | 2016-02-26 | 2016-09-18 | 半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (2) | US10283441B2 (zh) |
CN (2) | CN107134444B (zh) |
IT (1) | ITUB20161121A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110491842A (zh) * | 2018-05-14 | 2019-11-22 | 意法半导体股份有限公司 | 半导体器件及对应的方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170309549A1 (en) * | 2016-04-21 | 2017-10-26 | Texas Instruments Incorporated | Sintered Metal Flip Chip Joints |
IT201700087174A1 (it) | 2017-07-28 | 2019-01-28 | St Microelectronics Srl | Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4714952A (en) * | 1984-11-01 | 1987-12-22 | Nec Corporation | Capacitor built-in integrated circuit packaged unit and process of fabrication thereof |
US5258575A (en) * | 1990-05-07 | 1993-11-02 | Kyocera America, Inc. | Ceramic glass integrated circuit package with integral ground and power planes |
US20030011050A1 (en) * | 1997-06-06 | 2003-01-16 | Bissey Lucien J. | Semiconductor die assembly having leadframe decoupling characters |
US7166905B1 (en) * | 2004-10-05 | 2007-01-23 | Integrated Device Technology, Inc. | Stacked paddle micro leadframe package |
JP2007019054A (ja) * | 2005-07-05 | 2007-01-25 | Nichicon Corp | ヒューズ内蔵型固体電解コンデンサ |
US20130154071A1 (en) * | 2011-12-14 | 2013-06-20 | Samsung Electro-Mechanics Company, Ltd. | Isolation Barrier Device and Methods of Use |
CN103872013A (zh) * | 2012-12-14 | 2014-06-18 | 三星电机株式会社 | 功率模块封装 |
WO2015182114A1 (ja) * | 2014-05-30 | 2015-12-03 | パナソニックIpマネジメント株式会社 | 半導体装置、内蔵用キャパシタユニット、半導体実装体と、内蔵用キャパシタユニットの製造方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6167231A (ja) * | 1984-09-10 | 1986-04-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH05326821A (ja) * | 1992-05-20 | 1993-12-10 | Hitachi Ltd | 半導体集積回路装置における容量形成方法、容量付リードフレーム、及び半導体集積回路装置 |
JPH0685156A (ja) * | 1992-09-02 | 1994-03-25 | Nec Kyushu Ltd | 半導体装置用リードフレーム |
JPH06216309A (ja) * | 1993-01-14 | 1994-08-05 | Oki Electric Ind Co Ltd | 半導体装置 |
JPH0745781A (ja) * | 1993-07-28 | 1995-02-14 | Dainippon Printing Co Ltd | 半導体装置及びそれに用いる多層リードフレーム |
US6538313B1 (en) * | 2001-11-13 | 2003-03-25 | National Semiconductor Corporation | IC package with integral substrate capacitor |
US7948078B2 (en) * | 2006-07-25 | 2011-05-24 | Rohm Co., Ltd. | Semiconductor device |
US20100230784A1 (en) | 2009-03-16 | 2010-09-16 | Triune Ip Llc | Semiconductor Packaging with Integrated Passive Componentry |
JP2012038873A (ja) * | 2010-08-06 | 2012-02-23 | Nec Tokin Corp | 半導体装置 |
JP5601275B2 (ja) * | 2010-08-31 | 2014-10-08 | 日立金属株式会社 | 接合材料、その製造方法、および接合構造の製造方法 |
US20120098090A1 (en) * | 2010-10-22 | 2012-04-26 | Intersil Americas Inc. | High-efficiency power converters with integrated capacitors |
US8288202B2 (en) * | 2010-11-22 | 2012-10-16 | STATS ChiPAC, Ltd. | Method of forming partially-etched conductive layer recessed within substrate for bonding to semiconductor die |
US8426254B2 (en) | 2010-12-30 | 2013-04-23 | Stmicroelectronics, Inc. | Leadless semiconductor package with routable leads, and method of manufacture |
US9165873B1 (en) * | 2014-07-28 | 2015-10-20 | Texas Instruments Incorporated | Semiconductor package having etched foil capacitor integrated into leadframe |
-
2016
- 2016-02-26 IT ITUB2016A001121A patent/ITUB20161121A1/it unknown
- 2016-09-18 CN CN201610829735.4A patent/CN107134444B/zh active Active
- 2016-09-18 CN CN201621061462.5U patent/CN206059388U/zh active Active
- 2016-09-30 US US15/282,619 patent/US10283441B2/en active Active
-
2019
- 2019-04-29 US US16/398,022 patent/US10593614B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4714952A (en) * | 1984-11-01 | 1987-12-22 | Nec Corporation | Capacitor built-in integrated circuit packaged unit and process of fabrication thereof |
US5258575A (en) * | 1990-05-07 | 1993-11-02 | Kyocera America, Inc. | Ceramic glass integrated circuit package with integral ground and power planes |
US20030011050A1 (en) * | 1997-06-06 | 2003-01-16 | Bissey Lucien J. | Semiconductor die assembly having leadframe decoupling characters |
US7166905B1 (en) * | 2004-10-05 | 2007-01-23 | Integrated Device Technology, Inc. | Stacked paddle micro leadframe package |
JP2007019054A (ja) * | 2005-07-05 | 2007-01-25 | Nichicon Corp | ヒューズ内蔵型固体電解コンデンサ |
US20130154071A1 (en) * | 2011-12-14 | 2013-06-20 | Samsung Electro-Mechanics Company, Ltd. | Isolation Barrier Device and Methods of Use |
CN103872013A (zh) * | 2012-12-14 | 2014-06-18 | 三星电机株式会社 | 功率模块封装 |
WO2015182114A1 (ja) * | 2014-05-30 | 2015-12-03 | パナソニックIpマネジメント株式会社 | 半導体装置、内蔵用キャパシタユニット、半導体実装体と、内蔵用キャパシタユニットの製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110491842A (zh) * | 2018-05-14 | 2019-11-22 | 意法半导体股份有限公司 | 半导体器件及对应的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN107134444B (zh) | 2020-07-10 |
ITUB20161121A1 (it) | 2017-08-26 |
US10283441B2 (en) | 2019-05-07 |
CN206059388U (zh) | 2017-03-29 |
US20170250128A1 (en) | 2017-08-31 |
US10593614B2 (en) | 2020-03-17 |
US20190259691A1 (en) | 2019-08-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103367300B (zh) | 引线框、半导体装置以及引线框的制造方法 | |
KR100551641B1 (ko) | 반도체 장치의 제조 방법 및 반도체 장치 | |
CN103403864B (zh) | 具有凝聚端子的半导体封装体 | |
CN100423241C (zh) | 电路装置及其制造方法 | |
CN103066051B (zh) | 封装基板及其制作工艺、半导体元件封装结构及制作工艺 | |
US20090004774A1 (en) | Method of multi-chip packaging in a tsop package | |
TW201034151A (en) | Leadless integrated circuit package having high density contacts and manufacturing method | |
CN102456648B (zh) | 封装基板的制法 | |
US10756013B2 (en) | Packaged semiconductor system having unidirectional connections to discrete components | |
CN101174616A (zh) | 电路装置 | |
US20080308951A1 (en) | Semiconductor package and fabrication method thereof | |
CN109863594A (zh) | 具有颗粒粗糙化表面的封装半导体装置 | |
CN206059388U (zh) | 半导体器件 | |
KR20180002812A (ko) | 리드 캐리어 구조, 그리고 이로부터 다이 부착 패드들 없이 형성되는 패키지들 | |
CN107958893A (zh) | 改进的扇出球栅阵列封装结构及其制造方法 | |
JP2007287762A (ja) | 半導体集積回路素子とその製造方法および半導体装置 | |
US9202712B2 (en) | Lead frame and a method of manufacturing thereof | |
CN103972199B (zh) | 线键合方法和结构 | |
CN101652856A (zh) | 用于改良热性能的具有焊接盖的集成电路封装 | |
CN101770994A (zh) | 具有金属突点的半导体封装基板 | |
CN106601631A (zh) | 先封后蚀电镀铜柱导通一次包封三维封装结构的工艺方法 | |
CN106898593B (zh) | 半导体装置及其制造方法 | |
CN113299613A (zh) | 半导体封装结构及其制造方法 | |
KR101753416B1 (ko) | Ic 패키지용 리드프레임 및 제조방법 | |
JP2006286920A (ja) | 電子部品内蔵用リードフレーム、電子部品内蔵リードフレーム、および、樹脂封止型電子部品内蔵半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |