CN110491842A - 半导体器件及对应的方法 - Google Patents
半导体器件及对应的方法 Download PDFInfo
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- CN110491842A CN110491842A CN201910394928.5A CN201910394928A CN110491842A CN 110491842 A CN110491842 A CN 110491842A CN 201910394928 A CN201910394928 A CN 201910394928A CN 110491842 A CN110491842 A CN 110491842A
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- conductive layer
- conductive
- insulating layer
- core welding
- pipe core
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Abstract
本公开的实施例涉及半导体器件及对应的方法。一种半导体器件,包括:引线框,包括具有至少一个导电管芯焊盘区域的管芯焊盘;施加到导电管芯焊盘区域上的绝缘层。导电层被施加到绝缘层上,其中一个或多个半导体管芯例如粘合地耦合到导电层。导电管芯焊盘区域、导电层和夹在其间的绝缘层形成集成在器件中的至少一个电容器。导电管芯焊盘区域包括其中具有谷部和峰部的雕刻结构;导电层包括延伸到导电管芯焊盘区域的雕刻结构中的谷部中的导电填充材料。
Description
技术领域
本说明书涉及半导体器件。
一个或多个实施例可以应用于将至少一个电容器集成在至少一个半导体器件中,例如在引线框封装的集成电路的管芯焊盘(铜)块中。
背景技术
芯片级封装技术可能具有狭窄的空间限制,因此,分立电容器组件在面积占用方面可能具有高成本。
一项广泛的活动已致力于提供分立电容器在(芯片级)封装件内的集成,从而将组件放置在半导体管芯周围或之上。这可能导致平均封装尺寸的增加和占用面积方面的其他缺点。
发明内容
一个或多个实施例涉及具有引线框封装的半导体器件,该半导体器件包括:形成在管芯焊盘中的雕刻结构、导电填充材料层和夹在其间的绝缘层,可以是这种器件的示例。
一个或多个实施例可以涉及对应的方法。
一个或多个实施例可以应用于各种技术,诸如倒装芯片、QFN(四方扁平无引线)、QFN-mr(多行)、TQFP(薄四方扁平封装)。
一个或多个实施例可以包括在至少一个导电管芯焊盘区域中具有雕刻结构的管芯焊盘。
一个或多个实施例使得可以使用引线框蚀刻技术和/或激光蚀刻。
一个或多个实施例可以包括例如通过喷射印刷、喷涂或气溶胶分配例如可固化介电材料的气溶胶分配而提供的绝缘层。
一个或多个实施例可以包括UV或热固化绝缘层。
一个或多个实施例可以包括用导电填充材料(例如,导电胶)形成电容器的顶部电极。
一个或多个实施例可以包括例如通过基于微粒(例如,铜银)的低温烧结复合材料的丝网印刷或者导电材料(例如,铜、银、碳)的喷射印刷分配纳米颗粒而制造的导电层。
一个或多个实施例可以通过到至少一个电容器电极上的雕刻结构以增加电容器表面来促进改善电容增益。
一个或多个实施例促进为半导体器件提供(多个)集成电容器,该(多个)集成电容器与不具有这种电容器的器件相比具有相同的尺寸(例如,单个管芯)。
附图说明
现在将参考附图仅通过示例的方式描述一个或多个实施例,其中:
图1是可以用于制造根据实施例的半导体器件的某些部件的示例性透视图;
图2是图1的箭头II所示部分的放大视图;
图3是沿图1的III-III线的剖视图;
图4和图5是图3的箭头IV所示部分的可能不同实施例的放大视图;
图6是可以应用于图1中例示的部件的某些处理的示例性透视图;
图7是将图6中例示的处理应用于图4中例示的结构的可能结果的示例性放大视图;
图8是可以应用于图6中例示的部件的某些处理的示例性透视图;
图9是应用图8中例示的处理的可能结果的示例性放大视图;
图10是可以应用于图8中例示的部件的某些处理的示例性透视图;
图11是应用图10中例示的处理的可能结果的示例性放大视图;
图12是根据实施例的封装的半导体器件的示例性透视图;
图13是根据与图12的观察点基本相对的观察点的示例性透视图;
图14是沿图13的XIV-XIV线的剖视图;
图15至图18是实施例的可能发展的示例性透视图;
图19至图27是与引线框结构相关的实施例的可能发展的示例性透视图,其中图23是图22的箭头XXIII所示部分的放大视图,图25是图24的箭头XXV所示部分的放大视图,图26是沿图25的XXVI-XXVI线的剖视图;以及
图28是根据实施例的方法的示例性功能图。
应当理解,为了清楚和易于表示,各种附图可以不以相同的比例绘制。
具体实施方式
在随后的描述中,示出了一个或多个具体细节,旨在提供对本公开的实施例的示例的深入理解。实施例可以通过一个或多个具体细节或通过其他方法、组件、材料等获取。在其他情况下,未详细示出或描述已知的结构、材料或操作,使得实施例的某些方面不会被模糊。
在本说明书的框架中对“实施例”或“一个实施例”的引用旨在表示关于该实施例描述的特定配置、结构、特性在至少一个实施例中符合。因此,在本说明书中可能存在于一个或多个位置中的诸如“在实施例中”或“在一个(或多个)实施例中”等短语不一定指代同一实施例。此外,结合任何附图举例说明的特定构造、结构或特征可以在一个或多个实施例中以任何其他方式组合,如在其他附图中可能示例的。
本文中使用的参考仅仅是为了方便而提供的,因此不限定保护的范围或实施例的范围。
文献US 2017/250128 A1是将电容器集成在半导体器件中的示例。在半导体器件中(例如,在半导体封装件中)集成(高)电容电容器可能涉及严格的空间限制。
一个或多个实施例可以应用于制造半导体器件(例如,集成电路),例如,采用倒装芯片(FC)技术,例如,用于生产四方扁平无引线(QFN)、QFN多行(QFN-mr)或薄四方扁平封装(TQFP)集成电路。
图1是(金属,例如铜)引线框10的一个或多个实施例的透视图,其包括在引线框10中围绕管芯焊盘14的电接触结构(或引线)阵列12(要最终进行背蚀刻,如下所述)。
在一个或多个实施例中,电接触结构阵列12可能具有通过已知手段在其上提供的选择性电镀部件。
图2是图1的箭头II所示部分的放大视图。
在如本文中例示的一个或多个实施例中,引线框10的管芯焊盘14可以包括围绕(至少)一个导电管芯焊盘区域17的轮廓部分15。
在一个或多个实施例中,轮廓部分15也可以是导电的。
例如,轮廓部分15可以是描绘导电管芯焊盘区域17轮廓的管芯焊盘14的带状部分。带状部分15的端部可以例如通过间隙分开,从而部分15可以具有开放轮廓,例如,开放的方形轮廓。
在一个或多个实施例中,可以通过标准蚀刻工艺(例如,化学蚀刻工艺)提供导电管芯焊盘区域17。
在一个或多个实施例中,导电管芯焊盘区域17可以提供有至少一个雕刻结构/表面。
这种雕刻结构/表面可以有助于增加可以集成在如本文所述的器件中的至少一个电容器的电极的表面积。
在一个或多个实施例中,可以经由激光蚀刻引线框10的管芯焊盘14中的导电区域17来提供雕刻结构/表面。
应当注意,这种激光蚀刻可以有助于根据安装的不同类型的半导体管芯来定制引线框10的特性,如下面将讨论的(例如,参见图10、图18、图24)。
用于这种激光蚀刻工艺的示例性激光设备可以是从德国汉堡的ROFIN-SINARLaser GmbH可获取的ROFIN PowerLine Pico50。
带槽或开槽的表面可以是具有谷部和峰部的这种雕刻结构/表面的示例。例如,附图示出了具有交叉的、例如梳状横截面轮廓的带槽或开槽结构/表面的示例性实施例,其可以被视为包括梳状单元的一个或多个间隔重复部(参见,例如图4和图5)。
将另外理解的是,实施例不限于具有直线凹槽或狭槽的带槽或开槽结构/表面。例如,一个或多个实施例可以包括具有弯曲凹槽或狭槽的带槽或开槽图案,例如波浪形或迷宫图案。
而且,尽管本文中例示的实施例包括具有相同深度(即,均匀的雕刻深度)的凹槽或狭槽,但是一个或多个实施例可以包括具有不同深度(即,不均匀的雕刻深度)的凹槽或狭槽。
在一个或多个实施例中,如图4和图5中例示的雕刻结构可以包括谷部(凹陷沟道U)和峰部(顶表面P)的间隔重复部,例如周期性间隔的重复部。
图4和图5是导电管芯焊盘区域17的雕刻的可能尺寸(高度和宽度)的示例,例如,当使用标准蚀刻工艺(诸如化学蚀刻工艺(图4)或激光蚀刻(图5)蚀刻时),假定未蚀刻的引线框厚度“a”例如为0.15mm。
如图4所示,谷部U具有的深度“b”例如为0.07mm,并且宽度“c”等于例如0.05mm。峰部P具有的宽度“d”(在顶部)可以为例如0.05mm。
如图5所示,谷部U具有的深度“b”例如为0.1mm,并且宽度“c”等于例如0.06mm。峰部P具有的宽度“d”(在顶部)可以为例如0.07mm。
当然,所指示的值仅是示例性的而非限制实施例。
图6和图7是可以应用于图1中例示的部件的某些处理的示例:其中,图6是类似于图1的透视图,并且图7是将图6中例示的处理应用于图4中例示的结构的可能结果的示例性放大视图。
在一个或多个实施例中,(薄)绝缘层18可以施加到管芯焊盘14中的导电区域17上。因此,绝缘层18具有的轮廓可以遵循被雕刻到导电管芯焊盘区域17的表面上的谷部U和峰部V的轮廓。
在一个或多个实施例中,可以施加绝缘层18,例如通过喷射印刷。
在一个或多个实施例中,绝缘层18可以包括至少一种(可固化的)介电材料层。
可以在一个或多个实施例中使用的第一示例性电介质材料是以USA的NC的DuPontMicrocircuit Materials of Research Triangle Park的商品名DuPont LuxPrint 8153可获取的产品。
可以在一个或多个实施例中使用的另一种示例性介电材料是以USA的MA的Creative Materials,Inc.的商品名111-27可获取的产品。
可以在一个或多个实施例中使用的又一种示例性介电材料是以USA的IL的Applied Thin Films,Inc.的商品名Cerablak HTP可获取的产品。
在一个或多个实施例中,绝缘层18可以理想地包括具有高介电常数的介电材料,例如碳介电常数的数量级。
用于一个或多个实施例的示例性介电材料可以包括由USA的MA的Applied InkSolutions以商品名ANTISTAT-268销售的水基碳电阻涂层产品。
在一个或多个实施例中,施加在区域17上的绝缘层18可以通过标准固化工艺固化,例如UV固化或热固化。
例如,绝缘层18的厚度具有的值可以低于1微米(1微米=10-6m)。
图8是施加到图6的组件上的导电层20的一个或多个实施例的示例,例如在其上施加有绝缘层18的雕刻区域17(的整个或一部分)上。
在一个或多个实施例中,导电层20可以包括适于填充区域17的雕刻表面中的腔体的导电材料。
在一个或多个实施例中,导电层20可以包括导电粘合剂材料,例如具有银粉填料的导电胶。
在一个或多个实施例中,导电层20可以例如通过丝网印刷施加到绝缘层18上。
在一个或多个实施例中,绝缘层18因此可以夹在导电管芯焊盘区域17与导电层20之间以形成集成在如本文所述的器件中的电容器。
可以另外理解,雕刻的管芯焊盘区域17、导电层20和夹在其间的绝缘层18不必完全重叠。
应当注意,在技术沉积工艺的精度限制内,导电层20到组件上的任何布置都是可能的,以及半导体管芯22到导电层20上的任何布置都是可能的。例如,导电层应用可以具有+/-0.1mm的精度,而器件放置可以具有+/-0.15mm(1mm=10-3m)的精度。
例如,如图6和图8中可见,绝缘层18可以(也)在其上施加有导电层20的轮廓部分15上延伸,留下绝缘层18的周边部分未覆盖。
在一个或多个实施例中,导电层20可以延伸到(即,“填充”)谷部U,同时还覆盖区域17的雕刻结构的峰部P。
因此,如俯视图所示,导电层20可以表现为基本上均匀的表面。相反,在面向导电管芯焊盘区域17的一侧(绝缘层18夹在其间),导电层20可以呈现出与导电管芯焊盘区域17的雕刻结构基本上互补的雕刻结构。
如上所述,导电管芯焊盘区域17、导电层20和夹在其间的绝缘层18形成至少一个集成电容器(包括整体17、18和20),该电容器具有包括导电管芯焊盘区域17的“底部”电极和包括导电层20的“顶部”电极。
有利地,管芯焊盘区域17中的雕刻结构/表面(通过填充管芯焊盘区域17中的谷部U的导电层20以互补方式再现)有助于增加电容器的电极17、20的表面积,而不增加电容器占用率。
在一个或多个实施例中,这种雕刻结构有助于获取高电容值,例如在针对集成电容器17、18、20的纳法(1纳法=10-9F)的范围内。
如上所述,导电层/顶部电极20可以通过在绝缘层18上施加(例如,丝网印刷、注入)导电填充材料(可选地包括粘合剂材料)来获取。因此,顶部电极也可以具有梳状雕刻结构,例如与底部电极中的梳状雕刻结构相互交叉。
在一个或多个实施例中,导电层20可以被配置为包括将导电层20与前面讨论的电接触结构12a耦合的至少一个延伸部21,例如“轨道”。
在一个或多个实施例中,延伸部21可以通过再次将导电填充材料(可选地包括粘合剂材料)施加(例如,丝网印刷、注入)到最终将进行背蚀刻的引线框10的(至少)一部分来获取。
延伸部21可以便于电耦合到集成电容器17、18、20(即,包括导电管芯焊盘区域17、绝缘层18和导电层20的电容器)的“顶部”电极(即,导电层20)的电接触结构阵列12。
图9是将图8中例示的处理应用于导电管芯焊盘区域17的梳状单元16的可能结果的示例的放大视图。
图10是将一个或多个半导体芯片22布置在图8的组件上、即在导电层20上的可能性的示例(即,半导体芯片22布置在集成电容器17、18、20“之上”)。
在下面的讨论中,为了简单起见,将仅示出并且考虑一个半导体管芯22,然而,可以提供任何数目的半导体芯片。
如前所述,在一个或多个实施例中,导电层20可以包括粘合剂材料。这可以有助于将半导体管芯/芯片22粘合地耦合到导电层20。
在一个或多个实施例中,导电层20可以包括可固化材料。
在一个或多个实施例中,半导体管芯/芯片22可以安装到仍然未固化的导电层20上。
可选地,半导体管芯/芯片22可以通过本领域技术人员已知的其他方式安装到导电层20上。
图11是将半导体管芯/芯片22安装到导电层20上的可能结果的放大视图(再次称为图4中可见的梳状单元16)。
图12至图14是包括封装件28的半导体器件130的示例,该封装件28例如通过利用应用于其上模制有封装件28的引线框10的背表面10e的蚀刻工艺(用于此目的的本领域技术人员已知的任何类型)将电解绝缘封装模塑料(PMC)模制到图10和图11的组件上而提供。
背表面10e处的蚀刻工艺(“背蚀刻”)可以从引线框10的导电结构12(可能包括结构12a)形成个体的引脚,并且可以暴露管芯焊盘背面14e。
如图14的右侧所示,在一个或多个实施例中,导电层20的至少一部分(例如,一个或多个延伸部21)可以将引线框10的一个或多个导电接触区域12a与由导电层20、导电管芯焊盘区域17(绝缘层18夹在它们之间,出于比例的原因在图14中不可见)形成的电容器耦合。
在一个或多个实施例中,半导体管芯22可以具有电接触焊盘22a(参见例如图14),电接触焊盘22a被配置为耦合到:
引线框10,例如接触结构12中的一个接触结构;
集成电容器17、18、20。
在一个或多个实施例中,接触焊盘22a与引线框10的耦合可以经由引线接合结构24(由用于该目的的任何已知工艺提供)。
图15至图27是在一个或多个实施例中可以单独地或组合地包括的各种特征的示例。已经在前面讨论过的部件或元件等部件或元件用相同的参考标记表示,因此这里不必重复详细描述。
而且,应当理解,在任何其他一个图中所示的实施例中,可以单独地或组合地包括本文中结合在某一个图中示出的实施例而例示的特征。
例如,图15至图18是在管芯焊盘14中的多个导电区域17a-17d中(例如,管芯焊盘14中的四个导电区域17a-17d)包括多个雕刻结构的实施例的示例,具有谷部U和峰部P,如前所述。
在一个或多个实施例中,多个导电管芯焊盘区域(例如,四个区域17a-17d,这样的定量图形绝不是强制性的)的尺寸(表面区域)可以彼此不同。
在一个或多个实施例中,多个导电管芯焊盘区域17a-17d可以由于其中的谷部U和峰部P的不同取向而彼此不同,例如通过在相邻区域中相互正交定向的直线凹槽提供。
例如(如图15中可见):
区域17b中的凹槽可以与区域17a中的凹槽正交;
区域17c中的凹槽可以与区域17b中的凹槽正交;
区域17d中的凹槽可以与区域17c中的凹槽正交;以及
区域17a中的凹槽可以与区域17d中的凹槽正交。
换言之,管芯焊盘14中的管芯焊盘区域17a-17d中的雕刻部分可以包括具有方形矩阵状布置的相同雕刻结构的相互旋转的比例副本。
当然,前述仅是实施例中的可能的不同取向的示例。
在一个或多个实施例中,管芯焊盘区域17a-17d中的雕刻部分可以具有雕刻的梳状轮廓,其具有相同的高度、宽度以及峰部P与谷部U之间的距离。
在一个或多个实施例中,管芯焊盘区域17a-17d中的雕刻部分的表面积和各种尺寸可以彼此不同,例如高度和宽度a、b、c、d、e和/或其中的谷部U和峰部P的形状,因此具有不同的高度、宽度和/或峰部P与谷部U之间的距离。
例如,在一个或多个实施例中,管芯焊盘区域17a-17d中的雕刻部分可以具有相互镜像对称的相应的雕刻结构部分。
在一个或多个实施例中:
单个绝缘层18可以施加在管芯焊盘区域17a-17d中的雕刻部分上;或者
绝缘层18的各个不同部分18a-18d可以施加在区域17a-17d中的雕刻部分上。
类似地,在一个或多个实施例中:
可以提供在管芯焊盘区域17a-17d中的雕刻部分上延伸的单个导电层20;或者
导电层20中的各个不同的导电(层)部分20a-20d可以设置成在区域17a-17d中的相应的雕刻部分上延伸,例如以形成给定数目的“平面(lands)”。
后两种选择都可以与单个绝缘层18或绝缘层18的不同部分18a-18d组合。
刚刚讨论的各种可能性有助于提供集成在器件130中的多个电容器,它们可以彼此完全不同(例如,17a、18a、20a;17b、18b、20b;17c、18c、20c;17d、18d、20d),或者可以以平行布置的共享“顶部”和“底部”电极的共同部分。
此外,由于诸如它们的尺寸(表面积)和形态(例如,高度和宽度a、b、c、d、e和/或其中的谷部U和峰部P的形状)等因素,多个集成电容器可以具有相应的电容值(可能彼此不同),从而有助于获取多个集成电容器,例如具有不同的电容值。
无论在这方面采用何种选择,多个导电层部分20a-20d可以是(例如,正方形)矩阵状布置并且由十字形图案的间隙分开,从而使得十字形部分(例如,绝缘层18或导电管芯焊盘区域17)暴露以在电容器之间形成沟道。
在一个或多个实施例中,十字形部分/沟道因此可以由电绝缘材料填充,如参考封装件28所讨论的。
这种绝缘层18的暴露的十字形部分可以有助于在多个导电(层)部分20a-20d之间提供电绝缘,从而形成多个集成电容器的多个顶部电极。
在一个或多个实施例中,多个导电部分20a-20d可以包括相应的延伸部21a-21d,例如导电(填充材料)“轨道”,这些延伸部21a-21d耦合到电接触结构阵列12中的电接触结构12a-12d,以有利于将多个集成电容器电耦合到对应的接触引脚,基本上如前面结合在器件中提供单个集成电容器17、18、20而讨论的。
图18是其中半导体管芯22如前所述安装在多个导电部分20a-20d上的实施例的示例。同样,虽然为简单起见示出了单个半导体管芯22,但是可以提供多个半导体芯片22(例如,每个部分20a-20d一个)。
如先前结合在器件130中提供单个集成电容器17、18、20而讨论的,导电部分20a-20d可以包括粘合剂材料(以促进管芯/芯片22的粘合剂附接)和/或在安装管芯/芯片22时仍未固化的材料。
图19至图27是一个或多个实施例的示例,其中前述示例的相同标准可以应用于不同类型的引线框10,例如薄四方扁平封装(TQFP)引线框。
在一个或多个实施例中,引线框10可以包括围绕管芯焊盘14的电接触结构阵列12,例如从管芯焊盘14的侧面延伸的“翼形”引线。
同样,在前面已经讨论过的部件或元件等部件或元件用相同的参考标记表示,因此这里不必重复详细描述。
而且,将再次理解,在任何其他一个图中所示的实施例中,可以单独地或组合地包括本文中结合在某一个图中示出的实施例而例示的特征。
图22至图26表示包括经由(至少一个)引线接合结构24将半导体管芯/芯片22接合到阵列12中的至少一个导电结构的实施例。
在如图22至图24中例示的一个或多个实施例中,可以通过用于该目的的任何已知的方法将导电材料(例如,铜盘或圆柱体)的(引线接合)焊盘240施加到(例如,仍然未固化的)导电层20上。
利用将至少一个半导体管芯22施加到导电层20上,可以执行引线接合以便于通过以下方式形成电接合24:
第一电连接24a,其将引线框10的电接触引线12之一耦合到(引线接合)焊盘240;以及
第二电键24b,其将(引线接合)焊盘240耦合到半导体管芯22的触点22a。
图27是将封装件28提供到前面讨论的布置上的示例。封装件28的轮廓以阴影线示出,为简单起见,管芯/芯片22不可见。
图28是用于制造具有前述示例的特征的半导体器件130的示例的示意图。
在一个或多个实施例中,该方法可以包括第一组动作141,包括:
提供(金属,例如铜)引线框10,其具有电接触结构阵列12、以及在管芯焊盘14中的至少一个导电管芯焊盘区域17(图28中的框1411),
蚀刻(例如,化学蚀刻1412a或激光蚀刻1412b)引线框10的管芯焊盘14中的导电管芯焊盘区域17,例如通过在其中形成雕刻的梳状结构。
在一个或多个实施例中,图28中例示的方法的第二组动作142可以包括形成绝缘层18,例如通过向引线框10的管芯焊盘14中的导电管芯焊盘区域17上喷射印刷、喷涂或介电材料的气溶胶沉积中的一个。
例如,第二组动作142可以包括:
1421:例如经由印刷/喷涂或气溶胶,在引线框10的管芯焊盘14中的导电管芯焊盘区域17上形成绝缘材料,例如可固化的介电材料;
1422:例如经由UV或热固化来固化绝缘材料,从而形成具有减小的厚度的绝缘层18和引线框10的管芯焊盘14中的导电管芯焊盘区域17的相同的雕刻图案。
在一个或多个实施例中,该方法的第三组动作144可以包括:
1441:在绝缘材料18上形成导电层20(例如,包括导电粘合剂可固化材料的导电层),从而形成至少一个集成电容器,至少一个半导体管芯22将被放置在该集成电容器上;
1442:固化(例如,烘箱固化)导电层20,从而将管芯22附接到集成电容器17、18、20上;
1443:通过用于该目的的任何已知的方法进行等离子体清洁;
1444:提供引线接合24;
1445:通过用于该目的的任何已知的方法进行等离子体清洁;
1446:模塑封装件28;
1447:模具后固化;
1448:例如通过锯切提供具有至少一个集成电容器的至少一个半导体器件130,半导体器件130适于安装在诸如印刷电路板的基板上。
在一个或多个实施例中,半导体器件(例如,130)可以包括:
引线框(例如,10),其包括具有至少一个导电管芯焊盘区域(例如,17;17a、17b、17c、17d)的管芯焊盘(例如,14);
绝缘层(例如,18;18a、18b、18c、18d),其可以施加到上述至少一个导电管芯焊盘区域上;
导电层(例如,20;20a、20b、20c、20d),其可以施加到上述绝缘层上;
至少一个半导体管芯(例如,22),其可以耦合到上述导电层,其中至少一个导电管芯焊盘区域、导电层和夹在其间的绝缘层可以形成集成在器件中的至少一个电容器,其中:
至少一个导电管芯焊盘区域可以包括其中具有谷部(例如,U)和峰部(例如,P)的雕刻结构;以及
导电层可以包括导电材料,该导电材料延伸到至少一个导电管芯焊盘区域的上述雕刻结构中的谷部中。
在一个或多个实施例中,导电层可以包括粘合剂材料,其中至少一个半导体管芯(22)可以粘合地耦合到上述导电层。
在一个或多个实施例中,至少一个导电管芯焊盘区域的雕刻结构可以包括至少一个周期性的谷部和峰部的图案。
在一个或多个实施例中,至少一个导电管芯焊盘区域的雕刻结构可以包括梳状(例如,16)横截面轮廓。
在一个或多个实施例中,管芯焊盘可以包括可以提供集成在器件中的多个电容器的多个导电管芯焊盘区域(例如,17a、17b、17c、17d)。
在一个或多个实施例中,管芯焊盘可以包括多个导电管芯焊盘区域,多个导电管芯焊盘区域包括相应的其中具有谷部和峰部的雕刻部分。
在一个或多个实施例中,管芯焊盘中的多个导电管芯焊盘区域的上述相应的雕刻部分可以包括用于以下中的至少一个的彼此不同的相应的雕刻部分:
雕刻部分的表面积;和/或
其中的谷部和峰部的取向;和/或
其中的谷部和峰部的尺寸和/或形状(例如,a、b、c、d、e)。
在一个或多个实施例中,导电层可以包括可以提供集成在器件中的多个电容器的多个导电部分(例如,20a、20b、20c、20d)。
在一个或多个实施例中,半导体器件可以包括可以模制到耦合到上述导电层的至少一个半导体管芯上的封装件(例如,28)。
在一个或多个实施例中:
引线框可以包括围绕管芯焊盘的电接触结构阵列(例如,12;12a、12b、12c、12d);
导电层可以包括耦合到上述电接触结构阵列中的至少一个电接触结构以提供与其的电耦合的至少一个延伸部(例如,21;21a、21b、21c、21d)。
在一个或多个实施例中:
引线框可以包括围绕管芯焊盘的电接触引线阵列(例如,12);
可以提供引线接合(例如,24a,24b),以将上述导电层与在管芯焊盘周围的上述电触点引线阵列(12)中的至少一个引线(例如,12a)和/或在与上述导电层相对的接触位置(例如,22a)处的上述至少一个半导体管芯电耦合(例如,240)。
一个或多个实施例可以包括根据一个或多个实施例的制造半导体器件的方法(例如,140)。
在一个或多个实施例中,该方法可以包括:
通过在管芯焊盘中的上述至少一个导电管芯焊盘区域处选择性地蚀刻、优选地是激光蚀刻,提供(例如,141)上述雕刻结构;和/或
通过喷射印刷、喷涂或绝缘可固化材料的气溶胶沉积中的一个来形成(例如,142)上述绝缘层,并且热固化和/或UV固化可以施加到上述至少一个导电管芯焊盘区域上的上述绝缘层;和/或
通过丝网印刷导电填充材料,在上述绝缘层的至少一部分上形成(例如,144)上述导电层;和/或
在上述导电层中包括导电粘合剂材料,并且将上述至少一个半导体管芯粘合到上述导电层。
可以组合上述各种实施例以提供其他实施例。
在不影响基本原理的情况下,在不脱离保护范围的情况下,细节和实施例可以相对于仅作为示例描述的内容而变化,甚至是显著变化。
可以组合上述各种实施例以提供其他实施例。
根据以上详细描述,可以对实施例进行这些和其他改变。通常,在权利要求中,所使用的术语不应当被解释为将权利要求限制于说明书和权利要求中公开的特定实施例,而是应当被解释为包括所有可能的实施例以及这样的权利要求享有的等同物的全部范围。因此,权利要求不受本公开的限制。
Claims (21)
1.一种半导体器件,包括:
引线框,包括由导电材料制成并且具有谷部和峰部的管芯焊盘;
绝缘层,在所述管芯焊盘上;
导电层,在所述绝缘层上,其中所述导电层填充所述谷部,其中所述导电管芯焊盘区域、所述导电层和所述绝缘层形成电容器;以及
半导体管芯,被耦合到所述导电层。
2.根据权利要求1所述的半导体器件,其中所述导电层包括粘合剂材料,其中所述半导体管芯通过所述粘合剂材料被耦合到所述管芯焊盘。
3.根据权利要求1所述的半导体器件,其中所述管芯焊盘的所述谷部和所述峰部是谷部和峰部的图案。
4.根据权利要求1所述的半导体器件,其中所述导电管芯焊盘区域包括梳形横截面轮廓。
5.根据权利要求1所述的半导体器件,其中所述管芯焊盘包括彼此电隔离的多个导电管芯焊盘区域,所述多个导电管芯焊盘区域、所述导电层和所述绝缘层形成多个电容器。
6.根据权利要求5所述的半导体器件,其中所述多个导电管芯焊盘区域中的每个导电管芯焊盘区域包括谷部和峰部。
7.根据权利要求6所述的半导体器件,其中所述多个导电管芯焊盘区域中的至少一个导电管芯焊盘区域的所述谷部和所述峰部是与所述多个导电管芯焊盘区域中的其他导电管芯焊盘区域不同的取向。
8.根据权利要求1所述的半导体器件,其中所述导电层包括彼此分开以提供集成在所述器件中的多个电容器的多个导电部分。
9.根据权利要求1所述的半导体器件,包括在所述半导体管芯上的封装材料。
10.根据权利要求1所述的半导体器件,其中:
所述引线框包括围绕所述管芯焊盘的引线阵列;以及
所述导电层包括被耦合到所述引线阵列中的第一引线的延伸部。
11.根据权利要求1所述的半导体器件,其中:
所述引线框包括围绕所述管芯焊盘的引线阵列;以及
导电线将所述导电层与所述引线阵列中的至少一个引线电耦合。
12.一种方法,包括:
蚀刻、冲压或烧蚀管芯焊盘以形成峰部和谷部,其中所述管芯焊盘由导电材料制成;
在所述管芯焊盘上形成绝缘层,所述绝缘层覆盖所述管芯焊盘的所述峰部和所述谷部;
在所述绝缘层上形成导电层,其中所述管芯焊盘、所述绝缘层和所述导电层形成电容器;以及
将半导体管芯耦合到所述导电层。
13.根据权利要求12所述的方法,其中蚀刻、冲压或烧蚀所述管芯焊盘包括激光蚀刻所述管芯焊盘。
14.根据权利要求12所述的方法,其中形成所述绝缘层包括通过喷射印刷、喷涂或气溶胶沉积形成所述绝缘层。
15.根据权利要求14所述的方法,其中形成所述绝缘层还包括固化所述绝缘层。
16.根据权利要求12所述的方法,其中形成所述导电层包括在所述绝缘层上丝网印刷导电填充材料,其中将所述半导体管芯耦合到所述导电层包括在所述导电填充材料硬化之前将所述半导体管芯放置在导电粘合剂上。
17.根据权利要求12所述的方法,其中形成所述导电层包括在所述绝缘层上分配导电粘合剂材料,其中将所述半导体管芯耦合到所述导电层包括在所述导电粘合剂材料硬化之前将所述半导体管芯放置在所述导电粘合剂材料上。
18.一种半导体器件,包括:
管芯焊盘,具有峰部和谷部;
绝缘层,在所述管芯焊盘上,使得所述绝缘层在所述峰部上和在所述谷部中;
导电层,在所述绝缘层上,其中所述导电层位于所述峰部上并且填充所述谷部,其中所述管芯焊盘、所述绝缘层和所述导电层形成电容器;以及
半导体管芯,被耦合到所述导电层。
19.根据权利要求18所述的半导体器件,其中所述半导体管芯直接被耦合到所述导电层。
20.根据权利要求18所述的半导体器件,还包括与所述管芯焊盘间隔开的多个引线。
21.根据权利要求20所述的半导体器件,其中所述管芯焊盘被耦合到所述多个引线中的一个引线。
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