CN104781925B - 安装于衬底上的离散装置 - Google Patents

安装于衬底上的离散装置 Download PDF

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CN104781925B
CN104781925B CN201380056905.4A CN201380056905A CN104781925B CN 104781925 B CN104781925 B CN 104781925B CN 201380056905 A CN201380056905 A CN 201380056905A CN 104781925 B CN104781925 B CN 104781925B
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substrate
discrete
electrically conductive
conductive ink
package according
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CN104781925A (zh
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马修·D·罗米格
兰斯·C·莱特
莱斯利·E·斯塔克
弗兰克·斯特普尼克
斯里尼瓦萨恩·K·科杜里
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Texas Instruments Inc
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Texas Instruments Inc
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing Of Printed Wiring (AREA)

Abstract

本发明揭示一种制作具有安装于电子裸片的表面上的离散装置的电子装置的方法，其中所述离散装置及所述裸片两者通过经热固化的导电油墨连接且覆盖有经固化的囊封剂，所述方法包含：将所述离散装置放置于所述裸片上；及使所述离散装置及所述裸片中的每一者的温度保持低于约200℃。还揭示一种将离散装置电附接到衬底的方法，其包含：将所述装置放置于所述衬底上；施加导电油墨，所述导电油墨将所述装置上的至少一个端子连接到所述衬底上的至少一个触点；及使所述导电油墨固化。还揭示一种IC封装，其具有：离散电装置，其具有电端子；电衬底，其表面上具有接触垫；及经固化的导电油墨，其连接所述电端子中的至少一者与所述接触垫中的至少一者。

Description

安装于衬底上的离散装置
背景技术
集成电路(“IC”)封装在现代电子装置中是普遍存在的。典型的集成电路封装包含IC裸片(“芯片”)、引线框架及保护性囊封剂层。引线框架是通过在例如铜等导电材料薄片中切割图案而形成的。引线框架通常是以条带形式出现，其中在所述条带上以栅格阵列提供许多相同的引线框架图案。
IC裸片是其中提供执行预定功能的电路的小半导体材料(例如硅)块。裸片通常在顶表面上具有允许将裸片电路连接到外部电路的接触垫。
形成IC封装的常用方法包含将若干个相同裸片安装在引线框架条带的相同引线框架部分上。在裸片被安装于引线框架条带上之后，将裸片电连接到对应引线框架。在典型的工艺中，通过称为线接合的工艺借助小的细导线将裸片上的接触垫电连接到对应引线框架上的预定区。在一些情况中，可期望通过将离散电路装置附接到每一裸片而向所述裸片中并入额外功能性。离散电路装置通常是无源电路元件，例如电容器、电感器或电阻器。或者，离散装置可为更复杂的电路装置，例如传感器、微机电系统(MEMS)、振荡器或较小IC。离散电路装置通常以小的箱形配置提供，具有附接到对应裸片或其它电衬底上的两个接触垫的一对外部触点。
在完成对离散电路装置的线接合及附接之后，将引线框架条带移动到模制站(例如转移模制站)，在此处施加覆盖裸片、线接合、离散电路装置及引线框架中的每一者的大部分表面的模制化合物。每一引线框架的小的端部分不被涂覆有模制化合物以为后续形成的IC封装提供经暴露触点。在压力下将所施加模制化合物加热直到其固化到固态为止。经固化的模制化合物或“囊封剂”保护每一引线框架及相关联裸片、线接合连接件及离散装置的经囊封部分。
在模制化合物的固化之后，将引线框架条带切开或“单个化”以将条带分离成个别IC封装。在一种典型的情形中，每一IC封装包含经囊封裸片、线接合、离散装置及带有突出电触点的经囊封引线框架。
附图说明
图1是衬底及将安装于其上的离散装置的俯视透视图。
图2-5(现有技术)是图解说明放置通过焊料接缝附接的离散装置的常规方法的横截面侧视图。
图6-10是图解说明根据实例性所揭示实施例放置离散装置的方法的横截面侧视图及端视图。
图11-16是图解说明根据实例性所揭示实施例放置离散装置的经修改方法的横截面侧视图。
图17是将离散装置电附接到衬底的方法的流程图。
图18是制作具有安装于电子裸片的表面上的离散装置的电子装置的方法的流程图，其中所述离散装置及所述裸片两者均覆盖有经固化的囊封剂。
具体实施方式
图6-17揭示将离散电路装置40电附接到电衬底10(例如裸片)的实例性方法。所述方法包含将装置40放置于衬底10上并印刷至少一个导电油墨图案(例如，92、94)，所述至少一个导电油墨图案将装置40上横切于所述衬底延伸的至少一个端子(例如，56、58)连接到衬底10上的至少一个接触垫(例如，26、28)。在图10及16中，图式还揭示集成电路封装120，其包括具有电端子56、58的离散电路装置40及在其表面12上具有接触垫(例如，26、28)的衬底10。导电油墨图案96、98连接电端子56、58中的至少一者与接触垫26、28中的至少一者。IC封装120可具有保护性囊封剂涂层80。已如此大体描述了IC封装及将离散装置附接到衬底的方法，下文将进一步详细地描述IC封装及制作方法的各种实施例。
图1图解说明衬底，例如裸片10，其具有顶面表面12、底面表面14及边缘面表面16、18等。裸片10沿横向方向(X)、纵向方向(Y)及垂直方向(Z)延伸。在顶面表面12上提供多个接触垫20、22、24、26、28、30、32、34等，以用于将裸片10的内部电路连接到其它电装置。离散电路装置40(其可为无源电路元件，例如电阻器、电容器或电感器)将被安装于衬底10上。在所图解说明的实施例中，离散电路装置40呈大体箱形且可具有由陶瓷或其它绝缘体材料制成的外部。裸片10具有顶面表面42、底面表面44、前面表面46、背面表面48及两个端面表面52、54。离散装置40的端部分电镀有例如铜、银等导电金属，所述端部分接触装置40的内部电路(未展示)的端子端以提供外部经电镀端子56、58。
图2-5中图解说明以此项技术中已知的方式将离散装置40附接到衬底10。方法以将焊料膏图案72、74放置于两个接触垫26、28上而开始。焊料膏是以常规方式丝网印刷于裸片上且一般是在晶片层级上完成的。丝网印刷涉及相当长的设置周期且通常是一次对多个裸片而非一个裸片执行的。如图3中所展示，接着将离散装置40放置于裸片10上，其中装置40上的经电镀端子56、58啮合经印刷焊料膏图案72、74。通常使用取放机器来实现此目的。接下来，如图4中所展示，将图3的组合件移动到回流炉，所述回流炉通常在介于230℃与260℃之间的温度下操作。焊料膏72、74在回流炉中回流，从而形成焊料回流接缝76、78。接下来，如图5中所图解说明，将图4的组合件移动到例如常规转移模具等模制装置，在此处通过液体囊封剂层来覆盖裸片10及离散装置40，所述液体囊封剂层固化成硬的保护性囊封层80。
图6-10图解说明将离散装置40附接到裸片10的方法的实例性实施例，所述方法不使用焊料且因此避免回流炉的极端热量。图6展示衬底10(例如裸片)的具有接触垫26、28的一部分。如图7中所展示，工艺的第一部分是通过使用常规取放机器或其它机构将离散装置40放置于衬底10上。装置40通常被放置成其经电镀端子56、58接触衬底的接触垫26、28。(然而，在一些实施例(未展示)中，经电镀端子56、58不位于接触垫26、28上)。在图7中所展示的实施例中，除重力之外，不存在任何别的将离散装置40固持到衬底10的方式。接下来，如图8及8A中所图解说明，将大体L形经印刷导电油墨图案92、94印刷到经电镀部分56、58的端面52、54上及接触垫26、28上。可借助常规喷墨印刷机90来对印刷图案92、94进行喷墨印刷，在一个实施例中，喷墨印刷机90具有相对于衬底10的顶表面12以大约45度定向的喷嘴95。在印刷期间，首先使喷墨喷嘴95向下(方向ZZ)移动且接着使其横向(方向XX)移动以形成L形图案92、94。喷嘴95可具有适当纵向(方向YY)尺寸的尖端孔口，使得在单一遍次中印刷出L形图案(例如，94)的整个纵向宽度“a”。或者，可使用具有较小开口的喷墨喷嘴来印刷若干触及的邻近较小宽度L形遍次。尺寸“a”的典型范围可为约1μm到100μm。L形图案92、94的每一分支L1、L2的典型长度可为约50μm到200μm。并非使喷嘴90首先沿线性垂直方向然后沿线性横向方向移动，而是可使喷墨喷嘴95围绕纵向轴YY旋转以产生L形图案。
接下来，如图9中所图解说明，将图8的组合件移动到固化炉，在此处施加热量以使油墨固化，从而提供经固化的L形导电油墨图案96、98。取决于所使用的导电油墨的类型，固化步骤可在不同条件下进行。可使用的一种类型的油墨是纳米膏，其含有分散于基础液体介质中的纳米级(例如，直径为5nm)导电粒子。此项技术中已知使用纳米膏(例如，Ag纳米膏)来作为导电油墨。当所使用的导电油墨是纳米膏时，固化是在烧结炉中于约125℃到200℃的温度下进行的。当使用常规导电膏时，加热是在固化炉中于约125℃到175℃的温度下进行的。在一些情况中，还通过暴露于UV光来辅助固化，从而降低所需的时间及温度。
上述导电油墨图案92、94可全部由一或多条经喷墨印刷的迹线形成。此项技术中已知使用喷墨印刷机在二维表面上印刷导电迹线，如以下公开案中所描述：谢尔盖·雷米佐夫(Sergey Remizov)等人在2010年3月11日公开的题为“印刷电路板及制造方法(Printed Circuit Board and Manufacturing Method)”的第U.S.2010/0059251号美国专利申请公开案；白尹艾(Yoon-Ah Baik)等人在2010年6月17日公开的题为“表面处理方法、电路线形成方法、电路线形成设备及由其形成的印刷电路板(Surface Treatment Method，Circuit Lines Formation Method，Circuit Lines Formation Apparatus and PrintedCircuit Board Formed Thereby)”的第U.S.2010/0149249号美国专利申请公开案；李昭熙(Jong-Hee Lee)等人在2011年2月24日公开的题为“导电油墨、使用导电油墨制备金属布线的方法及使用此方法制备的印刷电路板(Conductive Ink，Method of Preparing MedalWiring Using Conductive Ink，and Printed Circuit Board Prepared Using Method)”的第U.S.2011/0042125号美国专利申请公开案，所述各案中的每一者针对其中所揭示的所有内容特此以引用方式并入本文中。以下申请案中也揭示了在电衬底上喷墨印刷导电油墨迹线：2012年8月22日申请的标题为“具有三维喷墨印刷迹线的电子组合件(ElectronicAssembly With Three Dimensional Inkjet Printed Traces)”的第US 13/591719号申请案，所述申请案的全部内容以引用方式并入本文中。
此项技术中已知可用于对导电迹线进行喷墨印刷的各种油墨配方，例如以引用方式并入的以上专利公开案中所揭示的油墨配方。在2010年7月15日公开的美国专利申请案U.S.2010/0178420中揭示了适合于印刷导电迹线的另一种此类油墨配方，所述美国专利申请案针对其中所揭示的所有内容特此以引用的方式并入本文中。可从各个制造商商购获得其它适合的喷墨油墨配方，例如杜邦公司(DuPont)、微电路材料事业部(MicrocircuitMaterials)、科研三角园区(Research Triangle Park)、NC 27709。一种此类杜邦喷墨油墨是以产品标示5000Silver Conductor出售的。
工艺中的下一步骤是将图9的组合件移动到例如常规转移模制装置等的模制化合物施加装置(未展示)，在此处施加覆盖衬底10及装置40以及上面安装衬底/裸片10的任何下伏引线框架(未展示)的大部分的模制化合物。在固化之后，所述模制化合物提供硬保护性囊封剂层80。囊封剂80将离散装置40牢固地且物理上固持于衬底10上的适当位置中。
图11-16中图解说明将离散装置40安装于衬底10上的经修改方法。在此方法中，如由图11所展示，第一步骤是将胶层110在接触垫26、28之间的区域中施加到衬底。接下来，如图12中所图解说明，将离散装置40定位于胶层110的顶部上，其中其经电镀端子56、58定位于接触垫26、28上面。接下来，如图13中所图解说明，将图12的组合件移动到胶固化炉，所述胶固化炉通常在约125℃到175℃的温度下操作。如图13所图解说明，在此阶段将液体胶110转化为经固化的胶层111，且因此胶层111将离散装置40在物理上固持于图13中所展示的位置处。接下来，如图14中所图解说明，图13的组合件具有以与上文参考图8所描述的方式相同的方式印刷在其上的L形导电油墨。接下来，如图15中所图解说明，将图14的组合件移动到油墨固化炉，在此处，湿的未固化导电油墨图案92、94被转化为经固化的导电油墨图案96、98。接下来，如图16所图解说明，将离散装置40及衬底10等囊封于保护性囊封剂层80中。因此，除胶层111以外，囊封剂80也用以将离散装置40相对于衬底10固持于固定位置中。
本文中所描述的将离散装置40安装于衬底10上的技术避免了与在参考图2-5所描述的现有技术方法中使用回流炉相关联的高温。新方法的实施例的另一优点是，不必同时将所有导体施加到所有相关联裸片。而是，一次一个地对导电油墨图案92、94进行喷墨印刷(如果需要如此操作)是很简单的事情。新方法的实施例的另一优点是，由于喷墨印刷及环氧树脂固化工艺的精确能力，可减小接触垫26及28的大小及间隔以及其到上面将放置其它离散装置的邻近垫的间隔。
图17图解说明将离散装置电附接到衬底的方法的流程图。所述方法包含将装置放置于衬底上并施加导电油墨，所述导电油墨将所述装置上横切于所述衬底延伸的至少一个端子连接到所述衬底上的至少一个触点。
图18图解说明制作具有安装于电子裸片的表面上的离散装置的电子装置的方法的流程图，其中所述离散装置及裸片两者均覆盖有经固化的囊封剂。所述方法包含将离散装置放置于裸片上，及从离散装置的放置一直到囊封剂的固化，使所述装置及裸片中的每一者的温度保持低于约200℃。
所属领域的技术人员将了解，在所主张发明的范围内，可对所描述实施例做出修改，且也可存在许多其它实施例。

Claims (9)

1.一种IC封装，其包括：
离散电装置，其具有第一表面、相对的第二表面、与所述第一表面和所述第二表面连接的多个第三表面，以及具有多个电端子，所述多个电端子中的至少一个端子实质上形成所述第三表面中的一者的至少一部分并实质上延伸到所述离散电装置的所述第一表面；
衬底，其具有与所述离散电装置直接接触的第一表面以及与所述衬底的所述第一表面对应的接触垫；以及
导电油墨，其电连接所述多个电端子中的所述至少一个端子与所述接触垫。
2.根据权利要求1所述的IC封装，其中所述导电油墨具有三维L形配置，所述三维L形配置具有碰触所述离散电装置的第一分支以及碰触所述衬底的第二分支。
3.根据权利要求1所述的IC封装，其中所述导电油墨包括纳米膏层。
4.根据权利要求1所述的IC封装，其中所述导电油墨包括导电膏层。
5.根据权利要求1所述的IC封装，其中所述离散电装置包括传感器、MEMS及振荡器中的至少一者。
6.根据权利要求2所述的IC封装，其中所述第一分支和所述第二分支具有1μm到100μm的横截面宽度。
7.根据权利要求1所述的IC封装，其进一步包括在所述离散电装置的一部分、所述导电油墨的一部分和所述衬底的一部分之上的囊封剂保护层。
8.根据权利要求1所述的IC封装，所述接触垫与所述离散电装置直接接触。
9.根据权利要求1所述的IC封装，所述至少一个端子位于所述接触垫上。
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US9646906B2 (en) * 2014-09-26 2017-05-09 Texas Instruments Incorporated Semiconductor package with printed sensor
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
US11682609B2 (en) 2019-06-29 2023-06-20 Texas Instruments Incorporated Three-dimensional functional integration
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Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6200146B1 (en) * 2000-02-23 2001-03-13 Itt Manufacturing Enterprises, Inc. Right angle connector
US6426552B1 (en) 2000-05-19 2002-07-30 Micron Technology, Inc. Methods employing hybrid adhesive materials to secure components of semiconductor device assemblies and packages to one another and assemblies and packages including components secured to one another with such hybrid adhesive materials
US7019391B2 (en) * 2004-04-06 2006-03-28 Bao Tran NANO IC packaging
KR100678419B1 (ko) * 2005-04-01 2007-02-02 삼성전기주식회사 기판의 표면처리방법, 배선형성방법 및 배선기판
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
GB0601008D0 (en) 2006-01-18 2006-03-01 Qinetiq Ltd Method of fabricating a semicondutor device
US20080169574A1 (en) * 2007-01-12 2008-07-17 Nokia Corporation Direct Die Attachment
US20100244056A1 (en) 2007-05-31 2010-09-30 Nthdegree Technologies Worldwide Inc. Addressable Or Static Light Emitting, Power Generating Or Other Electronic Apparatus
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
CN101999167B (zh) * 2008-03-12 2013-07-17 伊文萨思公司 支撑安装的电互连管芯组件
DE102008023882A1 (de) * 2008-05-16 2009-11-19 Bayer Materialscience Ag Druckbare Zusammensetzung auf Basis von Silberpartikeln zur Erzeugung elektrisch leitfähiger Beschichtungen
US20100025848A1 (en) 2008-08-04 2010-02-04 Infineon Technologies Ag Method of fabricating a semiconductor device and semiconductor device
KR100999506B1 (ko) 2008-09-09 2010-12-09 삼성전기주식회사 인쇄회로기판 및 그 제조 방법
JP2010141293A (ja) * 2008-11-14 2010-06-24 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
KR20100083391A (ko) 2009-01-13 2010-07-22 삼성에스디아이 주식회사 인쇄회로기판용 도전성 잉크 조성물의 제조 방법 및 인쇄회로기판의 제조방법
RU84542U1 (ru) * 2009-02-16 2009-07-10 Закрытое акционерное общество "Гирооптика" Микромеханический гироскоп-акселерометр
US20110115099A1 (en) * 2009-05-14 2011-05-19 Vertical Circuits, Inc. Flip-chip underfill
KR101082443B1 (ko) 2009-08-19 2011-11-11 삼성에스디아이 주식회사 도전성 잉크, 상기 도전성 잉크를 이용한 금속 배선의 형성 방법 및 상기 방법에 의하여 제조된 인쇄회로 기판
KR101088825B1 (ko) * 2010-07-09 2011-12-01 주식회사 하이닉스반도체 반도체 칩 및 이를 갖는 스택 패키지
KR102211934B1 (ko) * 2014-03-06 2021-02-04 삼성전자주식회사 반도체 패키지

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