CN104781925B - The discrete device being installed on substrate - Google Patents

The discrete device being installed on substrate Download PDF

Info

Publication number
CN104781925B
CN104781925B CN201380056905.4A CN201380056905A CN104781925B CN 104781925 B CN104781925 B CN 104781925B CN 201380056905 A CN201380056905 A CN 201380056905A CN 104781925 B CN104781925 B CN 104781925B
Authority
CN
China
Prior art keywords
substrate
discrete
electrically conductive
conductive ink
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380056905.4A
Other languages
Chinese (zh)
Other versions
CN104781925A (en
Inventor
马修·D·罗米格
兰斯·C·莱特
莱斯利·E·斯塔克
弗兰克·斯特普尼克
斯里尼瓦萨恩·K·科杜里
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN104781925A publication Critical patent/CN104781925A/en
Application granted granted Critical
Publication of CN104781925B publication Critical patent/CN104781925B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/24011—Deposited, e.g. MCM-D type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/245—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/822—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/822—Applying energy for connecting
    • H01L2224/8221—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/82399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/828—Bonding techniques
    • H01L2224/8284—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The present invention discloses a kind of method for making and having the electronic device for being installed on the discrete device on the surface of electronics bare die, both the wherein described discrete device and the bare die are connected by the electrically conductive ink through heat cure and are covered with cured encapsulant, and the method includes：The discrete device is positioned on the bare die；And the temperature of each of the discrete device and the bare die is made to keep below about 200 DEG C.A kind of method that discrete device is electrically attached to substrate is also disclosed, it includes：Described device is positioned on the substrate；Apply electrically conductive ink, at least one terminal in described device is connected at least one contact on the substrate by the electrically conductive ink；And the electrically conductive ink is made to cure.A kind of IC package is also disclosed, is had：Discrete electric installation, with electric terminal；Electric substrate has engagement pad on surface；And cured electrically conductive ink, connect at least one of at least one of described electric terminal and the engagement pad.

Description

The discrete device being installed on substrate
Background technology
It is generally existing that integrated circuit (" IC "), which is encapsulated in modern electronics,.Typically integrated antenna package includes IC bare dies (" chip "), lead frame and protectiveness encapsulant layers.Lead frame is by the conductive materials thin slice such as such as copper Middle cutting pattern and formed.Lead frame is typically to occur with strips, is carried with grid array wherein being taken in the item For many identical lead frame patterns.
IC bare dies are small semi-conducting material (such as silicon) blocks for wherein providing the circuit for executing predetermined function.Bare die usually exists There is the engagement pad for allowing die circuitry being connected to external circuit on top surface.
The common method for forming IC package includes that several same dies are mounted on to the identical lead of lead frame band On frame part.After bare die is installed on leadframe strip band, bare die is electrically connected to corresponding lead frame.In typical case Technique in, the engagement pad on bare die is electrically connected to by corresponding lead frame by small thin wire by the technique of referred to as wire bonding Fate on frame.In some cases, it may be desirable to the bare die by discrete circuit device is attached to each bare die In be incorporated to additional functionality.Discrete circuit device is typically passive electric circuit element, such as capacitor, inductor or resistor.Or Person, discrete device can be more complicated circuit device, such as sensor, MEMS (MEMS), oscillator or smaller IC.From Scattered circuit device is usually configured with small box-shaped and is provided, and has two engagement pads being attached on corresponding bare die or other electric substrates A pair of outer contact.
After completing to the wire bonding of discrete circuit device and attachment, lead frame band is moved to molding station (example Such as shift molding station), apply the big of each of covering bare die, wire bonding, discrete circuit device and lead frame here The mold compound of part surface.The small end part of each lead frame is not coated with mold compound with to be subsequently formed IC package offer be exposed through contact.Under stress by the heating of applied mold compound until it is cured to solid-state.Through Cured mold compound or " encapsulant " protect each lead frame and associated bare die, wire bonding connector and discrete device Encapsulated part.
After the solidification of mold compound, lead frame band is cut or " individualized " is band to be separated into individually IC package.In a kind of typical situation, each IC package includes encapsulated bare die, wire bonding, discrete device and carries protrusion The encapsulated lead frame of electric contact.
Description of the drawings
Fig. 1 is substrate and by the birds-eye perspective for the discrete device being mounted thereon.
Fig. 2-5 (prior art) is the cross for the conventional method for illustrating the discrete device for being placed through solder joints attachment Side cross-sectional view.
Fig. 6-10 is to illustrate to be regarded according to the cross-sectional side for the method that embodiment disclosed in exemplary places discrete device Figure and end-view.
Figure 11-16 is illustrated according to the transversal of the modified method of embodiment placement discrete device disclosed in exemplary Surface side view.
Figure 17 is the flow chart for the method that discrete device is electrically attached to substrate.
Figure 18 is the flow for making the method with the electronic device for being installed on the discrete device on the surface of electronics bare die Figure, wherein both the discrete device and the bare die are all covered with cured encapsulant.
Specific implementation mode
Fig. 6-17 discloses the exemplary methods that discrete circuit device 40 is electrically attached to electric substrate 10 (such as bare die).It is described Method includes that device 40 is positioned on substrate 10 to and printed at least one electrically conductive ink pattern (for example, 92,94), it is described at least One electrically conductive ink pattern is connected at least one terminal (for example, 56,58) that the substrate extends is transverse on device 40 At least one engagement pad (for example, 26,28) on substrate 10.In Figure 10 and 16, schema also discloses integrated antenna package 120, It includes having the discrete circuit device 40 of electric terminal 56,58 and the lining with engagement pad (for example, 26,28) on its surface 12 Bottom 10.Electrically conductive ink pattern 96,98 connects electric terminal 56, at least one of 58 and engagement pad 26, at least one of 28.IC Encapsulation 120 can have protectiveness encapsulant coating 80.It so generally describes IC package and discrete device is attached to substrate Method, the various embodiments of IC package and production method are described in further detail below.
Fig. 1 illustrates substrate, such as bare die 10, with top surface surface 12, bottom surface 14 and edge surface surface 16, 18 etc..(X), longitudinal direction (Y) and vertical direction (Z) extend bare die 10 in transverse direction.It is provided on top surface surface 12 multiple Engagement pad 20,22,24,26,28,30,32,34 etc., for the internal circuit of bare die 10 is connected to other electric installations.It is discrete Circuit device 40 (it can be passive electric circuit element, such as resistor, capacitor or inductor) will be installed on substrate 10. In embodiment illustrated, discrete circuit device 40 is in substantially box-shaped and can have by ceramics or other insulating material systems At outside.Bare die 10 has top surface surface 42, bottom surface 44, front-surface 46, backside surface 48 and two end face surfaces 52、54.The end part of discrete device 40 is electroplate with the conductive metal such as copper, silver, the inside of the end part contact device 40 The terminal end of circuit (not shown) is to provide external electroplated terminal 56,58.
It is illustrated in Fig. 2-5 and discrete device 40 is attached to substrate 10 in a manner known in the art.Method with Solder cream pattern 72,74 is positioned in two engagement pads 26,28 and is started.Solder cream is silk-screen printing in a usual manner in naked On piece and be usually to complete in wafer level.Silk-screen printing is related to the considerably long setting period and is typically once to multiple What bare die rather than a bare die executed.As shown in fig. 3, then discrete device 40 is positioned on bare die 10, wherein device Electroplated terminal 56,58 on 40 is engaged through printing soldering paste pattern 72,74.It is usually used to pick and place machine to realize this purpose. Next, as demonstrated in Figure 4, the sub-assembly of Fig. 3 is moved to reflow ovens, the reflow ovens are usually between 230 DEG C and 260 It is operated at a temperature of between DEG C.Solder cream 72,74 flows back in reflow ovens, to form solder reflux seam 76,78.It connects down Come, as illustrated in figure 5, the sub-assembly of Fig. 4 is moved to the device for molding such as conventional transfer mold, herein by Liquid encapsulant layers cover bare die 10 and discrete device 40, and the liquid encapsulant layers are solidified into hard protectiveness and are encapsulated layer 80。
Fig. 6-10 illustrates the example embodiments for the method that discrete device 40 is attached to bare die 10, and the method is not Avoid using solder and therefore the extreme heat of reflow ovens.Fig. 6 show substrate 10 (such as bare die) with engagement pad 26,28 A part.As shown in fig. 7, the first part of technique is to pick and place machine or other mechanisms by discrete device by using conventional 40 are positioned on substrate 10.Device 40 is normally placed in the engagement pad 26,28 of its electroplated terminal 56,58 contact substrate.(so And in some embodiment (not shown), electroplated terminal 56,58 is not located in engagement pad 26,28).It is shown in the figure 7 In embodiment, in addition to the gravitational force, there is no any other modes that discrete device 40 is secured to substrate 10.Next, such as Fig. 8 And it is illustrated in 8A, generally L-shaped is printed onto to the end face of electroplated part 56,58 through printing electrically conductive ink pattern 92,94 52, on 54 and in engagement pad 26,28.It can come to carry out ink jet printing to printed patterns 92,94 by conventional ink jet printer 90, In one embodiment, ink-jet printer 90 has the nozzle 95 that the top surface 12 relative to substrate 10 is oriented with about 45 degree. During printing, making inkjet nozzle 95 first, (direction ZZ) is mobile downwards and then makes its lateral (direction XX) mobile to form L-shaped Pattern 92,94.Nozzle 95 can have the tip aperture of appropriate longitudinal (direction YY) size so that print out L in single time time Entire longitudinally wide " a " of shape pattern (for example, 94).Alternatively, can be used the inkjet nozzle with smaller opening several to print The neighbouring smaller width L-shaped touched is all over secondary.The typical range of size " a " can be about 1 μm to 100 μm.L-shaped pattern 92,94 it is every One branch L1、L2Typical length can be about 50 μm to 200 μm.Not make nozzle 90 first along linear vertical direction then along Property horizontal direction movement, but inkjet nozzle 95 can be made to be rotated to produce L-shaped pattern around longitudinal axis YY.
Next, as illustrated in Fig. 9, the sub-assembly of Fig. 8 is moved to curing oven, apply heat here so that Ink solidification, to provide cured L-shaped electrically conductive ink pattern 96,98.Depending on the type of used electrically conductive ink, Gu Changing step can carry out at different conditions.Workable a type of ink is a nanometer cream, contains and is scattered in basal liquid Nanoscale (for example, a diameter of 5nm) conducting particles in medium.It is known in the art to use nanometer cream (for example, Ag nanometers Cream) it is used as electrically conductive ink.When used electrically conductive ink is nanometer cream, solidification is in sintering furnace in about 125 DEG C to 200 It is carried out at a temperature of DEG C.When using conventional conductive paste, heating be in curing oven at a temperature of about 125 DEG C to 175 DEG C It carries out.In some cases, it also assists curing by being exposed to UV light, to reduce required time and temperature.
Above-mentioned electrically conductive ink pattern 92,94 can be formed all by one or more trace through ink jet printing.In technique It is known that conductive trace is printed in two-dimensional surface using ink-jet printer, as described in following discloses case：Xie Ergailei meter Zuo Fu (Sergey Remizov) et al. entitled disclosed in 11 days March in 2010 " printed circuit board and manufacturing method The U.S. U.S.2010/0059251 of (Printed Circuit Board and Manufacturing Method) " is special Profit application publication；Bai Yinai (Yoon-Ah Baik) et al. it is entitled disclosed in 17 days June in 2010 " surface treatment method, Circuit line forming method, circuit line formed equipment and formed by it printed circuit board (Surface Treatment Method, Circuit Lines Formation Method, Circuit Lines Formation Apparatus and Printed Circuit Board Formed Thereby) " U.S.2010/0149249 Patent Application Publications；Li Zhaoxi (Jong-Hee Lee) et al. is entitled disclosed on 2 24th, 2011, and " electrically conductive ink prepares metal line using electrically conductive ink Method and using the method prepare printed circuit board (Conductive Ink, Method of Preparing Medal Wiring Using Conductive Ink, and Printed Circuit Board Prepared Using Method) " U.S.2011/0042125 Patent Application Publications, each of described each case be directed to wherein revealed institute There is content hereby incorporated herein by reference.The ink-jet printing conductive ink on electric substrate is also revealed in following application case Trace：Entitled " electronic subassembly (the Electronic with three-dimensional ink-jet printing trace filed in August in 2012 22 days Assembly With Three Dimensional Inkjet Printed Traces) " the application of US 13/591719 The full content of case, the application case is incorporated herein by reference.
The various ink formulations known in the art that can be used for carrying out conductive trace ink jet printing, such as with reference side The ink formulations disclosed in the above patent disclosure case that formula is incorporated to.In U.S. Patent Application Publication case on July 15th, 2010 The such ink formulations of another kind for being suitable for printing conductive trace, the United States Patent (USP) Shen are disclosed in U.S.2010/0178420 Please case be incorporated herein by reference hereby for wherein revealed all the elements.It can be commercially available from each manufacturer Other suitable ink jet ink formulations, such as E.I.Du Pont Company (DuPont), microcircuit materials division department (Microcircuit Materials), scientific research triangle garden (Research Triangle Park), NC 27709.A kind of such Du Pont's jetted ink It is to be sold with product indicia 5000Silver Conductor.
Next step in technique is the mold compound being moved to the sub-assembly of Fig. 9 such as routinely shifting device for molding Object bringing device (not shown) applies any of covering substrate 10 and device 40 and substrate/bare die 10 installed above here The most mold compound for the lead frame (not shown) that underlies.After solidification, the mold compound provides hard protection Property encapsulant layers 80.Encapsulant 80 is by discrete device 40 securely and in the appropriate location that is physically immobilizated on substrate 10.
Illustrate modified method discrete device 40 being installed on substrate 10 in Figure 11-16.In this method, such as It is shown by Figure 11, first step is to be applied to substrate in region by glue-line 110 between engagement pad 26,28.Next, such as It is illustrated in Figure 12, discrete device 40 is positioned on the top of glue-line 110, wherein its electroplated terminal 56,58 positions Above engagement pad 26,28.Next, as illustrated in Figure 13, the sub-assembly of Figure 12 is moved to adhesive curing stove, it is described Adhesive curing stove usually operates at a temperature of about 125 DEG C to 175 DEG C.As illustrated in Figure 13, in this stage by liquid glue 110 It is converted into cured glue-line 111, and therefore discrete device 40 is physically immobilizated in the position shown in Figure 13 by glue-line 111 Set place.Next, as illustrated, in figure 14, the sub-assembly of Figure 13 have by with above with reference to phase in a manner of described in Fig. 8 The L-shaped electrically conductive ink that same mode is printed thereon.Next, as illustrated in Figure 15, the sub-assembly of Figure 14 is moved To ink solidification stove, here, wet uncured electrically conductive ink pattern 92,94 is converted into cured electrically conductive ink pattern 96、98.Next, as illustrated in Figure 16, discrete device 40 and substrate 10 etc. are encapsulated in protectiveness encapsulant layers 80. Therefore, in addition to glue-line 111, encapsulant 80 is also discrete device 40 to be immobilizated in relative to substrate 10 in fixed position.
The technology described herein that discrete device 40 is installed on substrate 10 is avoided is retouched with reference to figure 2-5 The associated high temperature of reflow ovens is used in the art methods stated.Another advantage of the embodiment of new method is, it is not necessary to simultaneously All conductors are applied to all associated bare dies.But ink jet printing is carried out to electrically conductive ink pattern 92,94 one at a time (if necessary to so operation) is very simple thing.Another advantage of the embodiment of new method is, due to ink jet printing and ring The accurate capability of oxygen resin curing process, can reduce engagement pad 26 and 28 size and interval and its will be placed to above it is other The interval of the neighbouring pad of discrete device.
Figure 17 illustrates the flow chart for the method that discrete device is electrically attached to substrate.The method includes to put device It is placed on substrate and applies electrically conductive ink, the electrically conductive ink will be transverse at least one of the substrate extension in described device Terminal is connected at least one contact on the substrate.
Figure 18 illustrates the method for making and having the electronic device for being installed on the discrete device on the surface of electronics bare die Flow chart, wherein both the discrete device and bare die are all covered with cured encapsulant.The method includes will be discrete Device is positioned on bare die, and from the placement of discrete device until the solidification of encapsulant, makes every in described device and bare die The temperature of one keeps below about 200 DEG C.
Those skilled in the art will understand that in the range of institute's claimed invention, can make described embodiment and repair Change, and many other embodiments also may be present.

Claims (9)

1. a kind of IC package comprising：
Discrete electric installation is connect with first surface, opposite second surface, with the first surface and the second surface Multiple third surfaces, and there are multiple electric terminals, at least one of the multiple electric terminal terminal essentially forms institute It states at least part on one of third surface and extends essentially into the first surface of the discrete electric installation；
Substrate has the first surface being in direct contact with the discrete electric installation and the first surface with the substrate Corresponding engagement pad；And
Electrically conductive ink, at least one terminal being electrically connected in the multiple electric terminal and the engagement pad.
2. IC package according to claim 1, wherein the electrically conductive ink is configured with three-dimensional L-shaped, the three-dimensional L-shaped is matched It sets with touching the first branch of the discrete electric installation and touch the second branch of the substrate.
3. IC package according to claim 1, wherein the electrically conductive ink includes nanometer layer of paste.
4. IC package according to claim 1, wherein the electrically conductive ink includes conductive paste layer.
5. IC package according to claim 1, wherein the discrete electrical device includes in sensor, MEMS and oscillator At least one.
6. IC package according to claim 2, wherein first branch and second branch have 1 μm to 100 μm Cross-sectional width.
7. IC package according to claim 1 further comprises a part, the conduction in the discrete electric installation Encapsulant protective layer on a part for ink and a part for the substrate.
8. IC package according to claim 1, the engagement pad is in direct contact with the discrete electric installation.
9. IC package according to claim 1, at least one terminal is located in the engagement pad.
CN201380056905.4A 2012-11-05 2013-11-05 The discrete device being installed on substrate Active CN104781925B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/668,901 US9899339B2 (en) 2012-11-05 2012-11-05 Discrete device mounted on substrate
US13/668,901 2012-11-05
PCT/US2013/068475 WO2014071364A1 (en) 2012-11-05 2013-11-05 Discrete device mounted on substrate

Publications (2)

Publication Number Publication Date
CN104781925A CN104781925A (en) 2015-07-15
CN104781925B true CN104781925B (en) 2018-08-03

Family

ID=50621612

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380056905.4A Active CN104781925B (en) 2012-11-05 2013-11-05 The discrete device being installed on substrate

Country Status (3)

Country Link
US (1) US9899339B2 (en)
CN (1) CN104781925B (en)
WO (1) WO2014071364A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9646906B2 (en) 2014-09-26 2017-05-09 Texas Instruments Incorporated Semiconductor package with printed sensor
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
US11682609B2 (en) 2019-06-29 2023-06-20 Texas Instruments Incorporated Three-dimensional functional integration
US11569154B2 (en) 2021-05-27 2023-01-31 Texas Instruments Incorporated Interdigitated outward and inward bent leads for packaged electronic device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6200146B1 (en) * 2000-02-23 2001-03-13 Itt Manufacturing Enterprises, Inc. Right angle connector
US6426552B1 (en) 2000-05-19 2002-07-30 Micron Technology, Inc. Methods employing hybrid adhesive materials to secure components of semiconductor device assemblies and packages to one another and assemblies and packages including components secured to one another with such hybrid adhesive materials
US7019391B2 (en) * 2004-04-06 2006-03-28 Bao Tran NANO IC packaging
KR100678419B1 (en) * 2005-04-01 2007-02-02 삼성전기주식회사 Method for surface treatment of board, method for forming wiring and wiring substrate
US8067253B2 (en) * 2005-12-21 2011-11-29 Avery Dennison Corporation Electrical device and method of manufacturing electrical devices using film embossing techniques to embed integrated circuits into film
GB0601008D0 (en) 2006-01-18 2006-03-01 Qinetiq Ltd Method of fabricating a semicondutor device
US20080169574A1 (en) * 2007-01-12 2008-07-17 Nokia Corporation Direct Die Attachment
WO2008150965A2 (en) 2007-05-31 2008-12-11 Nthdegree Technologies Worldwide Inc. Method of manufacturing addressable and static electronic displays, power generating or other electronic apparatus
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
US8178978B2 (en) * 2008-03-12 2012-05-15 Vertical Circuits, Inc. Support mounted electrically interconnected die assembly
DE102008023882A1 (en) * 2008-05-16 2009-11-19 Bayer Materialscience Ag Printable composition based on silver particles for the production of electrically conductive coatings
US20100025848A1 (en) 2008-08-04 2010-02-04 Infineon Technologies Ag Method of fabricating a semiconductor device and semiconductor device
KR100999506B1 (en) 2008-09-09 2010-12-09 삼성전기주식회사 Printed circuit board and method of manufacturing the same
JP2010141293A (en) * 2008-11-14 2010-06-24 Seiko Epson Corp Semiconductor device and method for manufacturing the same
KR20100083391A (en) 2009-01-13 2010-07-22 삼성에스디아이 주식회사 Method of preparing conductive ink composition for printed circuit board and method of producing printed circuit board
RU84542U1 (en) * 2009-02-16 2009-07-10 Закрытое акционерное общество "Гирооптика" MICROMECHANICAL GYROSCOPE-ACCELEROMETER
US20110115099A1 (en) * 2009-05-14 2011-05-19 Vertical Circuits, Inc. Flip-chip underfill
KR101082443B1 (en) 2009-08-19 2011-11-11 삼성에스디아이 주식회사 Conductive ink, preparation method of metal micropattern using the same and printed circuit board prepared by the method
KR101088825B1 (en) * 2010-07-09 2011-12-01 주식회사 하이닉스반도체 Semiconductor chip and stack package having the same
KR102211934B1 (en) * 2014-03-06 2021-02-04 삼성전자주식회사 Semiconductor package

Also Published As

Publication number Publication date
CN104781925A (en) 2015-07-15
WO2014071364A1 (en) 2014-05-08
US9899339B2 (en) 2018-02-20
US20140124939A1 (en) 2014-05-08

Similar Documents

Publication Publication Date Title
CN103887265B (en) Integrated antenna package with layer printed circuit board and preparation method thereof
US10381286B2 (en) Power module
US20060043562A1 (en) Circuit device and manufacture method for circuit device
TWI511177B (en) Inkjet printed wirebonds, encapsulant and shielding
CN103633052B (en) Electronic building brick with three-dimensional ink-jet printing path line
CN104781925B (en) The discrete device being installed on substrate
CN102771200A (en) Multilayer printed circuit board and manufacturing method therefor
US9583436B2 (en) Package apparatus and manufacturing method thereof
KR20090081472A (en) Mounting substrate and method of manufacturing a semiconductor package using the same
CN104797083B (en) The method and its printed circuit board of embedding resistance in printed circuit board
CN108074907A (en) Semiconductor substrate comprising built-in module and the method for manufacturing the Semiconductor substrate
CN103632979A (en) Chip packaging substrate and structure, and manufacturing methods thereof
CN108155156A (en) Semiconductor package and its manufacturing method
CN110880456A (en) Custom lead frame from standard and printed lead frame parts
CN107665876A (en) Packaging body substrate, its manufacture method and packaging body
KR20140020767A (en) Chip-type electronic component and connecting structure
US20020084533A1 (en) Efficient multiple power and ground distribution of SMT IC packages
CN108352330A (en) Printing adhesion deposition for mitigating integrated circuit layering
CN110024110A (en) Integrated circuit packaging method and integration packaging circuit
CN104167369B (en) Manufacturing method of chip packaging structure
JP6193702B2 (en) Multiple wiring board
JP2007109938A (en) Semiconductor device
CN105282972B (en) Device internally-arranged type printed circuit board, semiconductor packages and its manufacturing method
JP6420088B2 (en) Manufacturing method of ceramic multilayer wiring board
JP6702410B2 (en) module

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant