ITUB20161121A1 - Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo - Google Patents

Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo

Info

Publication number
ITUB20161121A1
ITUB20161121A1 ITUB2016A001121A ITUB20161121A ITUB20161121A1 IT UB20161121 A1 ITUB20161121 A1 IT UB20161121A1 IT UB2016A001121 A ITUB2016A001121 A IT UB2016A001121A IT UB20161121 A ITUB20161121 A IT UB20161121A IT UB20161121 A1 ITUB20161121 A1 IT UB20161121A1
Authority
IT
Italy
Prior art keywords
seminonductor
procedure
correspondent devices
integrating condensers
condensers
Prior art date
Application number
ITUB2016A001121A
Other languages
English (en)
Inventor
Fulvio Vittorio Fontana
Giovanni Graziosi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITUB2016A001121A priority Critical patent/ITUB20161121A1/it
Priority to CN201621061462.5U priority patent/CN206059388U/zh
Priority to CN201610829735.4A priority patent/CN107134444B/zh
Priority to US15/282,619 priority patent/US10283441B2/en
Publication of ITUB20161121A1 publication Critical patent/ITUB20161121A1/it
Priority to US16/398,022 priority patent/US10593614B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
ITUB2016A001121A 2016-02-26 2016-02-26 Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo ITUB20161121A1 (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
ITUB2016A001121A ITUB20161121A1 (it) 2016-02-26 2016-02-26 Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo
CN201621061462.5U CN206059388U (zh) 2016-02-26 2016-09-18 半导体器件
CN201610829735.4A CN107134444B (zh) 2016-02-26 2016-09-18 在半导体器件中集成电容器的方法及对应器件
US15/282,619 US10283441B2 (en) 2016-02-26 2016-09-30 Method of integrating capacitors on lead frame in semiconductor devices
US16/398,022 US10593614B2 (en) 2016-02-26 2019-04-29 Integrated capacitors on lead frame in semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITUB2016A001121A ITUB20161121A1 (it) 2016-02-26 2016-02-26 Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo

Publications (1)

Publication Number Publication Date
ITUB20161121A1 true ITUB20161121A1 (it) 2017-08-26

Family

ID=55969425

Family Applications (1)

Application Number Title Priority Date Filing Date
ITUB2016A001121A ITUB20161121A1 (it) 2016-02-26 2016-02-26 Procedimento per integrare condensatori in dispositivi a seminconduttore e corrispondente dispositivo

Country Status (3)

Country Link
US (2) US10283441B2 (it)
CN (2) CN107134444B (it)
IT (1) ITUB20161121A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170309549A1 (en) * 2016-04-21 2017-10-26 Texas Instruments Incorporated Sintered Metal Flip Chip Joints
IT201700087174A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente metodo di fabbricazione di dispositivi a semiconduttore
IT201800005354A1 (it) 2018-05-14 2019-11-14 Dispositivo a semiconduttore e procedimento corrispondente

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167231A (ja) * 1984-09-10 1986-04-07 Matsushita Electric Ind Co Ltd 半導体装置
JPH05326821A (ja) * 1992-05-20 1993-12-10 Hitachi Ltd 半導体集積回路装置における容量形成方法、容量付リードフレーム、及び半導体集積回路装置
JPH0685156A (ja) * 1992-09-02 1994-03-25 Nec Kyushu Ltd 半導体装置用リードフレーム
JPH06216309A (ja) * 1993-01-14 1994-08-05 Oki Electric Ind Co Ltd 半導体装置
JPH0745781A (ja) * 1993-07-28 1995-02-14 Dainippon Printing Co Ltd 半導体装置及びそれに用いる多層リードフレーム
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6538313B1 (en) * 2001-11-13 2003-03-25 National Semiconductor Corporation IC package with integral substrate capacitor
US7166905B1 (en) * 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
US20120126416A1 (en) * 2010-11-22 2012-05-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die
US20130256390A1 (en) * 2010-08-31 2013-10-03 Hitachi Cable, Ltd. Junction material, manufacturing method thereof, and manufacturing method of junction structure

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JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
US5258575A (en) * 1990-05-07 1993-11-02 Kyocera America, Inc. Ceramic glass integrated circuit package with integral ground and power planes
JP2007019054A (ja) * 2005-07-05 2007-01-25 Nichicon Corp ヒューズ内蔵型固体電解コンデンサ
US7948078B2 (en) * 2006-07-25 2011-05-24 Rohm Co., Ltd. Semiconductor device
US20100230784A1 (en) 2009-03-16 2010-09-16 Triune Ip Llc Semiconductor Packaging with Integrated Passive Componentry
JP2012038873A (ja) * 2010-08-06 2012-02-23 Nec Tokin Corp 半導体装置
US20120098090A1 (en) * 2010-10-22 2012-04-26 Intersil Americas Inc. High-efficiency power converters with integrated capacitors
US8426254B2 (en) 2010-12-30 2013-04-23 Stmicroelectronics, Inc. Leadless semiconductor package with routable leads, and method of manufacture
US8674486B2 (en) * 2011-12-14 2014-03-18 Samsung Electro-Mechanics Isolation barrier device and methods of use
KR101420536B1 (ko) * 2012-12-14 2014-07-17 삼성전기주식회사 전력 모듈 패키지
WO2015182114A1 (ja) * 2014-05-30 2015-12-03 パナソニックＩｐマネジメント株式会社 半導体装置、内蔵用キャパシタユニット、半導体実装体と、内蔵用キャパシタユニットの製造方法
US9165873B1 (en) * 2014-07-28 2015-10-20 Texas Instruments Incorporated Semiconductor package having etched foil capacitor integrated into leadframe

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6167231A (ja) * 1984-09-10 1986-04-07 Matsushita Electric Ind Co Ltd 半導体装置
JPH05326821A (ja) * 1992-05-20 1993-12-10 Hitachi Ltd 半導体集積回路装置における容量形成方法、容量付リードフレーム、及び半導体集積回路装置
JPH0685156A (ja) * 1992-09-02 1994-03-25 Nec Kyushu Ltd 半導体装置用リードフレーム
JPH06216309A (ja) * 1993-01-14 1994-08-05 Oki Electric Ind Co Ltd 半導体装置
JPH0745781A (ja) * 1993-07-28 1995-02-14 Dainippon Printing Co Ltd 半導体装置及びそれに用いる多層リードフレーム
US6054754A (en) * 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6538313B1 (en) * 2001-11-13 2003-03-25 National Semiconductor Corporation IC package with integral substrate capacitor
US7166905B1 (en) * 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
US20130256390A1 (en) * 2010-08-31 2013-10-03 Hitachi Cable, Ltd. Junction material, manufacturing method thereof, and manufacturing method of junction structure
US20120126416A1 (en) * 2010-11-22 2012-05-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Partially-Etched Conductive Layer Recessed Within Substrate for Bonding to Semiconductor Die

Also Published As

Publication number Publication date
US20190259691A1 (en) 2019-08-22
US10283441B2 (en) 2019-05-07
US20170250128A1 (en) 2017-08-31
CN206059388U (zh) 2017-03-29
US10593614B2 (en) 2020-03-17
CN107134444B (zh) 2020-07-10
CN107134444A (zh) 2017-09-05

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