CN107039355A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN107039355A
CN107039355A CN201610960956.5A CN201610960956A CN107039355A CN 107039355 A CN107039355 A CN 107039355A CN 201610960956 A CN201610960956 A CN 201610960956A CN 107039355 A CN107039355 A CN 107039355A
Authority
CN
China
Prior art keywords
framework
lid
peripheral part
semiconductor device
junction surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610960956.5A
Other languages
English (en)
Other versions
CN107039355B (zh
Inventor
户洋哓
一户洋哓
西原达人
岩井裕次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN107039355A publication Critical patent/CN107039355A/zh
Application granted granted Critical
Publication of CN107039355B publication Critical patent/CN107039355B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6644—Packaging aspects of high-frequency amplifiers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/047—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/1632—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Semiconductor Lasers (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)

Abstract

本发明涉及一种半导体装置，涉及适合使用于通信设备、卫星以及雷达的高频模块，目的在于得到一种能够抑制从框架与盖的接合部产生的异物向腔室侵入的半导体装置。具有：安装部，其具有用于搭载半导体芯片的芯片搭载区域；框架，其以包围所述芯片搭载区域的方式设置于所述安装部；盖，其以覆盖由所述芯片搭载区域及所述框架包围的空间的方式，与所述框架接触地配置；以及接合部，其在所述框架与所述盖的接触面的外侧，将所述框架和所述盖进行接合。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，涉及适合使用于通信设备、卫星以及雷达的高频模块。
背景技术
在专利文献1中公开了半导体装置的封装构造。在该构造中，框架包围用于搭载半导体芯片的芯片搭载区域。在框架的上表面配置平板状的盖。框架与盖通过焊料进行接合，从而半导体装置被气密封装。
专利文献1：日本特开2001-176999号公报
在专利文献1所示的半导体装置中，由芯片搭载区域、框架以及盖形成作为中空构造的腔室。框架与盖进行接合，从而腔室被气密封装。在这里，框架和盖的接合部露出至腔室。从而，从接合部件即焊料产生的异物可能会侵入至腔室内。
发明内容
本发明就是为了解决上述的问题而提出的，其目的在于得到一种能够抑制从框架与盖的接合部产生的异物的侵入的半导体装置。
具有：安装部，其具有用于搭载半导体芯片的芯片搭载区域；框架，其以包围所述芯片搭载区域的方式设置于所述安装部；盖，其以覆盖由所述芯片搭载区域及所述框架包围的空间的方式，与所述框架接触地配置；以及接合部，其在所述框架与所述盖的接触面的外侧，将所述框架和所述盖进行接合。
发明的效果
在本发明的半导体装置中，框架与盖的接合部通过框架与盖的接触面而与腔室隔开。因此，利用接触面抑制从接合部产生的异物向腔室的侵入。
附图说明
图1是本发明的实施方式1涉及的半导体装置的剖视图。
图2是本发明的实施方式2涉及的半导体装置的剖视图。
图3是本发明的实施方式3涉及的半导体装置的剖视图。
图4是本发明的实施方式4涉及的半导体装置的剖视图。
图5是本发明的实施方式5涉及的半导体装置的剖视图。
图6是本发明的实施方式6涉及的半导体装置的剖视图。
图7是本发明的实施方式7涉及的半导体装置的剖视图。
图8是本发明的实施方式8涉及的半导体装置的剖视图。
标号的说明
10半导体装置，12安装部，18半导体芯片，20芯片搭载区域，31～38腔室，41～48盖，51～58框架，61～68外周部，70金锡合金，71～78接合部，81～88接触面，90槽，94～97台阶，194～197底面，294～297侧面，358倾斜面，261～268内侧面，163、165外侧面，466、467前端部
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置10进行说明。对相同或对应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是本实施方式涉及的半导体装置10的剖视图。半导体装置10具有安装部12和盖41。在安装部12处，在散热片16的上表面具有用于搭载半导体芯片18的芯片搭载区域20。在芯片搭载区域20，利用焊料24安装半导体芯片18及电路基板22。在芯片搭载区域20的两侧配置用于对半导体芯片18的输入输出信号进行传输的馈通部26。半导体芯片18及电路基板22通过键合导线而与馈通部26连接。在馈通部26的上表面配置用于将半导体装置10与外部电路进行连接的引线端子28。
在馈通部26的上表面以包围芯片搭载区域20的方式具有框架51。在框架51的上表面配置盖41。由芯片搭载区域20、框架51以及盖41所包围的空间形成腔室31。盖41具有在框架51的外侧向安装部12弯曲的外周部61。框架51与盖41在外周部61的内侧面261与框架51之间进行接合。其结果，腔室31被气密封装。框架51与盖41的接合部71形成于框架51与盖41的接触面81的外侧。另外，接合部71由金锡合金70形成。
盖41使用金属或者具有导电性表面的电介体。由此，能够抑制半导体装置10所发出的电磁波的泄露、以及外部的电磁波对半导体装置10的干扰。
下面，示出接合部71的形成方法。首先，对框架51及盖41实施镀金。然后，对盖41的朝向接合部71的部位实施镀锡。如果将盖41覆盖于框架51，则盖41的锡镀层与框架51的金镀层接触。在锡镀层与框架51的金镀层接触的状态下，利用加热炉或者回流处理而对接合部71进行加热。其结果，在接合部71形成金锡合金70，能够实现气密封装。
另外，盖41是按照下面的顺序而制作的。首先，对金属板的整个面进行镀镍及镀金。接下来，对金属板的外周进行镀锡。然后，实施冲压加工，形成外周部61。
通信设备、卫星以及雷达所使用的高频模块要求高可靠性和长寿命。因而，需要相对于温度、湿度、污染物质以及电磁波对半导体芯片18及电路基板22进行保护。因此，半导体芯片18及电路基板22配置于腔室31的内部，被气密封装。作为气密封装的手段，想到使用焊料而将盖与框架的接触面进行接合的方法。但是，如果利用该方法，则会成为由焊料形成的接合部露出至腔室的构造。此时，焊料的氧化膜以及熔解后的焊料可能会作为异物而侵入至腔室内。在本实施方式中，接合部71通过框架51与盖41的接触面81而与腔室31隔开。因此，通过接触面81抑制从接合部71产生的异物向腔室31的侵入。
并且，在使用焊料进行气密封装的情况下，为了得到稳定的接合，需要将焊料的氧化膜去除。因此，需要下面所示的擦除(scrub)的工序。首先，在由盖和框架夹住焊料的状态下，使焊料熔融。接下来，使用镊子等摇动盖，破坏焊料表面的氧化膜。在这里，如果进行擦除，则熔融的焊料有时会成为粒状，向腔室内部飞溅。另外，焊料氧化膜有可能通过擦除而成为块，向腔室内部落下。在本实施方式中，预先对盖41及框架51实施镀敷，进行加热，由此实现气密封装。因而，无需擦除的工序。因此，能够抑制焊料氧化膜及飞溅的焊料侵入至腔室31内。
由此，在本实施方式中，通过接触面81能够抑制异物向腔室31的侵入。并且，无需擦除的工序，能够抑制焊料氧化膜及飞溅的焊料侵入至腔室31内。由此，实现腔室内部的有无异物的检查的简化。另外，在使用焊料的情况下，为了抑制氧化膜的产生，需要将氧浓度维持为低的水平而进行作业。但是，在本实施方式中，由于不使用焊料，因此能够缓和氧浓度的水平。因而，能够降低制造成本。另外，在本实施方式中，仅通过将盖41覆盖于框架51而进行加热，即可实现气密封装。因而，作业变得容易，能够提高生产性。
实施方式2.
图2是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有在上表面设置了槽90的框架52。盖42具有向槽90的内部弯曲的外周部62。接合部72设置于外周部62的内侧面262与槽90之间。腔室32与接合部72通过接触面82而隔开。在这里，在剖视观察时框架52与盖42在多个面处相接触的情况下，隔着与腔室32相邻的接触面而在与腔室32相反侧形成接合部。即，隔着与腔室32相邻的、框架52与盖42的接触面82，在空间(腔室32)的外侧通过接合部72而使框架52与盖42接合。从接合部72有可能产生以下物质作为异物，即，从镀层产生的氧化膜及由于接合时的加热而熔解的金锡合金70。在本实施方式中，从接合部72产生的异物会被槽90捕捉。因此，在实施方式1所示的效果的基础上，在本实施方式中，还能够抑制框架52的外侧部分由于异物而被污染。
另外，在本实施方式中，通过调整外周部62的长度，能够变更腔室32的容积。对于高频模块来说，如果腔室的共振频率接近于高频模块的使用频带，则有时高频特性会变差。腔室的共振频率依赖于腔室的容积。因此，在本实施方式中，通过调整外周部62的长度，能够实现腔室32的共振频率的变更。因而，通过调整外周部62的长度，能够抑制高频特性变差。
实施方式3.
图3是本实施方式涉及的半导体装置10的剖视图。除了接合部73设置于外周部63的外侧面163与槽90之间以外，本实施方式与实施方式2相同。
在实施方式2中，接合部72与腔室32通过接触面82而隔开。与之相对地，在本实施方式中，接合部73与腔室33通过接触面83和槽90而隔开。从而，与实施方式2相比，能够进一步地抑制异物向腔室33的侵入。另外，与实施方式2相同地，在本实施方式中，通过调整外周部63的长度，能够变更腔室33的容积。从而，能够调整腔室33的共振频率而抑制高频特性变差。
实施方式4.
图4是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有设置了台阶94的框架54。台阶94朝向框架54的上表面而宽度变窄。另外，台阶94在框架54的外侧具有底面194和侧面294。另外，盖44具有向底面194弯曲的外周部64。接合部74设置于外周部64的内侧面264与侧面294之间。腔室34与接合部74通过接触面84而隔开。
在本实施方式中，从接合部74产生的异物会被底面194捕捉。因此，在本实施方式中，在实施方式1所示的效果的基础上，还能够抑制框架54的外侧部分的由异物而造成的污染。另外，与实施方式2相同地，在本实施方式中，通过调整外周部64的长度，能够变更腔室34的容积。从而，能够调整腔室34的共振频率而抑制高频特性变差。
实施方式5.
图5是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有设置了台阶95的框架55。台阶95朝向框架55的上表面而宽度变窄。另外，台阶95在框架55的内侧具有底面195和侧面295。另外，盖45具有向底面195弯曲的外周部65。接合部75设置于外周部65的外侧面165与侧面295之间。腔室35与接合部75通过接触面85而隔开。
在本实施方式中，从接合部75产生的异物会被台阶95捕捉。因此，在实施方式1所示的效果的基础上，还能够抑制由异物造成的框架55的外侧的污染。另外，与实施方式2相同地，在本实施方式中，通过调整外周部65的长度，能够变更腔室35的容积。从而，能够调整腔室35的共振频率而抑制高频特性变差。此外，在本实施方式中，在使外周部65伸长的情况下，能够保持将接合部75与腔室32隔开的接触面85。因此，能够兼顾对异物向腔室35的侵入的抑制和高频特性的提高。
实施方式6.
图6是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有设置了台阶96的框架56。台阶96朝向框架56的上表面而宽度变窄。另外，台阶96在框架56的外侧具有底面196和侧面296。另外，盖46具有向底面196弯曲的外周部66。外周部66具有向外侧朝水平方向进一步弯曲的前端部466。接合部76设置于底面196与前端部466之间。腔室36与接合部76通过接触面86而分隔。
在本实施方式中，前端部466与底面196从上下夹着接合部76。因此，在接合时通过从盖46的上方施加载荷，能够促进金锡合金70的形成。因而，在实施方式1所示的效果的基础上，还能够形成更为良好的金锡合金70，提高气密性。另外，与实施方式2相同地，在本实施方式中，通过调整外周部66的长度，能够变更腔室36的容积。从而，能够调整腔室36的共振频率而抑制高频特性变差。
实施方式7.
图7是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有设置了台阶97的框架57。台阶97朝向框架57的上表面而宽度变窄。另外，台阶97在框架57的内侧具有底面197和侧面297。另外，盖47具有向底面197弯曲的外周部67。外周部67具有向外侧朝水平方向进一步弯曲的前端部467。接合部77设置于底面197与前端部467之间。
在本实施方式中，与实施方式6相同地，通过从盖47的上方施加载荷，能够形成良好的金锡合金70，提高气密性。另外，与实施方式2相同地，在本实施方式中，通过调整外周部67的长度，能够变更腔室37的容积。从而，能够调整腔室37的共振频率而抑制高频特性变差。另外，在本实施方式中，在从盖47的上方施加载荷时，前端部467被按压于侧面297。因此，防止由于外周部67向外侧扩展而引起的腔室37的容积的变化。从而，能够防止由容积的变化而引起的腔室37的共振频率的变动。由此，能够防止由于共振频率的变动而引起高频特性变差。
实施方式8.
图8是本实施方式涉及的半导体装置10的剖视图。在本实施方式中，具有框架58。在框架58的外侧具有朝向上表面而宽度变窄的倾斜面358。盖48具有朝向倾斜面358倾斜的外周部68。接合部78设置于外周部68的内侧面268与倾斜面358之间。腔室38与接合部78通过接触面88而隔开。
在本实施方式中，与实施方式6相同地，通过从盖48的上方施加载荷，能够形成良好的金锡合金70。因而，在实施方式1所示的效果的基础上，还能够提高气密性。另外，通过沿倾斜面358形成接合部78，从而与其他实施方式相比，能够将接合部78设置得宽。从而，能够提高气密性。

Claims (9)

1.一种半导体装置，其特征在于，具有：
安装部，其具有用于搭载半导体芯片的芯片搭载区域；
框架，其以包围所述芯片搭载区域的方式设置于所述安装部；
盖，其以覆盖由所述芯片搭载区域及所述框架包围的空间的方式，与所述框架接触地配置；以及
接合部，其在所述框架与所述盖的接触面的外侧，将所述框架和所述盖进行接合。
2.根据权利要求1所述的半导体装置，其特征在于，
所述接合部由金锡合金形成。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述盖具有在所述框架的外侧向所述安装部弯曲的外周部，
所述接合部形成于所述框架与所述外周部的内侧面之间。
4.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架在上表面设置槽，
所述盖具有向所述槽的内部弯曲的外周部，
所述接合部设置于所述外周部的内侧面与所述槽之间。
5.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架在上表面设置槽，
所述盖具有向所述槽的内部弯曲的外周部，
所述接合部设置于所述外周部的外侧面与所述槽之间。
6.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架具有朝向上表面而宽度变窄、在外侧具有底面和侧面的台阶，
所述盖具有向所述底面弯曲的外周部，
所述接合部设置于所述侧面与所述外周部的内侧面之间。
7.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架具有朝向上表面而宽度变窄、在内侧具有底面和侧面的台阶，
所述盖具有向所述底面弯曲的外周部，
所述接合部设置于所述侧面与所述外周部的外侧面之间。
8.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架具有朝向上表面而宽度变窄、在外侧具有底面和侧面的台阶，
所述盖具有向所述底面弯曲的外周部，
所述外周部具有向外侧朝水平方向进一步弯曲的前端部，
所述接合部设置于所述底面与所述前端部之间。
9.根据权利要求1或2所述的半导体装置，其特征在于，
所述框架具有朝向上表面而宽度变窄的倾斜面，
所述盖具有朝向所述倾斜面倾斜的外周部，
所述接合部设置于所述外周部的内侧面与所述倾斜面之间。
CN201610960956.5A 2015-10-29 2016-10-28 半导体装置 Active CN107039355B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-212974 2015-10-29
JP2015212974A JP6477421B2 (ja) 2015-10-29 2015-10-29 半導体装置

Publications (2)

Publication Number Publication Date
CN107039355A true CN107039355A (zh) 2017-08-11
CN107039355B CN107039355B (zh) 2020-05-15

Family

ID=58546260

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610960956.5A Active CN107039355B (zh) 2015-10-29 2016-10-28 半导体装置

Country Status (4)

Country Link
US (1) US10211116B2 (zh)
JP (1) JP6477421B2 (zh)
CN (1) CN107039355B (zh)
DE (1) DE102016219274A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086404A (zh) * 2020-09-19 2020-12-15 广州华创精密科技有限公司 高密度线路芯片封装结构及其制作方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9859179B2 (en) * 2013-09-27 2018-01-02 Kyocera Corporation Lid body, package, and electronic apparatus
KR102191728B1 (ko) * 2018-10-23 2020-12-16 주식회사 코스텍시스 플랫 노리드 패키지
WO2023199799A1 (ja) * 2022-04-12 2023-10-19 ソニーセミコンダクタソリューションズ株式会社 半導体装置および電子機器

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4798946A (en) * 1987-04-09 1989-01-17 Mitsubishi Denki Kabushiki Kaisha Plastic package for an IC card
US5311402A (en) * 1992-02-14 1994-05-10 Nec Corporation Semiconductor device package having locating mechanism for properly positioning semiconductor device within package
JPH06163729A (ja) * 1992-11-20 1994-06-10 Toshiba Corp 半導体装置のシール構造
US5905301A (en) * 1996-02-01 1999-05-18 Nec Corporation Mold package for sealing a chip
JP2001176991A (ja) * 1999-12-21 2001-06-29 Kyocera Corp 電子部品装置
CN1394359A (zh) * 2000-11-27 2003-01-29 田中贵金属工业株式会社 电子元件的气密密封方法
JP2004088036A (ja) * 2002-06-27 2004-03-18 Kyocera Corp 電子装置及びその製造方法
CN102891152A (zh) * 2011-06-10 2013-01-23 新光电气工业株式会社 半导体封装体
US20130154085A1 (en) * 2011-12-14 2013-06-20 Daesik Choi Integrated circuit packaging system with heat conduction and method of manufacture thereof

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02111055A (ja) * 1988-10-20 1990-04-24 Sumitomo Electric Ind Ltd 半導体封止パッケージ
FR2683947B1 (fr) * 1991-11-18 1994-02-18 Sgs Thomson Microelectronics Sa Diode de protection monolithique basse tension a faible capacite.
JP2894214B2 (ja) * 1994-07-25 1999-05-24 日本電気株式会社 半導体装置
JPH10321746A (ja) 1997-05-16 1998-12-04 Murata Mfg Co Ltd 電子部品の実装構造
US6321444B1 (en) * 2000-04-11 2001-11-27 Japan Radio Co., Ltd. Method of making surface acoustic wave device
US6218730B1 (en) 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
JP2001044310A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその搭載方法
JP2002110833A (ja) 2000-10-04 2002-04-12 Sanyo Electric Co Ltd 半導体装置およびその製造方法
JP2002334944A (ja) 2001-05-08 2002-11-22 Nec Corp 中空構造パッケージ
DE10340974A1 (de) * 2003-09-05 2005-03-24 Robert Bosch Gmbh Steuergeräteeinheit und Verfahren zur Hestellung derselben
US20060179792A1 (en) * 2005-02-11 2006-08-17 Steve Shaw Modular stone surfacing system with field adjustable components for different applications
JP4791742B2 (ja) 2005-03-25 2011-10-12 吉川工業株式会社 電子部品のはんだ接合方法
CN101622706B (zh) 2007-02-26 2011-05-18 株式会社新王材料 气密密封用盖、电子部件容纳用封装和电子部件容纳用封装的制造方法
US8232615B2 (en) * 2010-02-23 2012-07-31 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Packaged device with acoustic transducer and amplifier
JP5368377B2 (ja) 2010-06-02 2013-12-18 三菱電機株式会社 電子部品パッケージおよびその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4798946A (en) * 1987-04-09 1989-01-17 Mitsubishi Denki Kabushiki Kaisha Plastic package for an IC card
US5311402A (en) * 1992-02-14 1994-05-10 Nec Corporation Semiconductor device package having locating mechanism for properly positioning semiconductor device within package
JPH06163729A (ja) * 1992-11-20 1994-06-10 Toshiba Corp 半導体装置のシール構造
US5905301A (en) * 1996-02-01 1999-05-18 Nec Corporation Mold package for sealing a chip
JP2001176991A (ja) * 1999-12-21 2001-06-29 Kyocera Corp 電子部品装置
CN1394359A (zh) * 2000-11-27 2003-01-29 田中贵金属工业株式会社 电子元件的气密密封方法
JP2004088036A (ja) * 2002-06-27 2004-03-18 Kyocera Corp 電子装置及びその製造方法
CN102891152A (zh) * 2011-06-10 2013-01-23 新光电气工业株式会社 半导体封装体
US20130154085A1 (en) * 2011-12-14 2013-06-20 Daesik Choi Integrated circuit packaging system with heat conduction and method of manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086404A (zh) * 2020-09-19 2020-12-15 广州华创精密科技有限公司 高密度线路芯片封装结构及其制作方法
CN112086404B (zh) * 2020-09-19 2022-07-05 广州华创精密科技有限公司 高密度线路芯片封装结构及其制作方法

Also Published As

Publication number Publication date
US20170125316A1 (en) 2017-05-04
DE102016219274A1 (de) 2017-05-04
US10211116B2 (en) 2019-02-19
JP6477421B2 (ja) 2019-03-06
JP2017085000A (ja) 2017-05-18
CN107039355B (zh) 2020-05-15

Similar Documents

Publication Publication Date Title
CN107039355A (zh) 半导体装置
US20150262960A1 (en) Power Semiconductor Package with Conductive Clips
JP5981660B2 (ja) 電子部品収納用パッケージおよび電子装置
US9041190B2 (en) Semiconductor package
US10373897B2 (en) Semiconductor devices with improved thermal and electrical performance
JP5776701B2 (ja) 半導体装置、および、半導体装置の製造方法
CN104934404B (zh) 半导体装置及其制造方法
JP6243510B2 (ja) 電子部品収納用パッケージおよび電子装置
US10122366B2 (en) Crystal oscillation device
US20110038132A1 (en) Microstructure Apparatus, Manufacturing Method Thereof, and Sealing Substrate
JP2008294587A (ja) 表面実装用の水晶発振器
US11114386B2 (en) Semiconductor device and method of manufacturing the same
JP2007312108A (ja) 表面弾性波装置
US9578770B2 (en) Package for electronic device
JP6030371B2 (ja) 素子収納用パッケージおよび実装構造体
US20110186979A1 (en) Semiconductor package and high-frequency semiconductor device
JP2014135414A (ja) 半導体素子収納用パッケージ
JP6239970B2 (ja) Ｔｏ−ｃａｎ型パッケージ用ヘッダーおよび半導体装置
JP2013004754A (ja) 半導体パッケージ及びその製造方法
CN110337718A (zh) 绝缘基体、半导体封装以及半导体装置
JP5642559B2 (ja) 電子部品モジュール
JP2017228684A (ja) 高周波半導体用パッケージ
JP6717519B2 (ja) 半導体装置の製造方法
JP3638901B2 (ja) 半導体装置用パッケージ
CN111316428A (zh) 半导体装置以及半导体装置的制造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant