CN106935556A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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CN106935556A
CN106935556A CN201611144425.5A CN201611144425A CN106935556A CN 106935556 A CN106935556 A CN 106935556A CN 201611144425 A CN201611144425 A CN 201611144425A CN 106935556 A CN106935556 A CN 106935556A
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semiconductor package
semiconductor chip
layer
chip
package part
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权容焕
柳承官
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

公开了一种半导体封装件。所述半导体封装件包括：堆叠结构；成型层，设置在堆叠结构的至少一个侧壁上；再分布线，电连接到堆叠结构；以及外部端子，电连接到再分布线。堆叠结构包括半导体芯片，半导体芯片具有有源表面和与有源表面相对的非有源表面。虚设基底设置在半导体芯片的非有源表面上。粘合层设置在虚设基底和半导体芯片之间。成型层包括与再分布线相邻的顶表面和与顶表面相对的底表面。通过成型层的底表面暴露虚设基底。

Description

半导体封装件及其制造方法
本专利申请要求于2015年12月31日提交到韩国知识产权局的第10-2015-0191285号韩国专利申请的优先权，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本发明构思的示例性实施例涉及一种半导体封装件，更具体地，涉及一种制造所述半导体封装件的方法。
背景技术
在制造半导体芯片或半导体封装件的工艺中可以包括研磨半导体芯片的工艺。在研磨工艺期间，在半导体芯片上会出现划痕或裂纹并且/或者半导体芯片会被污染物污染。因此，会减少半导体芯片的良率。
发明内容
本发明构思的示例性实施例可以提供一种包括不被损害或污染的半导体芯片的半导体封装件以及制造半导体封装件的方法。
本发明构思的示例性实施例可以提供一种具有提高的半导体封装件的良率的半导体封装件以及制造半导体封装件的方法。
本发明构思的示例性实施例可以提供一种具有增强的电特性和/或机械特性的半导体封装件以及制造半导体封装件的方法。
根据本发明的示例性实施例，半导体封装件包括堆叠结构、设置在堆叠结构的至少一个侧壁上的成型层、电连接到堆叠结构的再分布线以及电连接到再分布线的外部端子。堆叠结构包括半导体芯片，所述半导体芯片具有有源表面和与有源表面相对的非有源表面。粘合层设置在半导体芯片的非有源表面上。虚设基底设置在粘合层上。成型层包括与再分布线相邻的顶表面以及与顶表面相对的底表面。通过成型层的底表面暴露虚设基底。
根据本发明的示例性实施例，半导体封装件包括堆叠结构，所述堆叠结构包括半导体芯片、设置在半导体芯片下方的虚设基底以及设置在虚设基底和半导体芯片之间的金属粘合层。成型层设置在堆叠结构的第一侧壁和第二侧壁上。成型层具有顶表面以及与顶表面相对的底表面。外部端子电连接到半导体芯片。外部端子设置在成型层的顶表面上。半导体芯片包括有源表面和与有源表面相对的非有源表面，其中，在有源表面上设置有电连接到外部端子的电路层。虚设基底设置在半导体芯片的非有源表面上。通过成型层的底表面暴露虚设基底。
根据本发明的示例性实施例，半导体封装件包括半导体芯片，所述半导体芯片包括顶表面、设置在顶表面上的电路层以及与顶表面相对的底表面。粘合层覆盖半导体芯片的底表面。成型层设置在半导体芯片和粘合层的至少一个侧壁上。再分布线电连接到半导体芯片的电路层上。再分布线设置在半导体芯片的顶表面上并且延伸到成型层上。外部端子电连接到再分布线。
附图说明
通过参照附图详细地描述发明构思的示例性实施例，发明构思的以上和其它特征将变得更加明显，在附图中：
图1A是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。
图1B是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。
图1C是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。
图1D是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。
图2A、图2C、图2D、图2E、图2F、图2G、图2H、图2I和图2J是示出根据本发明构思的一些示例性实施例的制造半导体封装件的方法的剖视图。
图2B是示出图2A的另一个实施例的剖视图。
图2K是示出图2J的另一个实施例的剖视图。
图3A、图3B、图3C、图3D、图3E和图3F是示出根据本发明构思的一些示例性实施例的制造半导体封装件的方法的剖视图。
图3G是示出图3F的另一个实施例的剖视图。
具体实施方式
图1A是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。
参照图1A，半导体封装件1可以包括包含半导体芯片101的堆叠结构10、电连接到半导体芯片101的再分布线121、电连接到再分布线121的外部端子125以及设置在堆叠结构10的至少一个侧壁上的成型层105。在本发明构思的一些示例性实施例中，半导体封装件1不需要包括诸如印刷电路板(PCB)的封装基底。
半导体芯片101可以具有有源表面101a。电路层104可以设置在有源表面101a上。半导体芯片101可以包括与有源表面101a相对的非有源表面101b。有源表面101a可以包括电连接到电路层104的一个或更多个芯片焊盘103。在本发明构思的一些示例性实施例中，芯片焊盘103可以设置在半导体芯片101的有源表面101a的边缘区域中。在本发明构思的一些示例性实施例中，至少一个芯片焊盘103可以设置在半导体芯片101的有源表面101a的中心区域中。在本发明构思的一些示例性实施例中，芯片焊盘103可以设置在半导体芯片101的有源表面101a的基本上整个区域上。半导体芯片101的有源表面101a可以与成型层105的顶表面105a共平面。例如，半导体芯片101可以是存储芯片、逻辑芯片或存储芯片和逻辑芯片的组合。
堆叠结构10可以包括设置在半导体芯片101的非有源表面101b上的虚设基底113。粘合层111可以设置在虚设基底113和非有源表面101b之间。粘合层111和虚设基底113中的至少一个可以包括导体材料、非导体材料或半导体材料。例如，粘合层111可以包括金属膏(例如，铜膏)，虚设基底113可以包括硅基底。可以通过成型层105的底表面105c暴露虚设基底113。堆叠结构10的厚度T2可以等于或相似于成型层105的厚度T3。
金属粘合层111可以充当散热层，因此从半导体芯片101产生的热可以有效地消散。如下面参照图2I更加详细地描述的，虚设基底113可以减少或防止在制造工艺期间可能出现在半导体芯片101中的划痕或裂纹。虚设基底113可以减少或防止半导体封装件1的翘曲。虚设基底113和半导体芯片101可以具有基本上相同的尺寸或者可以具有彼此不同的尺寸。例如，虚设基底113的尺寸S1(例如，宽度)可以等于或相似于半导体芯片101的尺寸S2(例如，宽度)。虚设基底113的厚度X1可以等于半导体芯片101的厚度X2或者与半导体芯片101的厚度X2不同。
再分布线121可以电连接到芯片焊盘103。再分布线121可以越过半导体芯片101的侧壁延伸到成型层105上。外部端子125可以连接到再分布线121的端部。半导体封装件1可以具有扇出结构，在扇出结构中，外部端子125围绕半导体芯片101布置。保护层123可以覆盖再分布线121、半导体芯片101的有源表面101a以及成型层105的顶表面105a。
图1B、图1C和图1D是示出根据本发明构思的一些示例性实施例的半导体封装件的剖视图。可以省略或简要地提到如以上参照图1A描述的在本发明构思的示例性实施例中的相同或相似的元件和/或技术特征的描述。可以描述以上参照图1A描述的本发明构思的示例性实施例和参照图1B、1C和1D描述的本发明构思的示例性实施例之间的不同。
参照图1B，半导体封装件2可以包括包含半导体芯片101和粘合层111的堆叠结构10。半导体封装件2不需要包括虚设基底113。可以通过成型层105的底表面105d暴露粘合层111。当粘合层111包括金属材料时，粘合层111可以充当散热层并且可以充当基底，这可以减少或消除半导体封装件2的翘曲。
参照图1C，半导体封装件3可以包括其尺寸S1大于半导体芯片101的尺寸S2的虚设基底113。可以通过成型层105的底表面105c暴露虚设基底113。虚设基底113的侧壁不需要达到成型层105的侧壁。例如，可以通过成型层105覆盖虚设基底113的侧壁。
参照图1D，半导体封装件4可以包括其尺寸S1小于半导体芯片101的尺寸S2的虚设基底113。虚设基底113的尺寸S1可以小于半导体芯片101的尺寸S2，因此可以减小或消除半导体封装件4的翘曲。
图2A、图2C、图2D、图2E、图2F、图2G、图2H、图2I和图2J是示出根据本发明构思的一些示例性实施例的制造半导体封装件的方法的剖视图。图2B是示出图2A的另一个实施例的剖视图。图2K是示出图2J的另一个实施例的剖视图。
参照图2A，可以打薄具有彼此相对的第一表面102a和第二表面102b的晶片102。晶片102可以是例如包括电路层104和电连接到电路层104的芯片焊盘103的硅晶片。可以对晶片102的第二表面102b执行研磨工艺、化学机械抛光工艺(CMP)或蚀刻工艺以打薄晶片102。可以通过打薄工艺暴露比第二表面102b与靠近第一表面102a的第三表面102c。
可以通过粘合层72(例如，固晶膜(DAF))将支撑基底70结合到晶片102的第一表面102a。支撑基底70可以支撑晶片102并且可以在打薄工艺期间保护电路层104。例如，支撑基底70可以是尺寸等于或相似于晶片102的尺寸的硅晶片或玻璃基底。在本发明构思的一些示例性实施例中，可以在晶片102的第一表面102a上设置保护膜74。保护膜74可以保护电路层104免受在打薄工艺期间会引起的损害或污染。
参照图2C，采用设置在虚设基底113和第三表面102c之间的粘合层111，可以将虚设基底113结合到晶片102的第三表面102c。粘合层111和虚设基底113中的至少一个可以包括导体材料、非导体材料或半导体材料。例如，粘合层111可以包括金属膏(例如，铜膏)，虚设基底113可以包括硅晶片。虚设基底113的尺寸(例如，直径)可以等于或相似于晶片102的尺寸(例如，直径)。将虚设基底113结合到晶片102之后可以从晶片102去除支撑基底70和粘合层72。
参照图2D，可以沿着划线90切割晶片102，其中，虚设基底113结合到晶片102。在本发明构思的一些示例性实施例中，当执行切割工艺时，可以在晶片102的第一表面102a上设置保护膜76。保护膜76可以保护电路层104免受在切割工艺期间会引起的损害或污染。在本发明构思的一些示例性实施例中，可以使用切割设备(例如，刀片95)执行切割工艺。在本发明构思的一些示例性实施例中，可以通过激光切割工艺切割晶片102。
参照图2E，可以通过切割工艺将晶片102和虚设基底113分成多个堆叠结构10。每个堆叠结构10可以包括半导体芯片101，其中，使用粘合层111将虚设基底113结合到半导体芯片101。堆叠结构10的虚设基底113可以是虚设基底113的通过切割工艺彼此分开的部分中的相应的部分。在每个堆叠结构10中，虚设基底113的尺寸S1(例如，宽度)可以等于或相似于半导体芯片101的尺寸S2(例如，宽度)。虚设基底113的厚度X1可以基本上等于半导体芯片101的厚度X2或者与半导体芯片101的厚度X2不同。
半导体芯片101可以包括对应于晶片102的第一表面102a的有源表面101a以及对应于晶片102的第三表面102c的非有源表面101b。例如，半导体芯片101可以是存储芯片、逻辑芯片或存储芯片和逻辑芯片的组合。
参照图2F，可以通过诸如固晶膜(DAF)的粘合层82将多个堆叠结构10结合到支撑基底80的顶表面80a。支撑基底80可以包括硅晶片或玻璃基底。可以沿着支撑基底80的顶表面80a布置堆叠结构10，堆叠结构10可以彼此分隔开。可以在支撑基底80上设置堆叠结构10。半导体芯片101的有源表面101a可以面向支撑基底80。将堆叠结构10结合到支撑基底80之后，可以在支撑基底80上形成覆盖堆叠结构10的成型层105。成型层105可以包括例如环氧树脂塑封料(EMC)。
参照图2G，可以从成型层105去除支撑基底80和粘合层82。因此，可以暴露堆叠结构10。例如，可以暴露半导体芯片101的有源表面101a，因此可以暴露电路层104和芯片焊盘103。半导体芯片101的有源表面101a可以与成型层105的顶表面105a共平面。成型层105的厚度T1可以大于堆叠结构10的厚度T2。
参照图2H，再分布线121可以连接到芯片焊盘103。可以通过保护层123覆盖再分布线121，其中，保护层123覆盖半导体芯片101的有源表面101a以及成型层105。在本发明构思的一些示例性实施例中，保护层123可以包括诸如聚酰亚胺(PI)、聚苯并噁唑(PBO)或苯并环丁烯(BCB)的聚合物。在本发明构思的一些示例性实施例中，保护层123可以包括氧化硅层或氮化硅层。保护层123可以具有多层结构或单层结构。外部端子(例如，焊球)125可以电连接到再分布线121。再分布线121可以延伸越过半导体芯片101的侧壁。外部端子125可以与再分布线121的延伸越过半导体芯片101的侧壁的端部相邻。可以在半导体芯片101的外部设置外部端子125。
参照图2I，可以对成型层105的底表面105b执行背面研磨工艺。在本发明构思的一些示例性实施例中，可以将保护外部端子125的保护膜78结合到保护层123。可以通过成型层105的底表面105c使虚设基底113暴露，其中，可以通过背面研磨工艺使底表面105c凹进。在背面研磨工艺期间，在虚设基底113中以及/或在包括于成型层105中的填充件中会出现划痕或裂纹。然而，由于不暴露半导体芯片101，所以在半导体芯片101中不会出现划痕或裂纹。即使在虚设基底113的划痕或裂纹中会出现污染物，也可以保护半导体芯片101免受污染或损害。接地成型层105的厚度T3可以等于或近似于堆叠结构10的厚度T2。
参照图2J，可以沿划线92切割成型层105。在本发明构思的一些示例性实施例中，可以使用切割设备(例如，刀片95)执行切割工艺。可选择地，可以通过激光切割工艺切割成型层105。在本发明构思的一些示例性实施例中，当执行切割工艺时，保护膜79可以粘附到保护层123并且可以保护半导体芯片101和/或外部端子125免受在切割工艺期间会导致的损害或污染。可选择地，在对成型层105执行切割工艺期间不需要去除而是可以使用在背面研磨工艺中使用的保护膜78。可以通过成型层105的切割工艺制造半导体封装件1。
参照图2K，在对成型层105的底表面105b执行背面研磨工艺期间，可以通过过度研磨去除虚设基底113的至少一部分。在本发明构思的一些示例性实施例中，可以通过过度研磨基本上完全去除虚设基底113，因此可以通过成型层105的凹进的底表面105d暴露粘合层111。粘合层111可以是金属粘合层。当执行过度研磨时，金属粘合层111可以充当裂纹停止件或研磨停止件。执行过度研磨之后，可以切割成型层105以制造半导体封装件2。
图3A、图3B、图3C、图3D、图3E和图3F是示出根据本发明构思的一些示例性实施例的制造半导体封装件的方法的剖视图。图3G是示出图3F的另一个实施例的剖视图。
参照图3A，可以设置晶片102。晶片102可以包括第一表面102a、与第一表面102a相对的第二表面102b、电路层104以及芯片焊盘103。可以对晶片102的第二表面102b执行研磨工艺、CMP工艺或蚀刻工艺以打薄晶片102。然后，可以沿划线90切割晶片102。可以使用诸如刀片95的切割设备执行晶片102的切割工艺。在采用设置在支撑基底70和第一表面102a之间的粘合层72而将支撑基底70结合到晶片102的第一表面102a的状态下，可以执行打薄晶片102的工艺。在将保护膜74结合到晶片102的第一表面102a的状态下可以执行打薄晶片102的工艺。可以通过打薄晶片102的工艺暴露晶片102的第三表面102c。第三表面102c和第一表面102a之间的距离可以小于第二表面102b和第一表面102a之间的距离。在将保护电路层104的保护膜76结合到晶片102的第一表面102a的状态下，可以执行晶片102的切割工艺。
参照图3B，通过切割工艺可以将晶片102分成多个半导体芯片101。半导体芯片101可以包括有源表面101a以及与有源表面101a相对的非有源表面101b。例如，半导体芯片101可以是存储芯片、逻辑芯片或存储芯片和逻辑芯片的组合。
参照图3C，通过诸如固晶膜(DAF)的粘合层82可以将多个半导体芯片101结合到支撑基底80(例如，硅晶片或玻璃基底)。可以在支撑基底80上设置半导体芯片101，有源表面101a面向支撑基底80。采用设置在虚设基底113和非有源表面101b之间的粘合层111，可以将虚设基底113结合到半导体芯片101中的每个的非有源表面101b。因此，可以在支撑基底80的顶表面80a上设置彼此分隔开的多个堆叠结构10。可以在支撑基底80上设置环氧树脂塑封料(EMC)以形成使堆叠结构10成型的成型层105。粘合层111可以包括金属膏(例如，铜膏)，虚设基底113可以包括硅基底。虚设基底113的尺寸S1(例如，宽度)可以大于半导体芯片101的尺寸S2(例如，宽度)。
参照图3D，可以从使堆叠结构10成型的成型层105去除支撑基底80和粘合层82。通过去除支撑基底80和粘合层82可以暴露堆叠结构10。例如，可以暴露半导体芯片101的有源表面101a，因此可以暴露电路层104和芯片焊盘103。半导体芯片101的有源表面101a可以与成型层105的顶表面105a共平面。成型层105的厚度T1可以等于或大于堆叠结构10的厚度T2。虚设基底113的厚度X1可以等于半导体芯片101的厚度X2或者与半导体芯片101的厚度X2不同。
参照图3E，可以形成连接到芯片焊盘103的再分布线121，可以形成覆盖再分布线121的保护层123。外部端子(例如，焊球)125可以形成为电连接到再分布线121。可以在半导体芯片101外部设置外部端子125。
参照图3F，可以对成型层105的底表面105b执行背面研磨工艺，可以沿划线92切割成型层105。可以通过背面研磨工艺和切割工艺制造半导体封装件3。当执行背面研磨工艺和切割工艺中的至少一种时，可以将保护膜78粘附到保护层123。
参照图3G，虚设基底113的尺寸S1可以小于堆叠结构10中半导体芯片101的尺寸S2。在这种情况下，可以执行以上参照图3F更详细地描述的背面研磨工艺和切割工艺以制造半导体封装件4。
根据本发明构思的一些示例性实施例，可以将虚设基底结合到半导体芯片，可以减少或消除半导体芯片中的划痕或裂纹的出现。另外，虚设基底可以减少或消除半导体封装件的翘曲。
虽然已经参照发明构思的示例性实施例部分地示出和描述了发明构思，但是本领域普通技术人员将理解的是，在不脱离发明构思的精神和范围的情况下，可以做出形式和细节方面的各种改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
堆叠结构；
成型层，设置在所述堆叠结构的至少一个侧壁上；
再分布线，电连接到所述堆叠结构；以及
外部端子，电连接到所述再分布线，
其中，所述堆叠结构包括：半导体芯片，具有有源表面和与所述有源表面相对的非有源表面；粘合层，设置在所述半导体芯片的所述非有源表面上；以及虚设基底，设置在所述粘合层上，
其中，所述成型层包括与所述再分布线相邻的顶表面以及与所述顶表面相对的底表面，
其中，通过所述成型层的所述底表面暴露所述虚设基底。
2.根据权利要求1所述的半导体封装件，其中，所述粘合层包括金属膏。
3.根据权利要求1所述的半导体封装件，其中，所述再分布线设置在所述半导体芯片的所述有源表面上并且越过所述半导体芯片的侧壁延伸到所述成型层上。
4.根据权利要求1所述的半导体封装件，其中，所述成型层围绕所述半导体芯片的侧壁，
其中，所述外部端子设置在围绕所述半导体芯片的所述侧壁的所述成型层的所述顶表面上。
5.根据权利要求1所述的半导体封装件，其中，所述半导体封装件还包括设置在所述再分布线上并且覆盖所述半导体芯片的所述有源表面和所述成型层的所述顶表面的保护层。
6.根据权利要求1所述的半导体封装件，其中，所述虚设基底的尺寸基本上等于所述半导体芯片的尺寸。
7.根据权利要求1所述的半导体封装件，其中，所述虚设基底的尺寸大于或小于所述半导体芯片的尺寸。
8.根据权利要求1所述的半导体封装件，其中，所述半导体芯片的所述有源表面基本上与所述成型层的所述顶表面共平面。
9.一种半导体封装件，所述半导体封装件包括：
堆叠结构，包括：半导体芯片；虚设基底，设置在所述半导体芯片下方；以及金属粘合层，设置在所述虚设基底和所述半导体芯片之间；
成型层，设置在所述堆叠结构的第一侧壁和第二侧壁上，所述成型层具有顶表面以及与所述顶表面相对的底表面；以及
外部端子，电连接到所述半导体芯片，所述外部端子设置在所述成型层的所述顶表面上，
其中，所述半导体芯片包括：有源表面，在有源表面上设置有电连接到所述外部端子的电路层；非有源表面，与所述有源表面相对，
其中，所述虚设基底设置在所述半导体芯片的所述非有源表面上，其中，通过所述成型层的所述底表面暴露所述虚设基底。
10.根据权利要求9所述的半导体封装件，所述半导体封装件还包括保护层，所述保护层覆盖所述半导体芯片的所述有源表面和所述成型层的所述顶表面。
11.根据权利要求10所述的半导体封装件，所述半导体封装件还包括再分布线，所述再分布线将所述外部端子电连接到所述半导体芯片的所述电路层，
其中，所述保护层围绕所述再分布线。
12.根据权利要求11所述的半导体封装件，其中，所述半导体芯片还包括电连接到所述电路层的芯片焊盘，
其中，所述再分布线连接到所述芯片焊盘。
13.根据权利要求9所述的半导体封装件，其中，所述堆叠结构的厚度基本上等于所述成型层的厚度。
14.根据权利要求9所述的半导体封装件，其中，所述金属粘合层包括铜膏。
15.一种半导体封装件，所述半导体封装件包括：
半导体芯片，包括顶表面、设置在所述顶表面上的电路层以及与所述顶表面相对的底表面；
粘合层，覆盖所述半导体芯片的所述底表面；
成型层，设置在所述半导体芯片和所述粘合层的至少一个侧壁上；
再分布线，电连接到所述半导体芯片的所述电路层上，所述再分布线设置在所述半导体芯片的所述顶表面上并且延伸到所述成型层上；以及
外部端子，电连接到所述再分布线。
16.一种半导体封装件，所述半导体封装件包括：
虚设基底；
成型层，设置在所述虚设基底的第一侧表面和第二侧表面上，其中，所述成型层设置在所述虚设基底的顶表面的一部分上；
堆叠结构，包括设置在所述虚设基底上的半导体芯片，其中，所述成型层设置在所述堆叠结构的第一侧表面和第二侧表面上；以及
再分布线，设置在所述半导体芯片上并且电连接到所述半导体芯片。
17.根据权利要求16所述的半导体封装件，所述半导体封装件还包括设置在所述虚设基底和所述堆叠结构之间的粘合层。
18.根据权利要求16所述的半导体封装件，所述半导体封装件还包括电连接到所述再分布线的外部端子。
19.根据权利要求18所述的半导体封装件，其中，所述外部端子设置在所述成型层上方。
20.根据权利要求16所述的半导体封装件，所述半导体封装件还包括设置在所述再分布线和所述半导体芯片之间的芯片焊盘。
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