CN106571296A - 晶圆的形成方法 - Google Patents

晶圆的形成方法 Download PDF

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CN106571296A
CN106571296A CN201510659200.2A CN201510659200A CN106571296A CN 106571296 A CN106571296 A CN 106571296A CN 201510659200 A CN201510659200 A CN 201510659200A CN 106571296 A CN106571296 A CN 106571296A
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forming method
wafer
deuterium
silicon substrate
thermal annealing
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肖德元
张汝京
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Zing Semiconductor Corp
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Priority to US15/178,041 priority patent/US20170103900A1/en
Priority to JP2016123427A priority patent/JP6174761B2/ja
Priority to DE102016115524.1A priority patent/DE102016115524A1/de
Priority to KR1020160122782A priority patent/KR101888250B1/ko
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02598Microstructure monocrystalline

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  • Inorganic Chemistry (AREA)
  • Mechanical Engineering (AREA)
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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

本发明提出了一种晶圆的形成方法,在形成硅衬底后,对硅衬底在氘气下进行快速热退火处理,形成钝化层,钝化层能够使硅衬底表面的粗糙度降低,在后续栅氧化层的形成或界面的形成时,氘能够扩散出,并与界面处等悬空键进行结合,形成较为稳定的结构,从而避免载流子的穿透,提高器件的性能。

Description

晶圆的形成方法
技术领域
本发明涉及半导体制造领域,尤其涉及一种晶圆的形成方法。
背景技术
单晶硅是制造半导体电子元件时的最初材料,其通常由所谓Czochralski(直拉法,CZ)方法制备而成。
随着现代微电子器件的尺寸不断收缩,对硅衬底质量的挑战逐渐增大。而硅衬底的质量取决于生长在其内部微小缺陷(microdefects)的大小和分布情况。在使用直拉法或者悬浮区法(Float Zone)形成的硅衬底的过程中,大多数微小缺陷会聚集硅内部空隙(silicon-vacancies)或者填在间隙之中。
使用氢气形成钝化层在半导体器件制造领域已经是被广为所知并且常用的技术手段。在氢钝化过程中,能够去除缺陷对半导体器件的影响。例如,该种缺陷被描述为复合或者半导体器件中心的活性成分。这些中心是由悬空键造成,该悬空键能够去除电荷载体或者引入不必要的电荷载体,这部分主要取决于偏压。而悬空键主要发生在表面或器件的界面,同时其也能够发生在空缺、微孔隙等处,其也与杂质相关。
在半导体制造领域中,还存在由热载流子引起的器件性能下降的问题。该问题在小尺寸器件及高压器件中尤其重要。当使用高压器件时,通道内的载流子具有较大的能量能够穿透进入绝缘层,从而使器件的性能变差。
由于氢气形成的钝化层不太稳定,在与悬空键进行键合后,极易被破坏,从而使悬空键再次暴露出,从而影响器件的性能。
发明内容
本发明的目的在于提供一种晶圆的形成方法,能够降低晶圆表面的粗糙度,并且能够减少后续器件界面层的悬空键,提高器件的性能。
为了实现上述目的,本发明提出了一种晶圆的形成方法,包括步骤:
提供硅衬底;
对所述硅衬底进行快速热退火处理,形成钝化层,所述快速热退火使用的气体包括氘气。
进一步的,在所述的晶圆的形成方法中,所述快速热退火的温度范围为1200℃~1380℃。
进一步的,在所述的晶圆的形成方法中,所述快速热退火使用的气体为氘气和氢气的混合气体。
进一步的,在所述的晶圆的形成方法中,所述氘气占的比例范围为1%~100%。
进一步的,在所述的晶圆的形成方法中,所述快速热退火使用的气体为氘气和氧气的混合气体。
进一步的,在所述的晶圆的形成方法中,所述氘气占的比例范围为1%~100%。
进一步的,在所述的晶圆的形成方法中,所述快速热退火使用的气体为氘气。
进一步的,在所述的晶圆的形成方法中,所述硅衬底的形成方法包括:
形成硅铸块;
对所述硅铸块依次进行切薄、表面磨削、抛光、边缘处理及清洗处理,形成硅衬底。
进一步的,在所述的晶圆的形成方法中,所述硅衬底为单晶硅。
进一步的,在所述的晶圆的形成方法中,所述硅衬底采用直拉法形成。
与现有技术相比,本发明的有益效果主要体现在:在形成硅衬底后,对硅衬底在氘气下进行快速热退火处理,形成钝化层,钝化层能够使硅衬底表面的粗糙度降低,在后续栅氧化层的形成或界面的形成时,氘能够扩散出,并与界面处等悬空键进行结合,形成较为稳定的结构,从而避免载流子的穿透,提高器件的性能。
附图说明
图1为本发明一实施例中晶圆的形成方法的流程图。
具体实施方式
下面将结合示意图对本发明的晶圆的形成方法进行更详细的描述,其中表示了本发明的优选实施例,应该理解本领域技术人员可以修改在此描述的本发明,而仍然实现本发明的有利效果。因此,下列描述应当被理解为对于本领域技术人员的广泛知道,而并不作为对本发明的限制。
为了清楚,不描述实际实施例的全部特征。在下列描述中,不详细描述公知的功能和结构,因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中,必须做出大量实施细节以实现开发者的特定目标,例如按照有关系统或有关商业的限制,由一个实施例改变为另一个实施例。另外,应当认为这种开发工作可能是复杂和耗费时间的,但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1,在本实施例中,提出了一种晶圆的形成方法,包括步骤:
S100:提供硅衬底;
S200:对所述硅衬底进行快速热退火处理,形成钝化层,所述快速热退火使用的气体包括氘气。
具体的,所述硅衬底的形成方法包括:
形成硅铸块(ingot);打磨所述硅铸块至所需的尺寸,例如晶圆大小的尺寸;
接着,对所述硅铸块依次进行切薄(slicing)、表面磨削(surface grinding)、抛光(polishing)、边缘处理(edge profiling)及清洗处理(cleaning)等工艺,从而形成硅衬底。在本实施例中,所述硅衬底为单晶硅,采用直拉法(CZ)形成。
在步骤S200中,对所述硅衬底进行快速热退火处理,形成钝化层。钝化层的形成能够减少硅衬底表面的粗糙度,提高硅衬底的性能。
其中,所述快速热退火的温度范围为1200℃~1380℃,例如是1300℃。
所述快速热退火使用的气体为氘气和氢气的混合气体,其中,氘气占的比例范围为1%~100%,具体比例可以由工艺需求来决定。
此外,除了使用氘气和氢气的混合气体,还可以使用氘气和氧气的混合气体,其中,氘气占的比例范围为1%~100%,具体比例可以由工艺需求来决定。
除了使用混合气体,还可以采用纯的氘气进行快速热退火处理。
使用氘气进行快速热退火处理时,氘原子能够暂时贮存在硅衬底中的间隙中,由于氘原子体积小,在后续形成栅氧化层时,可以与栅氧化层等的悬空键进行结合,形成稳定的化学键,消除多余的悬空键,从而可以提高栅氧化层的性能。此外,氘原子不仅仅与栅氧化层的悬空键进行结合,还能够与半导体器件的中其他层的悬空键进行结合,而且形成的化学键较其他元素(例如氢原子)形成的化学键更为稳定。
综上,在本发明实施例提供的晶圆的形成方法中,在形成硅衬底后,对硅衬底在氘气下进行快速热退火处理,形成钝化层,钝化层能够使硅衬底表面的粗糙度降低,在后续栅氧化层的形成或界面的形成时,氘能够扩散出,并与界面处等悬空键进行结合,形成较为稳定的结构,从而避免载流子的穿透,提高器件的性能。
上述仅为本发明的优选实施例而已,并不对本发明起到任何限制作用。任何所属技术领域的技术人员,在不脱离本发明的技术方案的范围内,对本发明揭露的技术方案和技术内容做任何形式的等同替换或修改等变动,均属未脱离本发明的技术方案的内容,仍属于本发明的保护范围之内。

Claims (10)

1.一种晶圆的形成方法,其特征在于,包括步骤:
提供硅衬底;
对所述硅衬底进行快速热退火处理,形成钝化层,所述快速热退火使用的气体包括氘气。
2.如权利要求1所述的晶圆的形成方法,其特征在于,所述快速热退火的温度范围为1200℃~1380℃。
3.如权利要求1所述的晶圆的形成方法,其特征在于,所述快速热退火使用的气体为氘气和氢气的混合气体。
4.如权利要求3所述的晶圆的形成方法,其特征在于,所述氘气占的比例范围为1%~100%。
5.如权利要求1所述的晶圆的形成方法,其特征在于,所述快速热退火使用的气体为氘气和氧气的混合气体。
6.如权利要求5所述的晶圆的形成方法,其特征在于,所述氘气占的比例范围为1%~100%。
7.如权利要求1所述的晶圆的形成方法,其特征在于,所述快速热退火使用的气体为氘气。
8.如权利要求1所述的晶圆的形成方法,其特征在于,所述硅衬底的形成方法包括:
形成硅铸块;
对所述硅铸块依次进行切薄、表面磨削、抛光、边缘处理及清洗处理,形成硅衬底。
9.如权利要求1所述的晶圆的形成方法,其特征在于,所述硅衬底为单晶硅。
10.如权利要求8所述的晶圆的形成方法,其特征在于,所述硅衬底采用直拉法形成。
CN201510659200.2A 2015-10-13 2015-10-13 晶圆的形成方法 Pending CN106571296A (zh)

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CN201510659200.2A CN106571296A (zh) 2015-10-13 2015-10-13 晶圆的形成方法
TW105107081A TWI593023B (zh) 2015-10-13 2016-03-08 晶圓的形成方法
US15/178,041 US20170103900A1 (en) 2015-10-13 2016-06-09 Method for forming wafer
JP2016123427A JP6174761B2 (ja) 2015-10-13 2016-06-22 ウエハ形成方法
DE102016115524.1A DE102016115524A1 (de) 2015-10-13 2016-08-22 Method for forming wafer
KR1020160122782A KR101888250B1 (ko) 2015-10-13 2016-09-26 웨이퍼를 형성하기 위한 방법

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845635A (zh) * 2017-10-31 2018-03-27 长江存储科技有限责任公司 一种存储结构及其形成方法
CN109841513A (zh) * 2017-11-24 2019-06-04 上海新昇半导体科技有限公司 一种晶片及其制造方法、电子装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255197B1 (en) * 1998-06-10 2001-07-03 Jim Mitzel Hydrogen annealing method and apparatus
CN101872746A (zh) * 2009-04-24 2010-10-27 上海华虹Nec电子有限公司 采用nd3退火来提高sonos闪存器件可靠性的方法
CN102487047A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法
CN103515213A (zh) * 2012-06-25 2014-01-15 中芯国际集成电路制造(上海)有限公司 形成FinFET栅介质层的方法和形成FinFET的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10223628A (ja) * 1997-02-04 1998-08-21 Fujitsu Ltd 半導体装置の製造方法
US5982020A (en) * 1997-04-28 1999-11-09 Lucent Technologies Inc. Deuterated bipolar transistor and method of manufacture thereof
US6797644B2 (en) * 2000-08-01 2004-09-28 Texas Instruments Incorporated Method to reduce charge interface traps and channel hot carrier degradation
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびsoi基板
US20030017690A1 (en) * 2001-07-18 2003-01-23 Motorola, Inc. Apparatus and method for attaching integrated circuit structures and devices utilizing the formation of a compliant substrate to a circuit board
JP2003209253A (ja) * 2002-01-11 2003-07-25 Seiko Epson Corp 基板装置及びその製造方法並びに電気光学装置及び電子機器
KR100482372B1 (ko) * 2002-12-03 2005-04-14 삼성전자주식회사 반도체 소자의 게이트 산화막 형성방법
JP4125952B2 (ja) * 2002-12-27 2008-07-30 株式会社東芝 半導体装置の製造方法
JP2005045203A (ja) * 2003-07-10 2005-02-17 Toshiba Corp 磁気ランダムアクセスメモリ及びその製造方法
JP4999265B2 (ja) * 2004-08-27 2012-08-15 大陽日酸株式会社 ゲート絶縁膜の製造方法
US20070187386A1 (en) * 2006-02-10 2007-08-16 Poongsan Microtec Corporation Methods and apparatuses for high pressure gas annealing
JP2008047752A (ja) * 2006-08-18 2008-02-28 Ihi Corp 半導体装置の製造方法及び装置
US20080050879A1 (en) * 2006-08-23 2008-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming metal-containing gate structures
JP2010141272A (ja) * 2008-12-15 2010-06-24 Sumco Corp エピタキシャルウェーハとその製造方法
JP6242724B2 (ja) * 2014-03-20 2017-12-06 株式会社東芝 半導体装置およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6255197B1 (en) * 1998-06-10 2001-07-03 Jim Mitzel Hydrogen annealing method and apparatus
CN101872746A (zh) * 2009-04-24 2010-10-27 上海华虹Nec电子有限公司 采用nd3退火来提高sonos闪存器件可靠性的方法
CN102487047A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 半导体结构的形成方法
CN102486999A (zh) * 2010-12-01 2012-06-06 中芯国际集成电路制造(北京)有限公司 栅极氧化层的形成方法
CN103515213A (zh) * 2012-06-25 2014-01-15 中芯国际集成电路制造(上海)有限公司 形成FinFET栅介质层的方法和形成FinFET的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
杜中一: "《半导体技术基础》", 31 January 2011, 化学工业出版社 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107845635A (zh) * 2017-10-31 2018-03-27 长江存储科技有限责任公司 一种存储结构及其形成方法
CN109841513A (zh) * 2017-11-24 2019-06-04 上海新昇半导体科技有限公司 一种晶片及其制造方法、电子装置

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