CN106558542A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN106558542A CN106558542A CN201610620077.8A CN201610620077A CN106558542A CN 106558542 A CN106558542 A CN 106558542A CN 201610620077 A CN201610620077 A CN 201610620077A CN 106558542 A CN106558542 A CN 106558542A
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 360
- 239000002184 metal Substances 0.000 claims abstract description 360
- 239000010410 layer Substances 0.000 claims abstract description 345
- 239000007769 metal material Substances 0.000 claims abstract description 42
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 229910052709 silver Inorganic materials 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 33
- 239000000463 material Substances 0.000 description 13
- 238000005240 physical vapour deposition Methods 0.000 description 13
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 11
- 238000007747 plating Methods 0.000 description 9
- 239000002002 slurry Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000004744 fabric Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004151 rapid thermal annealing Methods 0.000 description 3
- 229910052723 transition metal Inorganic materials 0.000 description 3
- -1 transition metal nitride Chemical class 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052756 noble gas Inorganic materials 0.000 description 2
- 150000002835 noble gases Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003112 inhibitor Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000003361 porogen Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
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Abstract
在制造半导体器件的方法中,在衬底上方形成介电层。在第一层间介电层中形成第一图案和第二图案。第一图案的宽度大于第二图案的宽度。在第一图案和第二图案中形成第一金属层。在第一图案中形成第二金属层。对第一和第二金属层实施平坦化操作以便形成通过第一图案的第一金属布线和通过第二图案的第二金属布线。第一金属层的金属材料不同于第二金属层的金属材料。第一金属布线包括第一和第二金属层并且第二金属布线包括第一金属层但不包括第二金属层。本发明的实施例还涉及半导体器件。
Description
技术领域
本发明涉及半导体集成电路,更具体地,涉及在金属布线之间具有气隙的半导体器件及其制造工艺。
背景技术
因为半导体工业采用新一代的具有更高性能和更大功能性的集成电路(IC),因此已经使用设置在下面的诸如晶体管的电子器件上方的多层金属布线结构。为了满足更高速度和更大可靠性的要求,已经开发了先进金属布线形成方法和结构。
发明内容
本发明的实施例提供了一种制造半导体器件的方法,包括:在衬底上方形成介电层;在所述介电层中形成第一图案和第二图案,所述第一图案的宽度大于所述第二图案的宽度;在所述第一图案和所述第二图案中形成第一金属层;在所述第一图案中形成第二金属层;以及对所述第一金属层和所述第二金属层实施平坦化操作以便形成通过所述第一图案的第一金属布线和通过所述第二图案的第二金属布线,其中:所述第一金属层的金属材料不同于所述第二金属层的金属材料,以及所述第一金属布线包括所述第一金属层和所述第二金属层,且所述第二金属布线包括所述第一金属层但不包括所述第二金属层。
本发明的另一实施例提供了一种半导体器件,包括:第一金属布线和第二金属布线,所述第一金属布线和所述第二金属布线在设置在衬底上方的同一层间介电层中形成,所述第一金属布线和所述第二金属布线设置在同一布线层上,所述布线层设置在所述层间介电层中,其中:所述第一金属布线至少包括由第一金属材料制成的第一金属层和设置在所述第一金属层上方的由第二金属材料制成的第二金属层,所述第二金属布线包括由所述第一金属材料制成的第一金属层但不包括由所述第二金属材料制成的任何金属层,以及所述第一金属材料不同于所述第二金属材料。
本发明的又一实施例提供了一种半导体器件,包括:第一金属布线和第二金属布线,所述第一金属布线和所述第二金属布线在设置在衬底上方的层间介电层中形成,所述第一金属布线和所述第二金属布线设置在同一布线层上,其中:所述第一金属布线包括具有多于一个导电层的分层结构,所述第二金属布线包括具有一个或多个导电层的分层结构,所述第一金属布线的分层结构不同于所述第二金属布线的分层结构。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图7示出根据本发明的一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。
图8和图9示出根据本发明的另一个实施例的用于制造金属布线结构的顺序工艺之一的示例性截面图。
图10A至图15示出根据本发明的另一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。
图16A至图21示出根据本发明的另一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现本发明的不同特征。下面将描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如,在下面的描述中第一部件在第二部件上方或者在第二部件上的形成可以包括第一部件和第二部件以直接接触方式形成的实施例,也可以包括额外的部件可以形成在第一和第二部件之间,以便第一部件和第二部件可以不直接接触的实施例。为了简明和清楚,各个部件可任意地以不同比例绘制。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作相应的解释。此外,术语“由…制成”可意指“包括”或“由…组成”。
图1至图7示出根据本发明的一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。在图1至图7中,示出了制造在衬底上方形成的金属布线层(布线层)之一的顺序工艺。尽管有构成位于衬底和金属布线层之间的半导体器件(下文称为“下面的结构”)的诸如晶体管或其他元件(例如,接触件等)的核心结构,但为了简洁在图1至图7中省略了这些下面的结构的详细图示。金属布线为在金属布线层中横向延伸的导电图案并且还可被称为互连件或互连金属层。
如图1所示,在设置在衬底1上方的下层结构5上方形成层间介电(ILD)层10。层间介电层还可被称为金属间介电(IMD)层。例如,ILD层10由一个或多个低-k介电材料层制成。低-k介电材料具有小于约4.0的k-值(介电常数)。一些低-k介电材料具有小于约3.5的k-值并且可具有小于约2.5的k-值。
ILD层10的材料可包括诸如SiCOH和SiOC的含有Si、O、C和/或H的化合物。诸如聚合物的有机材料可用于ILD层10。例如,在某些实施例中,ILD层10由含碳材料、有机-硅酸盐玻璃、含致孔剂的材料和/或其组合的一个或多个层制成。在一些实施例中,ILD层10中也可包括氮。ILD层10可为多孔层。在一个实施例中,ILD层10的密度小于约3g/cm3并且在其他实施例中可小于约2.5g/cm3。例如,可通过使用等离子体增强化学气相沉积(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)和/或旋涂技术形成ILD层10。在PECVD的情况下,在约25℃至约400℃的范围内的衬底温度下以及在小于100托的压力下沉积膜。
在一些实施例中,ILD层包括层间绝缘膜和线间绝缘膜,以便金属布线主要在金属间绝缘膜中形成。层间绝缘膜可包括SiOC膜,且线间绝缘膜可包括TEOS(正硅酸乙酯)膜。
如图2A和图2B所示,通过使用包括光刻和蚀刻工艺的图案化操作,在ILD层10中形成一个或多个第一凹槽15A和一个或多个第二凹槽15B。图2A是顶视图(平面图)且图2B是沿着图2A的线X1-X1截取的截面图。
在一些实施例中,可使用蚀刻停止层12以便可限定凹槽15A和15B的底部。在这种情况下,ILD层10可包括下ILD层10A和上ILD层10B,其中,蚀刻停止层12插入在下ILD层10A和上ILD层10B之间。下ILD层10A和上ILD层10B的材料可相同或不同。如果未使用蚀刻停止层,则可通过控制凹槽蚀刻的蚀刻时间或蚀刻速率控制凹槽的深度。在下面解释中,将其中形成凹槽的ILD 10的上部称为上ILD层10B,并将ILD 10的下部称为下ILD层10A,不论蚀刻停止层12是否存在。
如图2A和图2B所示,第一凹槽15A具有宽度Wa,其大于第二凹槽15B的宽度Wb。在一个实施例中,宽度Wa大于约40nm且小于约100μm,并且宽度Wb为从约40nm至约5nm的范围。在其他实施例中,宽度Wa大于约60nm且宽度Wb为从约30nm至10nm的范围。如图2A所示,凹槽15A和15B对应于金属布线,其通常具有长延伸线的形状。在垂直于金属布线(凹槽)的延伸方向的方向上限定宽度。
在一些实施例中,第一凹槽15A的深度Da为从约40nm至约100nm的范围,并且在其他实施例中为从约50nm至约80nm的范围。第二凹槽15B的深度Db与深度Da基本相同或略小于深度Da。
第一凹槽15A的高宽比(深度/宽度)小于约1,且第二凹槽15B的高宽比为从约1至约10的范围。
如图3所示,在凹槽中和在ILD 10上方形成阻挡层20。例如,阻挡层20由诸如TaN或TiN的过渡金属氮化物制成。在一些实施例中,阻挡层20的厚度为从约1nm至3nm的范围,并且在其他实施例中为从约1.5nm至约2.5nm的范围。可通过使用化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)或诸如无电极电镀的电镀形成阻挡层。
接下来,在阻挡层20上方形成第一金属层30。第一金属层30由Cu、Co、Al、Ru和Ag中的一种或多种制成。可通过ALD、PVD或CVD形成第一金属层30。ILD 10的上表面上的第一金属层的厚度T1为第二凹槽15B的宽度Wb的约50%或更大和约100%或更小并且小于约40nm。
关于该金属层形成操作,如图3所示,第二凹槽15B基本上由第一金属层30完全填充,同时第一凹槽15A未由第一金属层30完全填充。
然后,如图4所示,在第一金属层30上方形成第二金属层40。第二金属层40由Cu、Co、Al和Ag中的一种或多种制成,并且由与第一金属层30不同的材料制成。可通过PVD、CVD或电镀形成第二金属层40。ILD 10的上表面上的第二金属层的厚度T2为第一凹槽15A的宽度Wa的约50%或更大且小于约1000nm。在一些实施例中,T2为从约150nm至约1000nm的范围。
第二金属层40由与第一金属层30不同的材料制成。例如,当第一金属层30由Co制成时,第二金属层40由Cu、Al或Ag制成,并且当第一金属层30由Cu制成时,第二金属层40由Co、Al或Ag制成。在一个实施例中,第一金属层30由Co制成且第二金属层40由Cu制成。关于这些金属层形成操作,第一凹槽15A基本上由第一金属层30和第二金属层40完全填充。
在形成第二金属层40之后,实施诸如化学机械抛光(CMP)操作的平坦化操作。在本实施例中,平坦化操作包括三个CMP操作。
如图5所示,通过第一CMP操作,将第二金属层40部分去除。在一些实施例中,ILD10的上表面上的第二金属层40的剩余厚度T3为从约80nm至约120nm的范围。使用相对高的蚀刻速率实施第一CMP操作。
然后,如图6所示,实施第二CMP操作以部分去除第二金属层40和第一金属层30,并且CMP停止在ILD 10的上表面上的阻挡层20处。使用相对低的蚀刻速率实施第二CMP操作。
相对于第一金属层30,用于第一CMP的第一浆料对于第二金属层40具有约2或更大的蚀刻选择性。相对于第二金属层40,用于第二CMP的第二浆料对于第一金属层30具有约2或更大的蚀刻选择性。可通过调整抛光颗粒的类型、pH值、表面活性剂的类型、腐蚀抑制剂的类型以及螯合剂或强化剂的类型中的至少一个控制浆料的蚀刻选择性。
在第二CMP操作中,在暴露第一金属层30之后,第二金属层40的蚀刻速率小于第一金属层30的蚀刻速率。因此,即使第一凹槽15A具有更宽的图案宽度,仍可最小化第二金属层40的凹陷效应。在一个实施例中,从阻挡层20的上表面测量的金属填充的凹槽15A的中心处的凹陷量Dd为从约10nm至约20nm的范围。
在第二CMP操作之后,如图7所示,实施第三CMP操作以去除设置在ILD 10上表面上的阻挡层20并且获得金属层的期望的厚度和平坦度。用于第三CMP的第三浆料对于第二金属层40和第一金属层30具有基本相等的蚀刻速率。
通过第三CMP操作,在设置在同一层间介电层中的一个金属层层级(同一金属层层级)中形成第一金属布线M1A和第二金属布线M1B。第一金属布线M1A包括阻挡层20、第一金属层30和第二金属层40,并且第二金属布线M1B包括阻挡层20和第一金属层30而没有第二金属层40。换言之,第一金属布线M1A和第二金属布线M1B的层结构不同,并且特别地,第一金属布线M1A的导电层的数量不同于(大于)第二金属布线M1B的导电层的数量。在形成位于一个金属层中的金属布线之后,在ILD 10以及金属布线M1A和M1B上方形成第二ILD。在平面图中金属布线M1A和M1B横向延伸并且用于电连接位于不同横向位置的不同元件。
在上述实施例中,如图3所示,第二凹槽15B基本上由第一金属层30完全填充。然而,在一些实施例中,如图8所示,在第二凹槽15B中形成裂缝或空隙35。裂缝或空隙35的宽度Ws为从约1nm至约5nm的范围。
当形成裂缝或空隙时,如图8所示,实施热处理HT以去除裂缝或空隙35。热处理包括在熔炉中的快速热退火(RTA)操作或加热操作。在一些实施例中,在惰性气体(例如,Ar和/或N2)环境中,在从约200℃至约500℃的范围内的温度下将RTA实施约1分钟至约10分钟。可在惰性气体(例如,Ar和/或N2)环境中,在从约200℃至约500℃的范围内的温度下实施熔炉加热约10分钟至约30分钟。通过热处理,第一金属层30中的晶粒生长并且填充裂缝或空隙35。
在一些实施例中,如图9所示,在形成第二金属层40之后实施热处理HT。可在平坦化操作之后或之间实施热处理HT。例如,分别在形成第一金属层之后和形成第二金属层之后,可将热处理实施两次或多次。
图10A至图15示出根据本发明的另一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。
在图10A至图15中,示出用于制造通孔层(通孔层级)之一的顺序工艺,所述通孔层在衬底上方的垂直方向上在两个金属布线层(层级)之间或者在一个金属布线层和下面的结构之间形成。通孔是在通孔层中垂直延伸的导电图案并且连接下层导电图案和上层导电图案。通孔还可被称为通孔插塞或接触插塞。关于图1至图9描述的相同或类似的结构、操作、工艺和/或材料可应用于下列实施例并且为了简洁可省略其详细描述。
与图1类似,在设置在衬底1上方的下层结构5上方形成层间介电(ILD)层10。在该实施例中,形成对应于图2B的ILD 10的下部的ILD层10A。
如图10A和图10B所示,通过使用包括光刻和蚀刻工艺的图案化操作在ILD层10A中形成一个或多个第一导通孔16A以及一个或多个第二导通孔16B。图10A是顶视图(平面图)且图10B是沿着图10A的线X2-X2截取的截面图。
如图10A以及图10B所示,在下导电图案7A上方形成第一导通孔16A并在下导电图案7B上方形成第二导通孔16B。分别在第一和第二导通孔16A和16B的底部暴露下导电图案7A和7B。下导电图案7A和7B可为位于下面的核心结构中的导电图案或者位于下金属布线层中的导电图案。
如图10A以及图10B所示,第一导通孔16A具有宽度Wc,其大于第二导通孔16B的宽度Wd。在一个实施例中,宽度Wc大于约40nm且小于约150nm,并且宽度Wd为从约40nm至约5nm的范围。在其他实施例中,宽度Wc大于约60nm且宽度Wd为从约30nm至10nm的范围。如图10A所示,在平面图中,导通孔16A以及16B具有基本上圆形形状。将宽度定义为圆形的直径。当第一导通孔的尺寸足够大时,第一导通孔的形状为圆角正方形。如果在设计方案上导通孔具有矩形形状,则在ILD 10A中形成的导通孔具有椭球形或圆矩形。
在一些实施例中,第一导通孔16A和第二导通孔16B的深度Dc为从约40nm至约100nm的范围,并且在其他实施例中为从约50nm至约80nm的范围。
第一导通孔16A的高宽比(深度/宽度)小于约1,并且第二导通孔16B的高宽比为从约1至约10的范围。
与图3类似,如图11所示,在凹槽中和在ILD 10A上方形成阻挡层20。例如,阻挡层20由诸如TaN或TiN的过渡金属氮化物制成。在一些实施例中,阻挡层20的厚度为从约1nm至3nm的范围,并且在其他实施例中,为从约1.5nm至约2.5nm的范围。可通过使用化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)或诸如无电极电镀的电镀形成阻挡层。
接下来,与图3类似,如图11所示,在阻挡层20上方形成第一金属层30。第一金属层30由Cu、Co、Ru、Al和Ag中的一种或多种制成。可通过ALD、PVD或CVD形成第一金属层30。ILD10的上表面上的第一金属层的厚度T1为第二导通孔16B的宽度Wd的约50%或更大和约100%或更小并且小于约40nm。
关于该金属层形成操作,如图11所示,第二导通孔16B基本上由第一金属层30完全填充,同时第一导通孔16A未由第一金属层30完全填充。
然后,如图12所示,在第一金属层30上方形成第二金属层40。第二金属层40由Cu、Co、Al和Ag中的一种或多种制成,并且由与第一金属层30不同的材料制成。可通过PVD、CVD或电镀形成第二金属层40。ILD 10的上表面上的第二金属层的厚度T2为第一导通孔16A的宽度Wc的约50%或更大且小于约600nm。在一些实施例中,T2为从约100nm至约600nm的范围。在一个实施例中,第一金属层30由Co制成且第二金属层40由Cu制成。关于这些金属层形成操作,第一导通孔16A基本上由第一金属层30和第二金属层40完全填充。
在形成第二金属层40之后,实施诸如化学机械抛光(CMP)操作的平坦化操作。在本实施例中,平坦化操作包括三个CMP操作。
如图13所示,通过第一CMP操作,将第二金属层40部分去除。在一些实施例中,ILD10A的上表面上的第二金属层40的剩余厚度T3为从约80nm至约120nm的范围。使用相对高的蚀刻速率实施第一CMP操作。
然后,实施第二CMP操作以部分去除第二金属层40和第一金属层30。如图14所示,CMP停止在ILD 10A的上表面上的阻挡层20处。使用相对低的蚀刻速率实施第二CMP操作。
相对于第一金属层30,用于第一CMP的第一浆料对于第二金属层40具有约2或更大的蚀刻选择性。相对于第二金属层40,用于第二CMP的第二浆料对于第一金属层30具有约2或更大的蚀刻选择性。
在第二CMP操作中,在暴露第一金属层30之后,第二金属层40的蚀刻速率小于第一金属层30的蚀刻速率。因此,即使第一导通孔16A具有更宽的图案宽度,仍可最小化第二金属层40的凹陷效应。在一个实施例中,从阻挡层20的上表面测量的金属填充的凹槽16A的中心处的凹陷量Dd为从约10nm至约20nm的范围。
在第二CMP操作之后,如图15所示,实施第三CMP操作以去除设置在ILD 10A的上表面上的阻挡层20并且获得通孔插塞的期望的厚度和平坦度。用于第三CMP的第三浆料对于第二金属层40和第一金属层30具有基本相等的蚀刻速率。
通过第三CMP操作,在一个通孔层层级中形成第一通孔插塞VA和第二通孔插塞VB。第一通孔插塞VA包括阻挡层20、第一金属层30和第二金属层40,并且第二通孔插塞VB包括阻挡层20和第一金属层30而没有第二金属层40。在形成位于一个通孔层中的通孔插塞之后,在ILD 10A以及通孔插塞VA和VB上方形成第二ILD。通孔插塞VA和VB分别用于连接上层元件和下层元件。
与图8和图9类似,当在第一金属层30中形成裂缝或空隙时,实施热处理以去除裂缝或空隙。
图16A至图21示出根据本发明的另一个实施例的用于制造半导体器件的金属布线结构的示例性顺序工艺。
在图16A至图21中,示出用于制造金属布线层(布线层级)之一以及设置在金属布线层之一的正下方的通孔层之一的顺序工艺。尽管有构成位于衬底和金属布线层之间的半导体器件(下文称为“下面的结构”)的诸如晶体管或其他元件(例如,接触件等)的核心结构,但为了简洁在图16A至图21中省略这些下面的结构的详细插图。关于图1至图15描述的相同或类似的结构、操作、工艺和/或材料可应用于下列实施例并且为了简洁可省略其详细描述。
如图1所示,在设置在衬底1上方的下层结构5上方形成层间介电(ILD)层10。
如图16A以及图16B所示,通过使用包括光刻和蚀刻工艺的图案化操作,在ILD 10的上ILD 10B中形成一个或多个凹槽15C,并在下ILD层10A中形成一个或多个第一导通孔17A和一个或多个第二导通孔17B。图16A是顶视图(平面图)且图16B是沿着图16A的线X3-X3截取的截面图。
如图16A以及图16B所示,在下导电图案7A上方形成第一导通孔17A并在下导电图案7B上方形成第二导通孔17B。分别在第一和第二导通孔17A以及17B的底部暴露下导电图案7A以及7B。下导电图案7A以及7B可为位于下面的核心结构中的导电图案或者位于下金属布线层中的导电图案。
如图16A以及图16B所示,第一导通孔17A具有宽度Wc’,其大于第二导通孔17B的宽度Wd’。在一个实施例中,宽度Wc’大于约40nm且宽度Wd’为从约40nm至约5nm的范围。值Wc’/Wd’小于约25。在其他实施例中,宽度Wc’大于约60nm且宽度Wd’为从约30nm至10nm的范围。凹槽15C具有宽度We,其大于第二导通孔17B的宽度Wd’。宽度We可等于或大于第一导通孔17A的宽度Wc’。尽管在图16A以及16B中的一个凹槽15C中形成第一和第二导通孔17A以及17B,但可在不同凹槽中形成第一和第二导通孔。
在一些实施例中,凹槽15C的深度Da’为从约40nm至约100nm的范围,并且在其他实施例中为从约50nm至约80nm的范围。在一些实施例中,第一导通孔17A和第二导通孔17B的深度Dc’为从约40nm至约100nm的范围,并且在其他实施例中为从约50nm至约80nm的范围。
凹槽15C的高宽比(深度/宽度)小于约1。第一导通孔17A的高宽比(深度/宽度)小于约1,且第二导通孔17B的高宽比为从约1至约10的范围。
如图17所示,在凹槽15C、第一和第二导通孔17A以及17B中以及在ILD10B上方形成阻挡层20。例如,阻挡层20由诸如TaN或TiN的过渡金属氮化物制成。在一些实施例中,阻挡层20的厚度为从约1nm至3nm的范围,并且在其他实施例中为从约1.5nm至约2.5nm的范围。可通过使用化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)或诸如无电极电镀的电镀形成阻挡层。
接下来,在阻挡层20上方形成第一金属层30。第一金属层30由Cu、Co、Ru、Al和Ag中的一种或多种制成。可通过ALD、PVD或CVD形成第一金属层30。ILD 10的上表面上的第一金属层的厚度T1为第二导通孔17B的宽度Wd’的约50%或更大和约100%或更小并且小于约40nm。
关于该金属层形成操作,如图17所示,第二导通孔17B基本上由第一金属层30完全填充,同时凹槽15C和第一导通孔17A未由第一金属层30完全填充。
然后,如图18所示,在第一金属层30上方形成第二金属层40。第二金属层40由Cu、Co、Al和Ag中的一种或多种制成,并且由与第一金属层30不同的材料制成。可通过PVD、CVD或电镀形成第二金属层40。ILD 10B的上表面上的第二金属层的厚度T2为凹槽15C的宽度We的约50%或更大且小于约1000nm。在一些实施例中,T2为从约150nm至约1000nm的范围。
第二金属层40由与第一金属层30不同的材料制成。例如,当第一金属层30由Co制成时,第二金属层40由Cu、Al或Ag制成,并且当第一金属层30由Cu制成时,第二金属层40由Co、Al或Ag制成。在一个实施例中,第一金属层30由Co制成且第二金属层40由Cu制成。关于这些金属层形成操作,凹槽15C和第一导通孔17A基本上由第一金属层30和第二金属层40完全填充。
在形成第二金属层40之后,实施诸如化学机械抛光(CMP)操作的平坦化操作。在本实施例中,平坦化操作包括三个CMP操作。
如图19所示,通过第一CMP操作,将第二金属层40部分去除。在一些实施例中,ILD10B的上表面上的第二金属层40的剩余厚度T3为从约80nm至约120nm的范围。使用相对高的蚀刻速率实施第一CMP操作。
然后,如图19所示,实施第二CMP操作以部分去除第二金属层40和第一金属层30,并且CMP停止在ILD 10B的上表面上的阻挡层20处。使用相对低的蚀刻速率实施第二CMP操作。
在第二CMP操作中,在暴露第一金属层30之后,第二金属层40的蚀刻速率小于第一金属层30的蚀刻速率。因此,即使凹槽15C具有更宽的图案宽度,仍可最小化第二金属层40的凹陷效应。在一个实施例中,从阻挡层20的上表面测量的金属填充的凹槽15C的中心处的凹陷量Dd为从约10nm至约20nm的范围。
在第二CMP操作之后,如图21所示,实施第三CMP操作以去除设置在ILD 10B的上表面上的阻挡层20并且获得金属层的期望的厚度和平坦度。用于第三CMP的第三浆料对于第二金属层40和第一金属层30具有基本相等的蚀刻速率。
通过第三CMP操作,在一个金属层层级中形成金属布线M1,并在位于一个金属层层级之下的一个通孔层层级中形成第一通孔插塞VA和第二通孔插塞VB。金属布线M1和第一通孔插塞VA包括阻挡层20,第一金属层30和第二金属层40,以及第二通孔插塞VB包括阻挡层20和第一金属层30而没有第二金属层40。在形成一个金属层中的金属布线之后,在ILD 10B和金属布线MA以及通孔插塞VA和VB上方形成第二ILD。
与图8以及图9类似,当在第一金属层30中形成裂缝或空隙时,实施热处理以去除裂缝或空隙。
上述实施例并不互相排斥,并且可将不同实施例结合。此外,图案(例如,凹槽、导通孔)的数量不局限于附图所示的数量。
本文描述的各个实施例或实例提供若干优于现有技术的优点。例如,在本发明中,由于使用两种不同的金属层和两个不同的平坦化操作(CMP),因此能够降低更宽图案中的凹陷效应。此外,低的凹陷效应可降低CMP中膜的总损失并且降低抛光时间。而且,可改善图案形貌,从而提高制造产量。
应该理解,本文不必讨论所有优点,没有特定优势是所有实施例或实例都必需的,并且其他实施例或实例可提供不同优点。
根据本发明的一个方面,在制造半导体器件的方法中,在衬底上方形成介电层。在第一层间介电层中形成第一图案和第二图案。第一图案的宽度大于第二图案的宽度。在第一图案和第二图案中形成第一金属层。在第一图案中形成第二金属层。对第一和第二金属层实施平坦化操作以便形成通过第一图案的第一金属布线和通过第二图案的第二金属布线。第一金属层的金属材料不同于第二金属层的金属材料。第一金属布线包括第一和第二金属层并且第二金属布线包括第一金属层但不包括第二金属层。
在上述方法中,还包括,在形成所述第一金属层之前,在所述第一图案和所述第二图案中以及在所述介电层的上表面上方形成第三金属层。
在上述方法中,其中:所述第一金属层的金属材料包括Cu、Co、Ru、Al和Ag中的一种,以及所述第二金属层的金属材料包括Cu、Co、Al和Ag中的一种。
在上述方法中,其中:所述第一金属层的金属材料包括Co,以及所述第二金属层的金属材料包括Cu。
在上述方法中,还包括,在形成所述第一金属层之前,在所述第一图案和所述第二图案中以及在所述介电层的上表面上方形成第三金属层,其中,所述第三金属层包括TiN或TaN。
在上述方法中,其中,所述平坦化操作包括:第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率。
在上述方法中,其中,所述平坦化操作包括:第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率,其中,实施所述第一平坦化操作,使得不暴露所述第一金属层。
在上述方法中,还包括,在形成所述第一金属层之前,在所述第一图案和所述第二图案中以及在所述介电层的上表面上方形成第三金属层,其中:所述平坦化操作包括:第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率,以及所述第二平坦化操作使用设置在所述介电层的上表面上方的所述第三金属层作为蚀刻停止层。
在上述方法中,还包括,在形成所述第一金属层之前,在所述第一图案和所述第二图案中以及在所述介电层的上表面上方形成第三金属层,其中:所述平坦化操作包括:第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率,以及所述第二平坦化操作使用设置在所述介电层的上表面上方的所述第三金属层作为蚀刻停止层,所述平坦化操作包括:在所述第二平坦化操作之后实施的第三平坦化操作,其中,通过所述第三平坦化操作去除设置在所述介电层的上表面上方的所述第三金属层。
在上述方法中,其中,所述第一图案和所述第二图案是在平面图中横向延伸的凹槽并且用于金属布线以电连接位于不同横向位置处的不同元件。
在上述方法中,其中,所述第一图案和所述第二图案是在所述介电层中垂直延伸的孔并且用于连接上层元件和下层元件的接触插塞。
在上述方法中,还包括在形成所述第一金属层之后且在形成所述第二金属层之前实施热处理。
在上述方法中,还包括在形成所述第二金属层之后实施热处理。
根据本发明的另一个方面,半导体器件包括第一金属布线和第二金属布线,第一金属布线和第二金属布线在设置在衬底上方的层间介电层中形成。第一金属布线和第二金属布线设置在同一布线层上。第一金属布线至少包括由第一材料制成的第一金属层和设置在第一金属层上方的由第二金属材料制成的第二金属层。第二金属布线包括由第一金属材料制成的第一金属层但不包括由第二金属材料制成的任何金属层。第一金属材料不同于第二金属材料。
在上述半导体器件中,其中:所述第一金属布线还包括设置所述第一金属布线的所述第一金属层下方的由第三金属材料制成的金属阻挡层,以及所述第二金属布线还包括设置在所述第二金属布线的所述第一金属层下方的由所述第三金属材料制成的金属阻挡层。
在上述半导体器件中,其中:所述第一金属材料包括Cu、Co、Ru、Al和Ag中的一种,以及所述第二金属材料包括Cu、Co、Al和Ag中的一种。
在上述半导体器件中,其中:所述第一金属层的金属材料包括Co,以及所述第二金属层的金属材料包括Cu。
在上述半导体器件中,其中:所述第一金属布线还包括设置所述第一金属布线的所述第一金属层下方的由第三金属材料制成的金属阻挡层,以及所述第二金属布线还包括设置在所述第二金属布线的所述第一金属层下方的由所述第三金属材料制成的金属阻挡层,其中,所述第三金属材料包括TiN或TaN。
根据本发明的另一个方面,半导体器件包括第一金属布线和第二金属布线,第一金属布线和第二金属布线在设置在衬底上方的层间介电层中形成。第一金属布线和第二金属布线设置在同一布线层上。第一金属布线包括具有多于一个导电层的分层结构,并且第二金属布线包括具有一个或多个导电层的分层结构。第一金属布线的分层结构不同于第二金属布线的分层结构。
在上述半导体器件中,其中:所述第一金属布线中的导电层的数量大于所述第二金属布线中的导电层的数量。
上面论述了若干实施例的部件,以便本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种制造半导体器件的方法,包括:
在衬底上方形成介电层;
在所述介电层中形成第一图案和第二图案,所述第一图案的宽度大于所述第二图案的宽度;
在所述第一图案和所述第二图案中形成第一金属层;
在所述第一图案中形成第二金属层;以及
对所述第一金属层和所述第二金属层实施平坦化操作以便形成通过所述第一图案的第一金属布线和通过所述第二图案的第二金属布线,其中:
所述第一金属层的金属材料不同于所述第二金属层的金属材料,以及
所述第一金属布线包括所述第一金属层和所述第二金属层,且所述第二金属布线包括所述第一金属层但不包括所述第二金属层。
2.根据权利要求1所述的方法,还包括,在形成所述第一金属层之前,在所述第一图案和所述第二图案中以及在所述介电层的上表面上方形成第三金属层。
3.根据权利要求1所述的方法,其中:
所述第一金属层的金属材料包括Cu、Co、Ru、Al和Ag中的一种,以及
所述第二金属层的金属材料包括Cu、Co、Al和Ag中的一种。
4.根据权利要求1所述的方法,其中:
所述第一金属层的金属材料包括Co,以及
所述第二金属层的金属材料包括Cu。
5.根据权利要求2所述的方法,其中,所述第三金属层包括TiN或TaN。
6.根据权利要求1所述的方法,其中,所述平坦化操作包括:
第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及
在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率。
7.根据权利要求6所述的方法,其中,实施所述第一平坦化操作,使得不暴露所述第一金属层。
8.根据权利要求2所述的方法,其中:
所述平坦化操作包括:
第一平坦化操作,其中,所述第二金属层的蚀刻速率高于所述第一金属层的蚀刻速率;以及
在所述第一平坦化操作之后实施的第二平坦化操作,其中,所述第二金属层的蚀刻速率小于所述第一金属层的蚀刻速率,以及
所述第二平坦化操作使用设置在所述介电层的上表面上方的所述第三金属层作为蚀刻停止层。
9.一种半导体器件,包括:
第一金属布线和第二金属布线,所述第一金属布线和所述第二金属布线在设置在衬底上方的同一层间介电层中形成,所述第一金属布线和所述第二金属布线设置在同一布线层上,所述布线层设置在所述层间介电层中,其中:
所述第一金属布线至少包括由第一金属材料制成的第一金属层和设置在所述第一金属层上方的由第二金属材料制成的第二金属层,
所述第二金属布线包括由所述第一金属材料制成的第一金属层但不包括由所述第二金属材料制成的任何金属层,以及
所述第一金属材料不同于所述第二金属材料。
10.一种半导体器件,包括:
第一金属布线和第二金属布线,所述第一金属布线和所述第二金属布线在设置在衬底上方的层间介电层中形成,所述第一金属布线和所述第二金属布线设置在同一布线层上,其中:
所述第一金属布线包括具有多于一个导电层的分层结构,
所述第二金属布线包括具有一个或多个导电层的分层结构,
所述第一金属布线的分层结构不同于所述第二金属布线的分层结构。
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US9530737B1 (en) | 2016-12-27 |
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US11127680B2 (en) | 2021-09-21 |
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