CN107658289A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明的实施例提供了一种半导体器件,包括:第一层间介电(ILD)层,设置在衬底上方;以及第一金属配线图案,形成在第一层间介电层中并且沿着与衬底平行的第一方向延伸。在沿横穿第一方向且与衬底平行的第二方向的截面中,第一金属配线图案的顶部被第一二维材料层覆盖。本发明的实施例还提供了另一种半导体器件和制造半导体器件的方法。
Description
技术领域
本公开涉及半导体集成电路,更具体地,涉及具有带二维材料层的金属配线结构的半导体器件和其制造工艺。
背景技术
随着半导体工艺引入具有更高性能和更大功能的新一代集成电路(IC),已经采用设置在诸如晶体管的底层电子器件上方的多层金属配线结构。为了满足更高速度和更可靠的要求,已经开发出高级金属配线形成方法。
发明内容
根据本公开的实施例,提供了一种半导体器件,包括:第一层间介电(ILD)层,设置在衬底上方;以及第一金属配线图案,形成在第一层间介电层中并且沿着与衬底平行的第一方向延伸。在沿横穿第一方向且与衬底平行的第二方向的截面中,第一金属配线图案的顶部被第一二维材料层覆盖。
根据本公开的实施例,提供了一种半导体器件,包括:第一层间介电(ILD)层,设置在衬底上方;第一金属配线图案,形成在第一层间介电层中并且沿着平行于衬底的第一方向延伸;第二ILD层,设置在第一ILD层和第一金属配线图案上方;以及第二金属配线图案,形成在第二ILD层中并且连接到第一金属配线图案。在沿横穿第一方向并且与衬底平行的第二方向的截面中,第二金属配线图案的顶部被第一二维材料层覆盖。
根据本公开的实施例,提供了一种制造半导体器件的方法,包括:在衬底上方形成第一层间介电层。在第一层间介电层中形成第一凹槽。在第一凹槽中形成金属配线图案。在金属配线图案的顶部上形成二维材料层。
附图说明
当结合参考附图进行阅读时,根据下文具体的描述可以更好地理解本公开。应该强调,根据工业中的标准实践,各个部件未按比例绘出且仅用于示出的目的。事实上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1至图13示出了根据本公开一个实施例的用于制造半导体器件的顺序工艺的示例性截面视图。
图14至图17示出了根据本公开另一个实施例的用于制造半导体器件的顺序工艺的示例性截面视图。
图18至图23示出了根据本公开另一个实施例的用于制造半导体器件的顺序工艺的截面视图。
图24至图25示出了根据本公开另一个实施例的用于制造半导体器件的顺序工艺的截面视图。
具体实施方式
应该理解,以下公开提供了用于实现本发明不同特征的许多不同实施例或实例。以下描述了部件和配置的具体实施例或实例以简化本发明。当然,这些仅仅为实例而不用于限制。例如,元件的尺寸并不限于所公开的范围或数值,而是可依据器件的工艺条件和/或者期望的属性。此外,在以下描述中第一部件形成在第二部件上方或第二部件上包括第一和第二部件被形成为直接接触的实施例,并且还可以包括形成插入第一和第二部件之间的附加部件以使第一和第二部件不直接接触的实施例。为了简化和清楚的目的,图中各个部件可以按不同比例任意绘制。
此外,为了便于描述,诸如“在…下面”、“在…下方”、“下”、“在…上方”、“上”等空间相对位置术语在本文中可以用于描述如附图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中描述的方位外,这些空间相对位置术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上),并因此对本文中使用的空间相对位置描述符进行同样的解释。另外,术语“由…制成”可意味着“包括”或“由…组成”。
图1至图13是根据本公开一个实施例的用于制造半导体器件的顺序工艺的示例性截面视图。图1至图13示例了制造一个或多个形成在衬底之上的金属配线层(配线水平)的示例性顺序工艺。虽然存在构成衬底和金属配线层之间的半导体器件(这以后称作“下方的结构”)的诸如晶体管或其它元件(例如,接触件等)的核心结构,但为了简单起见在图1至图13中省略了这些元件的详细示例说明。应当理解,在图1至图13示出的工艺之前、期间和之后能够提供另外的操作,并且对于本方法的另外实施例而言下面描述的一些操作能够被替换或删除。操作/工艺的顺序可以是互换的。
如图1所示,第一层间介电(ILD)层10形成在设置于衬底1上方的底层结构5上方。底层结构5包括晶体管、电阻器、电容器、局部配线、隔离层和/或器件隔离层。
层间介电层还可被称为金属间介电(IMD)层。第一ILD层10由例如氧化硅基材料、氮化硅基材料和低k介电材料中的一层或多层制成。低k介电材料具有低于约3.5的k值(介电常数)。一些低k介电材料具有低于约3.5的k值,并且具有低于约2.5的k值。氧化硅基材料包括氧化硅、SiON、SiOC或者SiOCN、SiCOH,并且氮化硅基材料包括氮化硅、SiON、SiCN或者SiOCN。
诸如聚合物的有机材料可用于第一ILD层10。例如,第一ILD层10由含碳材料、有机硅酸盐玻璃、含多孔材料和/或其组合的一层或多层制成。在一些实施例中,氮也可被包括在第一ILD层10中。第一ILD层10可以是多孔层。在一个实施例中,第一ILD层10的密度小于约3g/cm3,并且在另一个实施例中小于约2.5g/cm3。第一ILD层10可通过使用例如等离子增强化学汽相沉积(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)和/或旋涂技术形成。在PECVD情况下,薄膜以范围在约25℃至约400℃之间的衬底温度和以小于100托的压力沉积。
在一些实施例中,第一ILD层可包括层间绝缘膜和线间绝缘膜,使得金属配线可主要在金属间绝缘膜中形成。层间绝缘膜可包括SiOC膜并且线间绝缘膜可包括TEOS(四乙基原硅酸盐)膜。
形成金属配线图案的操作包括镶嵌工艺。在镶嵌工艺中,金属材料的一层或多层可形成在第一凹槽15和第一ILD层10的上表面中,并且实施诸如化学机械抛光(CMP)方法和/或回蚀刻方法的平坦化工艺以去除金属材料的形成在第一ILD层10的上表面上的部分。
如图2所示,第一凹槽15通过使用包括光刻和蚀刻工艺的图案化操作形成在第一ILD层10中。在一些实施例中,连接到底层结构中的一个或多个元件的一个或多个通孔(接触孔)(未示出)可形成在第一凹槽的底部。在一些实施例中,第一凹槽15包括作为通孔部分的下部和作为配线部分的在Y方向延伸的上部,此处Z方向是堆叠方向(衬底的法线方向)。
在一些实施例中,蚀刻停止层12可被使用以限定凹槽15的底部。在这种情况下,第一ILD层10可包括下方第一ILD层10A和上方第一ILD层10B,且蚀刻停止层12插入在这两者之间。用于下方第一ILD层10A和上方第一ILD层10B的材料可以相同或不同。如果没有使用蚀刻停止层,可通过控制蚀刻时间或凹槽蚀刻的蚀刻速率来控制凹槽的深度。
如图3所示,由导电材料制成的阻挡层20形成在第一ILD 10上方和凹槽15内部。阻挡层20包括TiN、TaN和Ti中的一层或多层。在一些实施例中,阻挡层20的厚度在约0.5nm到约7nm的范围内。阻挡层20能够通过化学汽相沉积(CVD)、包括溅射的物理汽相沉积(PVD)、原子层沉积(ALD)、无极电镀和/或化学电镀形成。
在阻挡层20形成后,形成金属层30,如图4所示。用于金属层30的金属材料是Al、Cu、Co、Mn、W、Ni、Ti、Ta、Ru、Rh、Ir、Mo或其合金、TiN、TaN、TiW、WN、TiAl、TiAlN、TaC、TaCN、NiSi以及TiSiN的一层或多层。在一个实施例中,金属层30包括Cu和Cu合金(例如CuMn)或Ni。
随后,如图5所示,通过CMP去除设置在第一ILD层10的上表面上的阻挡层20和金属层30的上部部分。
在一些实施例中,如图6所示,可对金属层30的暴露表面进行物理和/或化学处理。在某些实施例中,在第一ILD层10的上部表面和金属层30的暴露表面上方实施等离子处理35。使用H2气体、NH3气体和/或Ar气体生成等离子体。
应用等离子处理35以去除在暴露的金属层30的上表面上形成的Cu氧化物并且促使例如石墨烯的二维材料容易地沉积。等离子处理35还能够修改第一ILD层10的表面,使得石墨烯生长被抑制在第一ILD层10的表面上。因此,仅选择性地将石墨烯沉积在金属层(Cu层)30上是可能的。在等离子处理期间,衬底温度维持在约25℃(室温)至约400℃的温度范围内。在一些实施例中,等离子的输入功率在从约100W至约1000W的范围内,且等离子处理期间的压力在约0.1托到约50托的范围内。在某些实施例中,等离子处理的持续期间在约3秒到约180秒的范围内。
等离子处理35可包括单步工艺或多步工艺,每一步包含氢基气体、氨基气体或氩基气体。在一些实施例中,自组装的单层(SAM)(未示出)形成在第一ILD层的表面上,其可以进一步抑制石墨烯层的沉积。SAM可由硅烷基材料、磷酸盐基材料、胺基材料和/或硫醇基材料制成。在一些实施例中,SAM的厚度在约2nm至约7nm的范围内。可省略等离子处理35。
在等离子处理35之后,二维(2D)材料层40选择性地形成在金属层30的表面上,如图7所示。二维材料通常被认为是具有几纳米或更小厚度的物质。在一些实施例中,2D材料层40包括石墨烯基材料,例如未掺杂的石墨烯、掺杂的石墨烯和石墨烯氧化物;过渡金属硫族化合物(TMD),例如MoS2、WS2和NbSe2;或者BN。
在一个实施例中,2D材料层40包括石墨烯。石墨烯层能够使用甲烷气体、乙烷气体、丙烷气体或者其他碳氢化合物气体中的一个或多个与氢气一起通过热CVD或等离子CVD形成。石墨烯层能够是单层或多层结构。因为诸如Cu或Ni的底层金属用作催化剂,因此石墨烯层能够选择性地形成在金属层30的表面上,如图7所示。在一些实施例中,还在阻挡层20上形成石墨烯层。在石墨烯的形成工艺期间,衬底温度在一些实施例中维持在约200℃至约750℃的温度范围内,并且在另一些实施例中维持在约250℃至约450℃温度范围内。在一些实施例中,采用了湿式形成工艺。
当2D材料为石墨烯氧化物时,通过以氧化剂或氧等离子体处理石墨层来形成石墨烯氧化物层。当2D材料是TMD或BN时,通过CVD、PVD和/或ALD形成2D材料层,并且可实施图案化操作以在金属层30的表面上形成2D材料层40。与石墨烯的情况相似,Cu层能够用作催化层,并且在铜表面上生长TMD或BN能够比在绝缘材料上生长TMD或BN更快,并且TMD或BN层能够可选择性地形成。
在一些实施例中,2D材料层40的厚度在约0.3nm至约2nm的范围中。
在形成2D材料层40后,可形成蚀刻停止层(ESL)45以覆盖2D材料层40和第一ILD层10的表面,如图8所示。ESL 45包括氮化硅基的绝缘材料的一层或多层。在一个实施例中,通过CVD形成的SiN被用作ESL 45。ESL 45的厚度在一些实施例中在约5nm至约15nm的范围内。可省略ESL 45。
随后,如图9所示,第二ILD层50被形成在ESL 45上。第二ILD层50可通过与第一ILD层10相同的工艺形成。
如图9所示,在沿X方向的截面中,金属配线图案WP1的顶部被2D材料层40覆盖,金属配线图案WP1的侧边和底部中至少一个被由不同于2D材料层40的导电材料制成的阻挡层20覆盖。在一个实施例中,金属配线图案WP1的侧边和底部由阻挡层20覆盖。
随后,上部金属层被形成在金属配线图案上。如图10所示,开口55被形成在第二ILD层50和ESL 45中以制造金属配线图案WP2。
然后,如图11所示,由导电材料制成的第二阻挡层60被形成在第二ILD层60上方和开口55内部。第二阻挡层60能够通过与阻挡层20相同的工艺形成。在一些实施例中,第二阻挡层60的厚度在约2nm至约7nm的范围内。
在阻挡层60形成之后,形成第二金属层,并且设置在第二ILD层50的上表面上的阻挡层60和第二金属层的上部部分通过CMP去除,如图12所示。第二金属层35能够通过与金属层30类似的工艺形成。
进一步地,通过使用针对图6和图7的类似操作,第二2D材料层70形成在第二金属层35的上表面上。
如图13所示,在沿着X方向的截面中,金属配线图案WP2的顶部被2D材料层70覆盖,并且金属配线图案WP2的侧面和底部中的至少一个被阻挡层20或60覆盖。在一个实施例中,2D材料保持在下方金属层30的上表面处。
随后,第三ILD层和第二ESL可形成在配线图案WP2上方。
图14至图17示出了根据本公开另一实施例的用于制造半导体器件的顺序工艺的示例性截面图。上面针对图1至图13提出的类似或相同配置、工艺、材料和/或结构可在下面实施例中被采用,因而可省略详细解释。应当理解,能够在图14至图17示出的工艺之前、期间和之后提供另外的操作,并且对于方法的额外实施例,以下描述的一些操作能够被替换或删除。操作/工艺的顺序可以是互换的。
在图1至图13的实施例中,诸如TiN的导电材料被作用阻挡层。在下面的实施例中,在形成诸如Cu层的金属层之前2D材料层被用作阻挡层。
在如图2所示形成凹槽层15之后,2D材料层25形成在第一ILD层10上方和凹槽15内部,如图14所示。
在一个实施例中,2D材料层25包括石墨烯。石墨烯层能够使用甲烷气体、乙烷气体、丙烷气体或者其他碳氢化合物气体中的一个或多个与氢气一起通过热CVD或等离子CVD形成。石墨烯层能够是单层或多层结构。在用于形成石墨烯的操作中,衬底温度被调整以使得在没有催化剂的情况下形成石墨烯,并因此石墨烯层能够形成在第一ILD层10上方以及凹槽15内部,如图14所示。
通过CVD、PVD和/或ALD形成的诸如TMD或BN的其他2D材料能够被用作2D材料层25。
在一些实施例中,2D材料层25的厚度在约0.3nm至约5nm的范围内。
如图15所示,在通过实施关于图4至图7的相关或类似操作使用2D材料层形成阻挡层25之后,在金属层30的表面上形成2D材料层40。
如图15所示,在沿X方向的截面中,金属配线图案WP3的顶部被2D材料层40覆盖,并且金属配线图案WP3的侧边和底部中至少一个还被2D材料25覆盖。2D材料层25可与2D材料层40相同或不同。在一个实施例中,金属配线图案WP3的侧边和底部被2D材料层覆盖。
随后,通过实施关于图8至图10的相同或类似操作,在第二ILD层50和ESL 45中形成开口55。进一步地,如图16所示,形成作为第二阻挡层的第二2D材料层65。第二2D材料层65可与2D材料层25和/或40相同或不同。
在一个实施例中,第二2D材料层65由石墨烯制成,并且石墨烯层65能够选择性地形成在第二ILD层50(即,绝缘材料层)的表面上。通过调整沉积条件(例如,温度),能够区分石墨烯在金属表面和电介质表面上的沉积速率(例如,在电介质表面上的沉积速率快于在金属表面上的沉积速率),因而实现石墨烯在第二ILD层50上的选择性沉积。
在一些实施例中,第二2D材料层65的厚度在约0.3nm到约5nm的范围内。
然后,通过实施关于图12和图13的相同或类似的操作,形成如图17所示的金属配线图案WP4。2D材料层70可与2D材料层25、40和/或65相同或不同。
如图7所示,在沿X方向的截面中,金属配线图案WP4的顶部被2D材料层70覆盖,并且金属配线图案WP4的侧面和底部中的至少一个还被2D材料层25或65覆盖。在一个实施例中,金属配线图案WP4的侧边和底部被2D材料层覆盖。
随后,第三ILD层和第二ESL可形成在配线图案WP4上方。
图18至图23示出了根据本公开另一实施例的用于制造半导体器件的顺序工艺的截面视图。如上阐述的针对图1至图17的类似或相同配置、工艺、材料和/或结构可在下面的实施例中被使用,因此可省略详细解释。应当理解,在图18至图23示出的工艺之前、期间和之后能够提供另外的操作,并且对于方法的额外实施例,以下描述的一些操作能够被替换或删除。操作/工艺的顺序可以是互换的。
在凹槽15被如图2所示形成后,凹槽的下部部分被填充有导电材料80,如图18所示。导电材料包括Co、Cu、Ru、W、Ni、Ti、TiN、Ta、TaN或者硅化物的一层或多层。导电材料能够通过使用选择性的无极电镀方法或选择性的CVD方法被部分填充在凹槽中。导电材料层80可包括阻挡层(未示出)和主体导电层。
当凹槽15具有通孔部和配线部时,通孔部被填充有导体材料80。当凹槽15是通孔或者配线图案时,凹槽被填充至通孔深度的约40%到约60%的水平。
在特定实施例中,通孔部通过镶嵌工艺形成,而额外的ILD层形成在通孔部上方。然后,凹槽15被形成在另外的ILD中以暴露通孔部的上表面。
然后,与图3类似,阻挡层21被形成为如图19所示。
随后,通过关于图4和图5的相同或类似操作,凹槽15的上部被填充有金属层31,如图20所示。
然后,通过关于图6和图7的相同或类似操作,2D材料层41被形成在金属层31的上表面上,如图21所示。
如图21所示,配线图案WP5包括上部和导电材料制成的下部。在沿X方向的截面中,上部的顶部被2D材料层41覆盖,并且上部的侧面和底部中的至少一个被由导电材料制成的阻挡层21覆盖,且导电材料不同于2D材料层41。在一个实施例中,上部的侧面和底部被阻挡层21覆盖。
随后,与图8至图10类似,开口57被形成在第二ILD层50和ESL 45中,如图22所示。然后,与图18相类似,开口57的底部被填充有导电材料85,并且第二阻挡层61和第二金属层36被形成为与图19和图20相类似。进一步地,第二2D材料层71被形成为如图23所示。
如图23所示,配线图案WP6具有下部配线图案以及上部配线图案,每一个包括上部和由导电材料制成的下部。在沿着X方向的截面中,上部配线图案的上部的顶部被2D材料层71覆盖,并且其上部的侧边和底部中至少一个由导电材料制成的阻挡层61覆盖,并且导电材料与2D材料层71不同。在一个实施例中,上部的侧边和底部被阻挡层61覆盖。2D材料层41可与2D材料层61相同或不同。
在一些实施例中,配线图案WP6中的下部配线图案和上部配线图案的任一个具有与配线图案WP1或WP3相同或类似的结构。
随后,第三ILD层和第二ESL可被形成在配线图案WP6上方。
图24至图25示出了根据本公开另一实施例的用于制造半导体器件的顺序工艺的截面视图。在下面实施例中可采用如上面关于图1至图23阐述的相似或相同配置、工艺、材料和/或结构,并且省略了详细描述。应当理解,在图24至图25示出的工艺之前、之间和之后能够提供另外的操作,并且对于方法的额外实施例,以下描述的一些操作能够被替换或删除。操作/工艺的顺序可以是互换的。
在凹槽15的下部如图18所示被填充之后,2D材料层26共形地(非选择性的方式)被形成为阻挡层,如图24所示。在该沉积操作中,因为被填充在凹槽15上的导电材料不用作催化剂,因此2D材料层26能够被形成在ILD 10B和导电层80上。
然后,金属层31被形成为与图20相似,并且2D材料层41被形成在金属层31的表面上,与图21类似。随后,与图22至图23相似,开口被形成在第二ILD层50和ESL 45中,并且然后,开口的底部被填充有导电材料。
然后,作为第二阻挡层,第二2D材料层66被形成为与图24相似,且第二金属层36被形成。进一步,第二2D材料层71被形成为如图25所示。
如图25所示,配线图案WP7包括上部和由导电材料制成的下部。在沿着X方向的截面中,上部的顶部被2D材料层41覆盖,且上部的侧边和底部中至少一个被2D材料层26覆盖。2D材料层26和2D材料层41可以彼此相同或不同。在一个实施例中,上部的侧边和底部被2D材料层覆盖。
进一步,如图25所示,配线图案WP8具有下方配线图案和上方配线图案,每一个包括上部和由导电材料制成的下部。在沿X方向的截面中,上方配线图案的上部中的顶部被2D材料层71覆盖,且其上部的侧边和底部中至少一个被2D材料层66覆盖。在一个实施例中,上部的侧边和底部被2D材料层66覆盖。2D材料层71可与2D材料层26、41和/或61相同或不同。
在一些实施例中,配线图案WP8的下方配线图案和上方配线图案中的任一个具有与配线图案WP1、WP3或者WP5相同或相类似结构。
随后,第三ILD层和第二ESL可以被形成在配线图案WP8上方。
在此描述的各种实施例或实例提供了优于现有技术的优势。例如,在本公开中,由于二维材料层至少覆盖在金属配线层(例如,Cu层)的表面上,因此减少在金属配线层处的表面散射以及减少电阻率(例如,配线电阻率)是可能的。进一步地,增加金属配线层中的最大电流密度是可能的。
应当理解,不是所有优点都已在此有必要讨论,对于所有实施例或实例不需要特别的优点,并且其他实施例或实例可提供不同的优点。
根据本公开的一个方面,一种半导体器件包括:第一层间介电(ILD)层,设置在衬底上方;以及第一金属配线图案,形成在第一层间介电层中并且沿着与衬底平行的第一方向延伸。在沿横穿(例如,垂直于)第一方向且与衬底平行的第二方向的截面中,第一金属配线图案的顶部被第一二维材料层覆盖。
根据本发明的实施例,第一二维材料层包括石墨烯。
根据本发明的实施例,第一二维材料层包括过渡金属硫族化合物(TMD)。
根据本发明的实施例,过渡金属硫族化合物包括MoS2、WS2和NbSe2中的一者。
根据本发明的实施例,第一二维材料层包括BN。
根据本发明的实施例,在截面中,第一金属配线图案的侧面和底部被第一二维材料层覆盖。
根据本发明的实施例,在截面中,第一金属配线图案的侧面和底部被由与第一二维材料层不同的导电材料制成的阻挡金属层覆盖。
根据本发明的实施例,在截面中,第一金属配线图案的侧面和底部被由与第一二维材料层不同的二维材料制成的第二二维材料层覆盖。
根据本发明的实施例,第一金属配线图案包括通孔部分和配线部分。
根据本公开的另一方面,一种半导体器件包括:第一层间介电(ILD)层,设置在衬底上方;第一金属配线图案,形成在第一层间介电层中并且沿着平行于衬底的第一方向延伸;第二ILD层,设置在第一ILD层和第一金属配线图案上方;以及第二金属配线图案,形成在第二ILD层中并且连接到第一金属配线图案。在沿横穿(例如,垂直于)第一方向并且与衬底平行的第二方向的截面中,第二金属配线图案的顶部被第一二维材料层覆盖。
根据本发明的实施例,第一二维材料层包括石墨烯。
根据本发明的实施例,第一二维材料层包括过渡金属硫族化合物(TMD)。
根据本发明的实施例,过渡金属硫族化合物包括MoS2、WS2和NbSe2中的一者。
根据本发明的实施例,第一二维材料层包括BN。
根据本发明的实施例,在截面中,第一金属配线图案的侧面和底部被第一二维材料层覆盖。
根据本发明的实施例,在截面中,第一金属配线图案的顶部的一部分被第二二维材料层覆盖。
根据本发明的实施例,第一二维材料层的材料与第二二维材料层的材料相同。
根据本发明的实施例,在截面中,第二配线图案的侧面以及第一金属配线图案的侧面和底部被第一二维材料层覆盖。
根据本发明的实施例,在截面中,第二配线图案的侧面以及第一金属配线图案的侧面和底部,被由与第一二维材料层不同的导电材料制成的阻挡金属层覆盖。
根据本公开的另一方面,一种制造半导体器件的方法包括:在衬底上方形成第一层间介电层。在第一层间介电层中形成第一凹槽。在第一凹槽中形成金属配线图案。在金属配线图案的顶部上形成二维材料层。
前面概述了若干实施例或实例的特征,使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解,他们可以容易地使用本公开作为用于设计或修改用于执行与本公开的实施例或实例相同或类似的目的和/或实现相同或类似优点的其它工艺和结构的基础。本领域的技术人员还应该意识到,这种等效结构不背离本公开的精神和范围,并且可以进行各种改变、替换和变更而不背离本公开的精神和范围。
Claims (10)
1.一种半导体器件,包括:
第一层间介电(ILD)层,设置在衬底上方;以及
第一金属配线图案,形成在所述第一层间介电层中并且沿着与所述衬底平行的第一方向延伸,其中:
在沿横穿所述第一方向且与所述衬底平行的第二方向的截面中,所述第一金属配线图案的顶部被第一二维材料层覆盖。
2.根据权利要求1所述的半导体器件,其中,所述第一二维材料层包括石墨烯。
3.根据权利要求1所述的半导体器件,其中,所述第一二维材料层包括过渡金属硫族化合物(TMD)。
4.根据权利要求3所述的半导体器件,其中,所述过渡金属硫族化合物包括MoS2、WS2和NbSe2中的一者。
5.根据权利要求1所述的半导体器件,其中,所述第一二维材料层包括BN。
6.根据权利要求1所述的半导体器件,其中,在所述截面中,所述第一金属配线图案的侧面和底部被所述第一二维材料层覆盖。
7.根据权利要求1所述的半导体器件,其中,在所述截面中,所述第一金属配线图案的侧面和底部被由与所述第一二维材料层不同的导电材料制成的阻挡金属层覆盖。
8.根据权利要求1所述的半导体器件,其中,在所述截面中,所述第一金属配线图案的侧面和底部被由与所述第一二维材料层不同的二维材料制成的第二二维材料层覆盖。
9.一种半导体器件,包括:
第一层间介电(ILD)层,设置在衬底上方;
第一金属配线图案,形成在所述第一层间介电层中并且沿着平行于所述衬底的第一方向延伸;
第二层间介电层,设置在所述第一层间介电层和所述第一金属配线图案上方;以及
第二金属配线图案,形成在所述第二层间介电层中并且连接到所述第一金属配线图案,其中:
在沿横穿所述第一方向并且与所述衬底平行的第二方向的截面中,所述第二金属配线图案的顶部被第一二维材料层覆盖。
10.一种制造半导体器件的方法,包括:
在衬底上方形成第一层间介电层;
在所述第一层间介电层中形成第一凹槽;
在所述第一凹槽中形成金属配线图案;以及
在所述金属配线图案的顶部上形成二维材料层。
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