CN103579181A - 混合互连设计及其形成方法 - Google Patents

混合互连设计及其形成方法 Download PDF

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CN103579181A
CN103579181A CN201210575923.0A CN201210575923A CN103579181A CN 103579181 A CN103579181 A CN 103579181A CN 201210575923 A CN201210575923 A CN 201210575923A CN 103579181 A CN103579181 A CN 103579181A
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dielectric
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barrier layer
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conductive barrier
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CN103579181B (zh
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余振华
包天一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了混合互连设计及其形成方法，其中一种器件包括第一低k介电层以及位于第一低k介电层中的含铜通孔。该器件还包括位于第一低k介电层上方的第二低k介电层以及位于含铜通孔上方并与其电连接的含铝金属线。含铝金属线位于第二低k介电层中。

Description

混合互连设计及其形成方法
技术领域
本发明总的来说涉及半导体领域，更具体地，涉及混合互连设计及其形成方法。
背景技术
现代集成电路由形成在半导体衬底上的晶体管、电容器以及其他器件组成。在衬底上，这些器件最初是彼此分离的，但稍后互接到一起来形成功能电路。典型的互连结构包括诸如金属线(配线)的横向互连以及诸如通孔和接触件的垂直互连。互连结构的质量影响所制造电路的性能和可靠性。互连件越来越多地决定现代集成电路的性能和密度的限制。
互连结构可包括钨插塞和铝线。在新一代的集成电路中，包括使用双镶嵌工艺形成的铜线和通孔的双镶嵌结构也被用于形成互连结构。
发明内容
根据本发明的第一方面，提供了一种器件，包括：第一低k介电层；位于第一低k介电层中的含铜通孔；位于第一低k介电层上方的第二低k介电层；以及所述含铜通孔上方并与含铜通孔电连接的含铝金属线，其中含铝金属线位于第二低k介电层中。
优选地，该器件还包括导电势垒层，其中导电势垒层包括：位于含铜通孔下方的底部；以及位于含铜通孔的侧壁上的侧壁部分。
优选地，导电势垒层是非含铜层。
优选地，该器件还包括位于含铝金属线和含铜通孔之间的非含铝导电势垒层，其中，非含铝导电势垒层和含铝金属线共界。
优选地，该器件还包括介电势垒层，介电势垒层包括：位于含铝金属线的侧壁上的第一部分；以及与含铝金属线重叠的第二部分。
优选地，介电势垒层的第二部分包括与含铝金属线的顶面接触的底面。
优选地，该器件还包括位于含铝金属线上方并与含铝金属线接触的附加非含铝导电势垒层，其中，介电势垒层的第二部分包括与附加非含铝导电势垒层的顶面接触的底面。
优选地，该器件还包括：位于第二低k介电层上方的第三低k介电层；以及位于第三低k介电层中的金属线和通孔，其中，金属线和通孔形成双镶嵌结构。
根据本发明的第二方面，提供了一种器件，包括：第一低k介电层；位于第一低k介电层中的第一含铜通孔；位于第一低k介电层上方的第二低k介电层；以及位于第二低k介电层中并且电连接至第一含铜通孔的第一导线。第一导线包括：第一导电势垒层；和位于第一导电势垒层上方的第一含铝金属线；并且介电势垒层包括：位于第一含铝金属线的侧壁上的第一部分；与第一含铝金属线重叠的第二部分；以及位于第二低k介电层下方的第三部分。
优选地，该器件还包括位于第二低k介电层上方的多个金属层，其中位于第二低k介电层上方和低k介电层中的所有金属层均与对应下方的通孔形成双镶嵌结构。
优选地，该器件还包括：位于第一低k介电层下方的第三低k介电层；位于第三低k介电层中的第二含铜通孔，其中，第二含铜通孔具有单镶嵌结构；位于第一低k介电层和下方的第三低k介电层下方的第四低k介电层；以及位于第四低k介电层中的第二导线，其中，第二导线包括第二导电势垒层和位于第二导电势垒层上方的第二含铝金属线。
优选地，介电势垒层包括与第一低k介电层的顶面接触的底面。
优选地，该器件还包括位于第一低k介电层和第二低k介电层之间的蚀刻终止层，其中，介电势垒层包括：与蚀刻终止层的顶面接触的底面；以及与第二低k介电层的底面接触的顶面。
优选地，第一导电势垒层的边缘与第一含铝金属线的对应边缘对齐。
根据本发明的又一方面，提供了一种方法，包括：利用单镶嵌工艺在第一低k介电层中形成第一通孔；在第一通孔上方沉积含铝层；图案化含铝层以形成含铝线，其中含铝线电连接至第一通孔；以及在第一低k介电层上方形成第二低k介电层，其中，含铝线位于第二低k介电层中。
优选地，该方法还包括：在沉积含铝层之前，在第一低k介电层上方形成导电势垒层，其中，导电势垒层和含铝层被图案化为共界。
优选地，该方法还包括：在沉积含铝层之后，在含铝层上方形成导电势垒层，其中，导电势垒层和含铝层被图案化为共界。
优选地，该方法还包括：在图案化含铝层的步骤之后以及在形成第二低k介电层的步骤之前，形成介电势垒层，其中介电势垒层包括：位于含铝层的侧壁上的第一部分；以及与含铝层重叠的第二部分。
优选地，该方法还包括：在第二低k介电层上方形成第三低k介电层；以及执行双镶嵌工艺，包括在第三低k介电层中形成通孔开口和沟槽开口、在通孔开口和沟槽开口中填充含金属材料；和对含金属材料执行化学机械抛光(CMP)，其中，含金属材料的剩余部分在通孔开口中形成第二通孔以及在沟槽中形成金属线。
优选地，该方法还包括：在第一低k介电层和第二低k介电层之间形成蚀刻终止层；以及在沉积含铝层的步骤之前，图案化蚀刻终止层以去除蚀刻终止层与第一通孔重叠的部分。
附图说明
为了更完整地理解本实施例及其优点，现在结合附图作为参考进行下面的描述，其中：
图1至11是根据一些示例性实施例的制造互连结构的中间阶段的截面图。
具体实施方式
下面详细讨论本发明实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中具体化的可应用发明概念。所讨论的具体实施例是说明性的但不限制本发明的范围。
根据各种示例性实施例提供了互连结构及其形成方法。示出了形成互连结构的中间阶段。讨论了实施例的变化。在各个视图和说明性实施例中，类似的参考标号用于表示类似的元件。
图1示出了晶圆100，其包括半导体衬底10。半导体衬底10可由硅、锗、锗硅、III-V化合物半导体等形成。诸如晶体管、电容器、电阻器等的有源和无源器件12可形成为与半导体衬底10的顶面相邻。
图1还示出了层间介电层(ILD)14和接触插塞16的形成。可利用磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等形成ILD 14。可包括钨的接触插塞16可形成在ILD 14中并连接至器件12。介电层20形成在ILD 14上方。介电层20可选地被称为金属间介电(IMD)层。在一些实施例中，IMD层20包括低k介电材料，其具有低于3.9的介电常数(k值)。IMD层20的k值可还低于约3.0，或低于约2.5。
金属线22形成在IMD层20中。在说明书中，IMD层中的金属线被统称为金属层。因此，金属线22位于底部金属层M1中。可利用单镶嵌工艺形成金属线22，其与图1和图2所示的工艺类似。在一些实施例中，通过沉积和蚀刻含铝层(例如AlCu)并图案化含铝层来形成金属线22。在可选实施例中，利用单镶嵌工艺形成金属线22，因此其可包括势垒层22A以及位于势垒层22A上方的含铜层22B。势垒层22A可包括钛、氮化钛、钽、氮化钽或其他可选物质。例如，金属线22可具有约10nm和约50nm之间的厚度T1以及约8nm和约30nm之间的宽度W1。
再次参照图1，IMD层24形成在IMD 20上方。在一些实施例中，IMD层24具有低于约3.5的介电常数(k值)，因此其在说明中被称为低k IMD层24。低k IMD层24的k值还可低于约2.8。在一些实施例中，低k IMD层24包括氧、硅、氮等。示例性材料包括含碳材料、有机硅酸盐玻璃、含致孔剂材料等。可在低k IMD层24中形成孔隙以降低其k值。可利用诸如等离子体增强CVD(PECVD)的CVD方法来沉积低k IMD层24，尽管也可以使用诸如低压CVD(LPCVD)、原子层CVD(ALCVD)以及旋涂的其他沉积方法。
图1和图2示出了单镶嵌工艺。在图1中，通过蚀刻IMD层24来在低k IMD层24中形成通孔开口26。在一些实施例中，在IMD层24下方和IMD层20上方形成蚀刻终止层(未示出)，其中，蚀刻终止层可包括氮、基于硅和碳的电介质、掺杂碳的氧化物等。
图2示出了填充通孔开口26以形成通孔32。在一些实施例中，首先形成扩散势垒层28，其是部分位于通孔开口26中以及部分位于IMD层24上方的覆盖层。然后，在扩散势垒层28上方形成种子层(未示出，与含铜材料30结合)，之后通过电镀步骤来形成含铜材料30，直到含铜材料的顶面高于低k IMD层24的顶面。扩散势垒层28可包括钛、氮化钛、钽、氮化钽，或其他可选物质。在一些示例性实施例中，含铜材料30可包括超过90原子百分比、超过95原子百分比、或超过99原子百分比的铜。接下来，执行化学机械抛光(CMP)以去除位于低k IMD层24上方的含铜材料30和扩散势垒层28的过量部分，留下IMD层24中的通孔32。
接下来，如图3所示，可由氮化硅、碳化硅等形成的ESL 34形成在IMD层24和通孔32上方。在可选实施例中，不形成ESL 34。例如，ESL 34可具有约2nm和约20nm之间的厚度T8。接下来，参照图4，在沉积和图案化工艺中形成导电层叠层，其包括导电势垒36和含铝层38。在一些实施例中，导电势垒层40还形成在含铝层38上。在可选实施例中，不形成导电势垒层40。导电势垒层36和40(如果有的话)可包括钛、氮化钛、钽、氮化钽，或其他可选物质。在一些示例性实施例中，含铝层38可包括超过90原子百分比、超过95原子百分比、或超过99原子百分比的铜。然后，图案化叠层以形成金属线42，其电连接至对应下方的通孔32(并且可以与其接触)。由于使用相同的光刻掩模图案化层36、38和40，所以层36、38和40是共界的，层36、38和40的相应边缘彼此对准。在说明书中，金属线42被统称为金属层M2。在图案化步骤中，ESL 34和/或导电势垒36可用作蚀刻终止层。在说明书中，由包括单镶嵌工艺以及沉积和图案化工艺的混合工艺形成的通孔32和上覆金属线42的组合被称为复合结构。导电势垒36可具有约1nm和约20nm之间的厚度T2。含铝层38可具有约10nm和50nm之间的厚度T3。导电势垒层40可具有约1nm和约20nm之间的厚度T4。例如，金属线42可具有约8nm和约30nm之间的宽度W2。
图5示出了介电势垒44的形成，其包括位于金属线42侧壁上的侧壁部分、与金属线42重叠的顶部以及位于ESL 34上的下部。介电势垒44可具有约1nm和约20nm之间的厚度T5。在没有形成导电势垒层40的实施例中，介电势垒44的顶部接触金属线42中的含铝层38的顶面。另外，如果形成导电势垒层40，则导电势垒44的顶部接触金属线42中的导电势垒层40的顶面。介电势垒44可由AlOx、AlNx、SiCN、SiN等形成，其中x的值在0和1之间。例如，利用原子层沉积(ALD)形成介电势垒44。
图6示出了IMD层46的形成。IMD层46的材料可从形成IMD层24和/或IMD层20的可用材料的相同组中选择。在一些实施例中，利用具有低k值的旋涂介电层(SOD)形成IMD层46。在可选实施例中，可利用化学气相沉积(CVD)方法形成IMD层46，诸如PECVD、LPCVD、ALCVD等。作为CVD方法的结果，可在IMD层46中形成孔隙48，而且邻近的孔隙48之间可以减小IMD层46的有效k值，并且减小金属线42之间的寄生电容。在利用CVD方法形成IMD层46的实施例中，可执行CMP或研磨以使IMD层46的顶面变平。在利用SOD形成IMD层46的实施例中。可以执行或者可以省略CMP或研磨步骤。IMD层46的顶面高于金属线42的顶面和介电势垒层44的顶部。
在图7中，利用单镶嵌工艺形成通孔50，其形成基本上可与图1和图5所示相同。通孔50形成在IMD层46中，并且电连接至下面的金属线42。通孔50穿透介电层44以电连接至金属线42。在随后的步骤中，如图8所示，形成金属线52，其中形成工艺可与金属线42的形成基本相同。然后可以形成介电势垒层47，例如利用与介电势垒层44类似的材料和类似的厚度。金属线52统称为金属层M3。每条金属线52都包括导电势垒层54和位于导电势垒层54上方的含铝层56。例如，含铝层56可具有约10nm和约50nm之间的厚度T6以及约8nm和约30nm之间的宽度W3。利用与导电势垒层36和含铝层38基本相同的方法和相同的材料可分别形成导电势垒层54和含铝层56。在所示实施例中，在IMD层46上方和介电层47下方不形成ESL，尽管可形成ESL(未示出)，其中可利用与ESL 34类似的材料和类似的厚度形成ESL。此外，在所示实施例中不形成导电势垒层，尽管类似于导电势垒层40的导电势垒层还可形成在含铝层56上方并与其邻接。
图9和图10示出了直到顶部金属层Mtop(请参照图10)(其是形成在低k介电层中的最顶部的金属层)的剩余低k介电层的形成。例如，术语“Mtop”中的符号“top”代表整数，其可以是约3和约10之间的任意整数。因此，金属层Mtop下方的金属层称为金属层Mtop-1。在一些实施例中，金属层M2至Mtop的每一层和对应下方的通孔都具有混合结构。混合结构包括利用单镶嵌工艺形成的通孔和位于通孔上方并与其接触的含铝金属线，其中利用沉积和图案化而不是单镶嵌或双镶嵌工艺形成含铝金属线。在可选实施例中，下部的金属层M2至Mn(未示出)的每一层和对应下方的通孔形成混合结构，而利用双镶嵌工艺形成上部金属层M(n+1)(未示出)至Mtop的每一层，其中整数n可以是2和(top-1)之间并包括2和(top-1)的任意整数。例如，图9和图10示意性示出了用于形成上部金属层的双镶嵌工艺。
参照图9，形成作为低k介电层的IMD层58。接下来，利用蚀刻工艺在IMD层58中形成通孔开口60和沟槽62。接下来，如图10所示，填充通孔开口60和沟槽62，然后为CMP工艺。填充材料可包括导电势垒层64和位于导电势垒层64上方的导电材料66。导电材料64可由钛、氮化钛、钽、氮化钽等形成。例如，导电势垒层64的厚度T7可在约5nm和约50nm之间。导电材料66可包括铜或铜合金。作为填充步骤和CMP步骤的结果，通孔68和金属线70分别形成在通孔开口60和沟槽62中。例如，金属线70可具有约100nm和约5000nm之间的厚度T9以及约50nm和约5000nm之间的宽度W4。
图11示出了非低k介电层72的形成，其可以由氧化硅、氮化硅、未掺杂的硅酸盐玻璃等形成。金属布线(未示出)可在非低k介电层72中形成，并通过Mtop电连接至下面的金属层M1。
在实施例中，互连结构中的金属线可包括含铝金属线。主要由铝形成的含铝线(当其具有约40nm和50nm之间或更小的线宽时)可具有比具有相同宽度的铜线更小的线阻。此外，通过进一步减小铝线的线宽，铝线的线阻和铜线的线阻(具有相同的宽度)之间的差异随着线宽的逐渐减小而变大。因此，当线宽较小时，采用铝线可减小线阻并减小RC延迟。另一方面，当通过沉积和图案化形成铝线时，利用单镶嵌工艺而不是双镶嵌工艺形成下面的通孔。因此，空隙填充到通孔开口中比双镶嵌工艺中的空隙填充到沟槽和通孔开口更加容易。
此外，诸如金属层Mtop的上部金属层可具有比下面的金属层更宽的线宽。因此，上部金属层可采用双镶嵌工艺，上部金属层中的金属线包括铜线，而下部金属线可采用混合结构。因此，优化了上部金属层和下部金属层的线阻值。
根据实施例，一种器件包括第一低k介电层以及位于第一低k介电层中的含铜通孔。该器件还包括位于第一低k介电层上方的第二低k介电层以及位于含铜通孔上方并与其电连接的含铝金属线。含铝金属线位于第二低k介电层中。
根据其他实施例，一种器件包括第一低k介电层、位于第一低k介电层中的第一含铜通孔、位于第一低k介电层上方的第二低k介电层以及位于第二低k介电层中并电连接至第一含铜通孔的导线。导线包括导电势垒层以及位于导电势垒层上方的含铝金属线。介电势垒层包括位于含铝金属线侧壁上的第一部分、与含铝金属线重叠的第二部分以及位于第二低k介电层下方的第三部分。
根据其他实施例，一种方法包括：利用单镶嵌工艺在第一低k介电层中形成第一通孔；在第一通孔上方沉积含铝层；以及图案化含铝层以形成含铝线。含铝线电连接至第一通孔。在第一低k介电层上方形成第二低k介电层，其中含铝线在第二低k介电层中。
尽管已经详细描述了实施例及其优点，但应该理解，可以进行各种改变、替换和更改而不背离所附权利要求限定的实施例的精神和范围。此外，本申请的范围不旨在限于说明中描述的工艺、机械装置、制造、以及物质组成、工具、方法和步骤的特定实施例。本领域技术人员容易理解，根据本公开可以利用与本文描述的对应的实施例执行基本相同的功能或实现基本相同的结果的目前现有或即将开发的工艺、机械装置、制造、以及物质组成、工具、方法或步骤。因此，所附权利要求旨在包括在这种工艺、机械装置、制造、以及物质组成、工具、方法或步骤的范围。此外，每个权利要求构成独立的实施例，并且各种权利要求和实施例的组合均在本公开的范围内。

Claims (10)

1.一种器件，包括：
第一低k介电层；
位于所述第一低k介电层中的含铜通孔；
位于所述第一低k介电层上方的第二低k介电层；以及
位于所述含铜通孔上方并与所述含铜通孔电连接的含铝金属线，其中所述含铝金属线位于所述第二低k介电层中。
2.根据权利要求1所述的器件，还包括导电势垒层，其中，所述导电势垒层包括：
位于所述含铜通孔下方的底部；以及
位于所述含铜通孔的侧壁上的侧壁部分。
3.根据权利要求2所述的器件，其中，所述导电势垒层是非含铜层。
4.根据权利要求1所述的器件，还包括位于所述含铝金属线和所述含铜通孔之间的非含铝导电势垒层，其中，所述非含铝导电势垒层和所述含铝金属线共界。
5.根据权利要求1所述的器件，还包括介电势垒层，所述介电势垒层包括：
位于所述含铝金属线的侧壁上的第一部分；以及
与所述含铝金属线重叠的第二部分。
6.根据权利要求5所述的器件，其中，所述介电势垒层的第二部分包括与所述含铝金属线的顶面接触的底面。
7.根据权利要求5所述的器件，还包括位于所述含铝金属线上方并与所述含铝金属线接触的附加非含铝导电势垒层，其中，所述介电势垒层的第二部分包括与所述附加非含铝导电势垒层的顶面接触的底面。
8.根据权利要求1所述的器件，还包括：
位于所述第二低k介电层上方的第三低k介电层；以及
位于所述第三低k介电层中的金属线和通孔，其中，所述金属线和所述通孔形成双镶嵌结构。
9.一种器件，包括：
第一低k介电层；
位于所述第一低k介电层中的第一含铜通孔；
位于所述第一低k介电层上方的第二低k介电层；以及
位于所述第二低k介电层中并且电连接至所述第一含铜通孔的第一导线，所述第一导线包括：
第一导电势垒层；和
位于所述第一导电势垒层上方的第一含铝金属线；并且
介电势垒层包括：
位于所述第一含铝金属线的侧壁上的第一部分；
与所述第一含铝金属线重叠的第二部分；以及
位于所述第二低k介电层下方的第三部分。
10.一种方法，包括：
利用单镶嵌工艺在第一低k介电层中形成第一通孔；
在所述第一通孔上方沉积含铝层；
图案化所述含铝层以形成含铝线，其中所述含铝线电连接至所述第一通孔；以及
在所述第一低k介电层上方形成第二低k介电层，其中，所述含铝线位于所述第二低k介电层中。
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