CN105874595A - 铸模材料中的三维结构 - Google Patents

铸模材料中的三维结构 Download PDF

Info

Publication number
CN105874595A
CN105874595A CN201480026247.9A CN201480026247A CN105874595A CN 105874595 A CN105874595 A CN 105874595A CN 201480026247 A CN201480026247 A CN 201480026247A CN 105874595 A CN105874595 A CN 105874595A
Authority
CN
China
Prior art keywords
substrate
chip
passive structures
contact point
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480026247.9A
Other languages
English (en)
Other versions
CN105874595B (zh
Inventor
S·埃尔伯
A·沃尔特
K·雷因谷拉博
T·梅耶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Google LLC
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN105874595A publication Critical patent/CN105874595A/zh
Application granted granted Critical
Publication of CN105874595B publication Critical patent/CN105874595B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0033—Printed inductances with the coil helically wound around a magnetic core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/04—Fixed inductances of the signal type  with magnetic core
    • H01F17/045—Fixed inductances of the signal type  with magnetic core with core of cylindric geometry and coil wound along its longitudinal axis, i.e. rod or drum core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/02—Casings
    • H01F27/022—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F2017/004—Printed inductances with the coil helically wound around an axis without a core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/06—Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
    • H01F2027/065—Mounting on printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

一种方法，包括通过堆积工艺在基板上形成至少一个无源结构；在基板上引入一个或多个集成电路芯片；以及在至少一个无源结构和一个或多个集成电路芯片上引入铸模材料。一种方法，包括通过三维印刷工艺在基板上形成至少一个无源结构；在基板上引入一个或多个集成电路芯片；以及在铸模材料中内嵌所述至少一个无源结构和所述一个或多个集成电路芯片。一种装置，包括封装基板，包括内嵌于铸模材料中的至少一个三维印刷无源结构和一个或多个集成电路芯片。

Description

铸模材料中的三维结构
背景
领域
集成电路封装。
相关技术说明
更高水平集成度和更低的成本要求驱使着元件的集成，诸如系统级封装“SiP”解决方案。在这方面，尺寸的减小和成本的降低以及功能的增加是主要的推动力。
附图说明
图1示出了包括粘合层及粘合层上接触点的牺牲载体的侧面剖视图。
图2示出了在粘合层上形成无源结构并被连接至接触点之后图1的结构。
图3示出了在粘合层上引入两个集成电路芯片之后图2的结构。
图4示出了为嵌入无源结构和集成电路芯片在粘合层上引入铸模材料之后图3的结构。
图5示出了从载体移除内嵌于铸模材料中的结构之后图4的结构。
图6示出了为包括金属化层和接触点以及在接触点上放置焊料连接的其他晶片级处理之后图5的结构。
图7示出了以倒装芯片配置被连接至基板上的接触点的集成电路芯片。
图8示出了在基板上引入粉末材料以及形成无源结构的堆积或附加工艺之后图7的结构。
图9示出了通过附加或堆积工艺完成无源结构之后图8的结构。
图10示出了在移除未被电磁辐射熔化的用于形成无源结构的粉末之后图9的结构。
图11示出了在基板表面上引入铸模材料以将集成电路芯片和无源结构嵌入在铸模材料中之后图10的结构。
图12示出了在引入焊料连接至基板第二侧边上的接触点之后图11的结构。
图13示出了集成有集成电路芯片和纵向线圈的无源结构的封装。
图14示出了集成有集成电路芯片和在并排多线圈中以多线圈配置的多个线圈的封装结构。
图15示出了具有集成电路芯片和以多缠绕线圈水平配置的线圈的封装基板。
图16示出了具有多缠绕线圈纵向配置的封装结构。
图17示出了一种封装结构，其集成有集成电路芯片和以并排多线圈配置并具有置于线圈之间的例如磁性材料的芯的多个无源线圈。
图18示出了一种封装结构，其集成有集成电路芯片、以纵向多缠绕线圈配置并具有磁性材料串通其中的多个无源线圈、以及以水平多缠绕线圈配置并具有磁性芯串通其中的多个线圈。
图19示出了一种封装基板，其集成有集成电路芯片和多个无源结构，每个无源结构都带有互连，特别是例如铜材料的穿模导电过孔。
图20示出了集成有集成电路芯片和接地屏蔽的无源结构的封装基板。
图21示出了集成有集成电路芯片和天线的无源结构的封装基板。
图22示出了一种计算设备的实施例。
详细说明
本文描述了一种集成无源元件和有源电路元件，诸如封装中的集成电路芯片或多颗芯片的方法。有源电路元件是具有电气控制电子流动的能力的任何类型电路元件。本文中的无源元件或结构是不具有通过电气信号的方式控制电流的能力的元件或结构。无源元件或结构的示例包括电阻器、电容器、电感器、滤波器、平衡-不平衡变换器、收发器、接收器和/或互连、天线以及屏蔽。在一个实施例中，一种方法包括在基板上形成无源元件或结构，以及在基板上引入一个或多个有源电路元件(例如，一个或多个集成电路芯片)，随后在至少一个无源结构和一个或多个有源元件上引入铸模材料。在一个实施例中，在基板上形成无源结构是通过堆积工艺或加成工艺完成的。代表性地，三维加成工艺(例如，三维印刷工艺)被用以产生无源结构。三维加成工艺的典型代表是选择性熔化或烧结工艺，诸如选择性激光熔化系统或立体光刻工艺，其中例如，液体光聚合物被暴露至电磁能量以选择性地固化液体。简单或复杂的三维结构，例如线圈、天线、电阻器、或屏蔽可在封装过程之前或期间通过堆积或加成工艺(例如，逐层)被建造。另外，整个封装容积可被用以放置和创建额外的元件，这些元件增加了封装模组的功能和/或性能。通过采用使得整个封装容积可供有源和无源结构利用的方法，还能以二维无源结构无法实现的方式改善无源结构的电特性。最终，通过在完整的封装容积内实现无源元件或结构，封装的覆盖面积相比具有无源结构被并排贴装在印刷电路板上的封装可被制作得相对更小。
图1-6示出了一种产生封装的工艺流程的实施例，该封装包括至少一个无源结构和内嵌于封装容积中的一个或多个有源电路元件(例如，一个或多个集成电路芯片)的集成。在该实施例中，工艺流程采用了扇出晶片级键合技术，而内嵌于最终封装中的无源结构是线圈。图1示出了牺牲载体的侧面剖视图。举例而言，载体110是金属、聚合物或陶瓷材料，其具有足够为下一工艺操作提供功能的具有代表性的厚度(例如，毫米级厚度)。粘合剂层115被置于结构100的载体110表面上(如所见，为上表面)。在一个实施例中，粘合剂层115是层叠于载体110的双面粘合箔。在一个实施例中，可选接触点(诸如金属焊盘/表面，用于器件在结构上形成)被置于粘合层115上。
图2示出了在粘合层115上形成无源结构之后图1的结构，在该实施例中，该无源结构被连接至接触点120。在一个实施例中，无源结构130A、无源结构130B和无源结构130C分别都是通过堆积或加成工艺(例如，三维印刷工艺)形成的三维无源结构。图2将无源结构130A和无源结构130B示为水平放置线圈，而无源结构130C是纵向放置线圈。可以理解的是，线圈是结构的一种示例，其可通过堆叠或加成工艺(诸如3D印刷工艺)来构建。其他结构包括可构想的其他无源结构。
图3示出了在结构中引入两个集成电路芯片之后图2的结构。图3示出了附着于粘合层115的集成电路芯片140A和集成电路芯片140B。集成电路140A和集成电路芯片140B被置于粘合层115上未被无源结构130A-130C占据(例如，它们之间)的区域。图3特别示出了被置于无源结构130A和无源结构130C之间的集成电路芯片140A以及被置于集成电路芯片130B和集成电路芯片130C之间的集成电路芯片140B。在一个实施例中，集成电路芯片140A和集成电路芯片140B分别有一个器件侧边朝向粘合层115放置(如所见，器件侧朝下)。在另一实施例中，多芯片或管芯可被置于无源结构130A与130B和/或130B与130C之间。
图4示出了在粘合层上引入铸模材料以用于在其上嵌入无源结构和集成电路芯片之后图3的结构。图4示出了被置于粘合层115上并被引入用于嵌入无源结构130A-130C和集成电路芯片140A-140B的厚度的铸模材料150。在一个实施例中，适于铸模材料150的材料是诸如KE-G1250FC-20CU或填充有环氧树脂基铸模材料的铸模材料。
图5示出了从载体移除内嵌于铸模材料150中的结构之后图4的结构。在一个实施例中，通过增加热、化学或任意其他形式的能量来释放(分离)载体。图5示出了在释放基板110和粘合层115之后，包括内嵌于铸模材料150中的无源结构130A-130C和集成电路芯片140A-140B的结构100。
图6示出了在附加的晶片级处理之后的图5的结构。该工艺典型地包括清洁外露表面(由释放载体110而露出的表面)；引入例如聚酰亚胺、环氧树脂、聚苯并恶唑、共混物或类似材料的介电层160；形成开口或过孔至芯片或无源结构的接触点；引入籽晶和电镀及图案化再分布层170并引入阻焊材料180。图6还示出了作为预制球被印刷或放置的连接至再分布层190的接触点的焊料连接(焊球)。
图7-12示出了倒装封装中将三维无源结构结合一个或多个集成电路芯片的工艺流程的实施例。图7示出了以倒装芯片配置被连接至接触点或基板(封装或板)的集成电路芯片，诸如微处理器。结构200包括基板210，举例而言，该基板是无芯的或具有芯结构的基板，但也可以是模制的互连基板(MIS)或陶瓷基板。基板210包括在第一侧边上的接触点220和相对的第二侧边上的接触点225。集成电路芯片230被置于基板210上，并与接触点220相连。在一个实施例中，芯片230通过焊料连接(焊块)或铜柱被连接至基板210上的接触点220。可通过大规模回流或压接而附连这样的芯片。在倒装芯片配置中，芯片230以器件侧向下或朝向基板210的方式被附连至基板210。集成电路芯片230到基板210的连接可以是底部填充的。图7示出了例如聚合物材料的底部填充材料235。
图8示出了在基板210上与集成电路芯片203相邻的区域内引入粉末材料以及形成无源结构的堆积或加成工艺之后图7的结构。参照图8，在一个实施例中，通过依次引入粉末材料(材料颗粒)以及采用选择性电磁辐射熔化原理以在所期望的地方加热粉末并熔化(烧结)粉末，来形成无源结构。图8示出了一次一层被引入至基板210上的粉末240。具有代表性的，可通过从具有与基板210表面对齐的滚轴的粉末源中分散粉末(例如，导电颗粒)来完成这样的引入。一旦引入了一层粉末，电磁源被激活，而电磁辐射被施加在所期望的地方的粉末上。图8示出了电磁源250，其包括将电磁辐射260施加至所期望的粉末材料240颗粒上的扫描仪255。在一个实施例中，扫描仪255受控制器控制，该控制器包括非瞬态机器可读指令，该指令在执行时会在包含粉末的基板210区域中至少一个二维平面内(x和y方向)引起扫描仪255的移动，并在预设位置影响电磁辐射。
图9示出了完成引入和熔化粉末240以用于形成无源结构之后图8的结构。图9示出了水平线圈的无源结构245。如图9中所示，水平线圈和集成电路芯片230被粉末240内嵌或围绕。
图10示出了移除未被电磁辐射熔化的粉末240以用于形成无源结构之后图9的结构。图10示出了水平线圈的无源结构245，该水平线圈的无源结构245被置于基板210上并被连接至其表面上的接触点220(电气连接至基板210)。图11示出了在基板210表面上引入铸模或团状顶部材料以用于在铸模材料中嵌入集成电路芯片230和无源结构245之后图10的结构。
图12示出了在引入连接至基板210的第二侧边上的接触点225的焊料连接之后图11的结构。图12示出了连接至接触点225的焊料连接(焊块)260。
在上述实施例中，在基板上引入或放置芯片之后，无源结构被形成于封装基板上。在另一实施例中，可在将芯片放置或引入至封装基板上之前形成无源结构。
图13-21示出了与一个或多个集成电路芯片一起集成于封装中的无源结构的不同实施例。倒装芯片封装被用作示例实施例来阐释不同的无源结构。图13示出了集成有集成电路芯片330和纵向线圈的无源结构345的封装300。图14示出了集成有集成电路芯片430和在并排多线圈配置中以多线圈配置的线圈445A和445B的封装结构400。图15示出了集成有集成电路芯片530和以多缠绕线圈水平配置的线圈545A和线圈545B的封装基板500。图16示出了集成有集成电路芯片630和以多缠绕线圈纵向配置的线圈645A和线圈645B的封装结构600。
图17示出了封装结构700，其集成有集成电路芯片730和以并排多线圈配置并具有置于线圈之间的例如磁性材料的芯750的无源线圈745A和无源线圈745B。图18示出了封装结构800，其集成有集成电路芯片830、以纵向多缠绕线圈配置并具有磁性材料的芯850A串通其中的无源线圈845A和无源线圈845B、以及以水平多缠绕线圈配置并具有磁性芯850B串通其中的线圈845C和线圈845D。
图19示出了封装基板900，其集成有集成电路芯片930和无源结构945A、无源结构945B及无源结构945C，其中每个无源结构都带有互连，特别是例如铜材料的穿模导电过孔。这样的穿模过孔可分别被连接至基板910上的接触点。
图20示出了集成有集成电路芯片1030和接地屏蔽的无源结构1045的封装基板1000。
图21示出了集成有集成电路芯片1130和天线的无源结构1145的封装基板1100。
图22示出了根据一个实施例的计算设备1200。计算设备1200容纳有板1202。板1202可包括数个元件，包括但不限于处理器1204和至少一个通信芯片1206。处理器1204被物理及电气地耦接至板1202。在一些实现中，至少一个通信芯片1206也被物理及电气地耦接至板1202。在进一步的实现中，通信芯片1206是处理器1204的一部分。
根据其应用，计算设备1200可包括其他元件，所述其他元件可以或可以不物理及电气地连接至板1202。这些其他元件包括，但不限于，易失性存储器(例如DRAM)、非易失性存储器(例如ROM)、闪存、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、摄像机以及大容量存储设备(诸如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。
通信芯片1206实现对于去往和来自计算设备1200的数据传输的无线通信。术语“无线”及其衍生项可被用于描述可通过使用调制的电磁辐射经由非实体介质进行数据通信的电路、设备、系统、方法、技术、通信通道等。该术语并不表示相关设备不含有任何导线，尽管在一些实施例中，它们可能没有。通信芯片1206可实现多种无线标准或协议中的任一种，包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生，以及被指定为3G、4G、5G等的任何其他无线协议。计算设备1200可包括多个通信芯片1206。例如，第一通信芯片1206可专用于短距离无线通信，例如Wi-Fi和蓝牙，而第二通信芯片1206可专用于长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
计算设备1200的处理器1204包括封装在处理器1204中的集成电路管芯。术语“处理器”可指任何设备或设备的一部分，其处理来自寄存器和/或存储器的电子数据以将该电子数据转换成其他可被储存在寄存器和/或存储器中的电子数据。根据上述教导，在一些实现中，集成电路管芯可在封装中与无源结构一起被集成。
通信芯片1206还包括封装在通信芯片1206中的集成电路管芯。根据上述教导，在一些实现中，集成电路管芯可在封装中与无源结构一起被集成。
在进一步的实现中，容纳于计算设备1200中的另一元件可包含集成电路管芯，其包括一个或多个器件，诸如晶体管或金属互连。根据上述教导，在一些实现中，集成电路管芯可在封装中与无源结构一起被集成。
在不同的实现中，计算设备1200可以是手提电脑、上网本、笔记本、超级本、智能手机、平板、个人数字助理(PDA)、超级移动PC、移动电话、台式电脑、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数字录像机。在进一步的实现中，计算设备1200可以是任何其他处理数据的电子设备。
实例
示例1是一种方法，包括通过堆积工艺在基板上形成至少一个无源结构；在基板上引入一个或多个集成电路芯片；以及在至少一个无源结构和一个或多个集成电路芯片上引入铸模材料。
在示例2中，示例1方法中的基板包括牺牲基板，而在引入所述铸模材料之后，方法包括移除牺牲基板。
在示例3中，示例2方法中的每个所述至少一个无源结构和所述一个或多个集成电路芯片包括接触点，并且移除所述牺牲基板露出所述接触点，所述方法还包括将再分布层耦接至所述接触点。
在示例4中，引入示例1方法中的一个或多个芯片包括将一个或多个芯片的接触点耦接至基板的接触点。
在示例5中，示例4方法中的一个或多个芯片通过焊料连接被耦接至基板。
在示例6中，在示例4方法中的基板上形成所述至少一个无源结构包括将所述至少一个无源结构耦接至所述基板相应的一个或多个接触点。
在示例7中，示例1方法中的堆积工艺包括在所述基板上反复地沉积导电粉末层，并选择性地熔化所述沉积层中的所述导电粉末。
在示例8中，示例1方法中的堆积工艺包括立体光刻。
在示例9中，示例1方法中的至少一个无源结构包括线圈。
在示例10中，示例1方法中的至少一个无源结构包括天线、电阻器或屏蔽中的至少一个。
在示例11中，封装基板通过示例1-10方法中的任一项制成。
示例12是一种方法，包括通过三维印刷工艺在基板上形成至少一个无源结构；在基板上引入一个或多个集成电路芯片；以及在铸模材料中内嵌所述至少一个无源结构和所述一个或多个集成电路芯片。
在示例13中，示例12方法中的基板包括牺牲基板，而在所述铸模材料中内嵌所述至少一个无源结构和所述一个或多个集成电路之后，所述方法包括移除所述牺牲基板。
在示例14中，示例13方法中的每个所述至少一个无源结构和所述一个或多个集成电路芯片包括接触点，并且移除所述牺牲基板露出所述接触点，所述方法还包括：将金属化层耦接至所述接触点。
在示例15中，引入示例12方法中的一个或多个芯片包括将一个或多个芯片的接触点耦接至基板的接触点。
在示例16中，示例15方法中的一个或多个芯片通过焊料连接被耦接至基板。
在示例17中，在示例15方法中的基板上形成所述至少一个无源结构包括将所述至少一个无源结构耦接至所述基板相应的一个或多个接触点。
在示例18中，示例12方法中的三维印刷工艺包括在所述基板上反复地沉积导电粉末层，并选择性地熔化所述沉积层中的所述导电粉末。
在示例19中，示例12方法中的堆积工艺包括立体光刻。
在示例20中，封装基板通过示例12-19方法中的任一项制成。
示例21是一种装置，包括封装基板，该封装基板包括内嵌于铸模材料中的至少一个三维印刷无源结构和一个或多个集成电路芯片。
在示例22中，示例21装置中的至少一个无源结构包括天线、电阻器、线圈或屏蔽中的至少一个。
在示例23中，示例21装置中的封装还包括基板，该基板上具有接触点，并且所述至少一个无源结构和所述一个或多个集成电路芯片被耦接至所述基板相应的所述接触点。
在示例24中，示例23装置中的一个或多个集成电路芯片通过焊料连接被耦接至基板相应的接触点。
以上示意性实现的描述，包括摘要中的描述，并非旨在穷举或是要将本发明限制于所公开的确切形式。由于具体的实现方式和实例在此以示意性的目的被描述，相关领域技术人员会意识到，在本公开范围内的各种不同的等效修改都是可能的。
根据以上的详细说明可对本发明作出这些修改。在随附的权利要求中的术语不应被解读为将本发明限制于说明书和权利要求中所公开的特定的实现方式。相反，应由随附的权利要求来确定范围，权利要求应根据权利要求解释的既成规则来解读。

Claims (24)

1.一种方法包括：
通过堆积工艺在基板上形成至少一个无源结构；
在所述基板上引入一个或多个集成电路芯片；以及
在所述至少一个无源结构和所述一个或多个集成电路芯片上引入铸模材料。
2.如权利要求1所述的方法，其特征在于，所述基板包括牺牲基板，而在引入所述铸模材料之后，所述方法包括移除所述牺牲基板。
3.如权利要求2所述的方法，其特征在于，所述至少一个无源结构和所述一个或多个集成电路芯片中的每一个包括接触点，并且移除所述牺牲基板露出所述接触点，所述方法还包括：
将再分布层耦接至所述接触点。
4.如权利要求1所述的方法，其特征在于，引入所述一个或多个芯片包括将所述一个或多个芯片的接触点耦接至所述基板的接触点。
5.如权利要求4所述的方法，其特征在于，所述一个或多个芯片通过焊料连接耦接至所述基板。
6.如权利要求4所述的方法，其特征在于，在所述基板上形成所述至少一个无源结构包括将所述至少一个无源结构耦接至所述基板相应的一个或多个接触点。
7.如权利要求1所述的方法，其特征在于，所述堆积工艺包括在所述基板上反复地沉积导电粉末层，并选择性地熔化所沉积的层中的所述导电粉末。
8.如权利要求1所述的方法，其特征在于，所述堆积工艺包括立体光刻。
9.如权利要求1所述的方法，其特征在于，所述至少一个无源结构包括线圈。
10.如权利要求1所述的方法，其特征在于，所述至少一个无源结构包括天线、电阻器或屏蔽中的至少一个。
11.一种封装基板，所述封装基板通过权利要求1-10所述的任一方法制成。
12.一种方法包括：
通过三维印刷工艺在基板上形成至少一个无源结构；
在所述基板上引入一个或多个集成电路芯片；以及
在铸模材料中内嵌所述至少一个无源结构和所述一个或多个集成电路芯片。
13.如权利要求12所述的方法，其特征在于，所述基板包括牺牲基板，而在所述铸模材料中内嵌所述至少一个无源结构和所述一个或多个集成电路之后，所述方法包括移除所述牺牲基板。
14.如权利要求13所述的方法，其特征在于，所述至少一个无源结构和所述一个或多个集成电路芯片中的每一个包括接触点，并且移除所述牺牲基板露出所述接触点，所述方法还包括：
将金属化层耦接至所述接触点。
15.如权利要求12所述的方法，其特征在于，引入所述一个或多个芯片包括将所述一个或多个芯片的接触点耦接至所述基板的接触点。
16.如权利要求15所述的方法，其特征在于，所述一个或多个芯片通过焊料连接耦接至所述基板。
17.如权利要求15所述的方法，其特征在于，在所述基板上形成所述至少一个无源结构包括将所述至少一个无源结构耦接至所述基板相应的一个或多个接触点。
18.如权利要求12所述的方法，其特征在于，所述三维印刷工艺包括在所述基板上反复地沉积导电粉末层，并选择性地熔化所沉积的层中的所述导电粉末。
19.如权利要求12所述的方法，其特征在于，所述堆积工艺包括立体光刻。
20.一种封装基板，所述封装基板通过权利要求12-19所述的任一方法制成。
21.一种装置，包括：
封装基板，包括内嵌于铸模材料中的至少一个三维印刷无源结构和一个或多个集成电路芯片。
22.如权利要求21所述的装置，其特征在于，所述至少一个无源结构包括天线、电阻器、线圈或屏蔽中的至少一个。
23.如权利要求21所述的装置，其特征在于，所述封装还包括基板，所述基板上具有接触点，并且所述至少一个无源结构和所述一个或多个集成电路芯片被耦接至所述基板相应的所述接触点。
24.如权利要求21所述的装置，其特征在于，所述一个或多个集成电路芯片通过焊料连接耦接至所述基板相应的所述接触点。
CN201480026247.9A 2014-12-09 2014-12-09 铸模材料中的三维结构 Active CN105874595B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/069361 WO2016093808A1 (en) 2014-12-09 2014-12-09 Three dimensional structures within mold compound

Publications (2)

Publication Number Publication Date
CN105874595A true CN105874595A (zh) 2016-08-17
CN105874595B CN105874595B (zh) 2020-02-21

Family

ID=56107829

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480026247.9A Active CN105874595B (zh) 2014-12-09 2014-12-09 铸模材料中的三维结构

Country Status (7)

Country Link
US (1) US9711492B2 (zh)
EP (2) EP3916783A3 (zh)
JP (1) JP6163702B2 (zh)
KR (1) KR101785306B1 (zh)
CN (1) CN105874595B (zh)
TW (1) TWI619179B (zh)
WO (1) WO2016093808A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108900216A (zh) * 2018-06-01 2018-11-27 华为技术有限公司 一种无线传输模组及制造方法
CN112185689A (zh) * 2019-07-05 2021-01-05 诚勤科技有限公司 包含密封结构的滤波器制造方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10660208B2 (en) * 2016-07-13 2020-05-19 General Electric Company Embedded dry film battery module and method of manufacturing thereof
US10332841B2 (en) * 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US10269732B2 (en) * 2016-07-20 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info package with integrated antennas or inductors
JP6610498B2 (ja) * 2016-10-21 2019-11-27 株式会社村田製作所 複合型電子部品の製造方法
US10700011B2 (en) 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
TWI653896B (zh) 2017-02-10 2019-03-11 華邦電子股份有限公司 骨導式助聽裝置及骨導式揚聲器
CN108419194B (zh) 2017-02-10 2021-04-30 华邦电子股份有限公司 骨导式助听装置及骨导式扬声器
US11282800B2 (en) * 2017-09-30 2022-03-22 Intel Corporation Substrate integrated inductors using high throughput additive deposition of hybrid magnetic materials
US10750618B2 (en) * 2018-04-18 2020-08-18 University Of Hawaii System and method for manufacture of circuit boards
US10433425B1 (en) 2018-08-01 2019-10-01 Qualcomm Incorporated Three-dimensional high quality passive structure with conductive pillar technology
KR102574414B1 (ko) * 2019-05-21 2023-09-04 삼성전기주식회사 전자 부품 모듈
US11612061B2 (en) * 2019-09-30 2023-03-21 Appareo IoT, LLC Laser direct structuring of switches
US11158582B2 (en) * 2019-12-04 2021-10-26 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11450628B2 (en) * 2019-12-15 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure including a solenoid inductor laterally aside a die and method of fabricating the same
EP3852132A1 (en) 2020-01-20 2021-07-21 Infineon Technologies Austria AG Additive manufacturing of a frontside or backside interconnect of a semiconductor die
JP2022002260A (ja) * 2020-06-22 2022-01-06 株式会社村田製作所 表面実装型受動部品
KR20220045684A (ko) * 2020-10-06 2022-04-13 에스케이하이닉스 주식회사 지그재그 모양의 와이어를 포함하는 반도체 패키지
KR20220101249A (ko) * 2021-01-11 2022-07-19 엘지이노텍 주식회사 안테나 모듈
DE102021116533A1 (de) * 2021-06-25 2022-12-29 Tdk Electronics Ag Low loss inductor
DE102022108431A1 (de) 2022-04-07 2023-10-12 Krohne Ag Spulenanordnung für ein Durchflussmessgerät und Verfahren zum Herstellen einer Spulenanordnung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099752A (ja) * 2007-10-17 2009-05-07 Kyushu Institute Of Technology 半導体パッケージ及びその製造方法
US20140132386A1 (en) * 2012-11-02 2014-05-15 Hahn-Schickard-Gesellschaft Fur Angewandte Forschung E.V. Method for Producing a Coil and Electronic Device
US8822268B1 (en) * 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5571471A (en) * 1984-08-08 1996-11-05 3D Systems, Inc. Method of production of three-dimensional objects by stereolithography
US5643804A (en) * 1993-05-21 1997-07-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a hybrid integrated circuit component having a laminated body
US20040197493A1 (en) * 1998-09-30 2004-10-07 Optomec Design Company Apparatus, methods and precision spray processes for direct write and maskless mesoscale material deposition
TW507352B (en) 2000-07-12 2002-10-21 Hitachi Maxell Semiconductor module and producing method therefor
US20020112963A1 (en) * 2001-02-22 2002-08-22 Nikon Corporation Methods for fabricating high-precision thermally stable electromagnetic coils
US7556490B2 (en) * 2004-07-30 2009-07-07 Board Of Regents, The University Of Texas System Multi-material stereolithography
JP2007088363A (ja) * 2005-09-26 2007-04-05 Renesas Technology Corp 電子装置
KR100735411B1 (ko) * 2005-12-07 2007-07-04 삼성전기주식회사 배선기판의 제조방법 및 배선기판
JP4870509B2 (ja) * 2006-09-27 2012-02-08 新光電気工業株式会社 電子装置
DE102006058068B4 (de) * 2006-12-07 2018-04-05 Infineon Technologies Ag Halbleiterbauelement mit Halbleiterchip und passivem Spulen-Bauelement sowie Verfahren zu dessen Herstellung
GB2461443B (en) * 2007-04-13 2012-06-06 Murata Manufacturing Co Magnetic field coupling antenna module arrangements including a magnetic core embedded in an insulating layer and their manufacturing methods.
US8659154B2 (en) 2008-03-14 2014-02-25 Infineon Technologies Ag Semiconductor device including adhesive covered element
JP4795385B2 (ja) * 2008-05-26 2011-10-19 富士通株式会社 集積型電子部品
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
CN102569249B (zh) * 2010-12-08 2014-01-22 财团法人工业技术研究院 立体式电感
AU2012267207A1 (en) * 2011-06-10 2014-01-09 Axiflux Holdings Pty Ltd Electric motor/generator
KR101434003B1 (ko) * 2011-07-07 2014-08-27 삼성전기주식회사 반도체 패키지 및 그 제조 방법
KR101982887B1 (ko) 2011-07-13 2019-05-27 누보트로닉스, 인크. 전자 및 기계 구조체들을 제조하는 방법들
US9373923B2 (en) * 2011-11-22 2016-06-21 Savannah River Nuclear Solutions, Llc Rapid prototype extruded conductive pathways
US8665479B2 (en) * 2012-02-21 2014-03-04 Microsoft Corporation Three-dimensional printing
JP5941737B2 (ja) * 2012-04-13 2016-06-29 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US8786060B2 (en) * 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9343442B2 (en) * 2012-09-20 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Passive devices in package-on-package structures and methods for forming the same
US8952521B2 (en) * 2012-10-19 2015-02-10 Infineon Technologies Ag Semiconductor packages with integrated antenna and method of forming thereof
US9156680B2 (en) * 2012-10-26 2015-10-13 Analog Devices, Inc. Packages and methods for packaging
US8963135B2 (en) 2012-11-30 2015-02-24 Intel Corporation Integrated circuits and systems and methods for producing the same
US20140240071A1 (en) * 2013-02-26 2014-08-28 Entropic Communications, Inc. 3d printed inductor
US20140253279A1 (en) * 2013-03-08 2014-09-11 Qualcomm Incorporated Coupled discrete inductor with flux concentration using high permeable material
US9126365B1 (en) * 2013-03-22 2015-09-08 Markforged, Inc. Methods for composite filament fabrication in three dimensional printing
DE102013010228A1 (de) 2013-06-18 2014-03-27 Daimler Ag Induktor, Verfahren zur Herstellung eines Induktors und Pressenwerkzeug
US9878470B2 (en) * 2014-06-10 2018-01-30 Formlabs, Inc. Resin container for stereolithography
US9832875B2 (en) * 2014-07-07 2017-11-28 Hamilton Sundstrand Corporation Method for manufacturing layered electronic devices
US9969001B2 (en) * 2014-12-10 2018-05-15 Washington State University Three-dimensional passive components

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009099752A (ja) * 2007-10-17 2009-05-07 Kyushu Institute Of Technology 半導体パッケージ及びその製造方法
US20140132386A1 (en) * 2012-11-02 2014-05-15 Hahn-Schickard-Gesellschaft Fur Angewandte Forschung E.V. Method for Producing a Coil and Electronic Device
US8822268B1 (en) * 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108900216A (zh) * 2018-06-01 2018-11-27 华为技术有限公司 一种无线传输模组及制造方法
US11538774B2 (en) 2018-06-01 2022-12-27 Huawei Technologies Co., Ltd. Wireless transmission module and manufacturing method
CN112185689A (zh) * 2019-07-05 2021-01-05 诚勤科技有限公司 包含密封结构的滤波器制造方法

Also Published As

Publication number Publication date
JP2017505547A (ja) 2017-02-16
KR20160087747A (ko) 2016-07-22
US9711492B2 (en) 2017-07-18
US20160358897A1 (en) 2016-12-08
WO2016093808A1 (en) 2016-06-16
TWI619179B (zh) 2018-03-21
EP3053190A1 (en) 2016-08-10
TW201633411A (zh) 2016-09-16
EP3053190B1 (en) 2021-05-26
KR101785306B1 (ko) 2017-10-17
CN105874595B (zh) 2020-02-21
EP3916783A3 (en) 2022-07-13
JP6163702B2 (ja) 2017-07-19
EP3053190A4 (en) 2017-09-06
EP3916783A2 (en) 2021-12-01

Similar Documents

Publication Publication Date Title
CN105874595A (zh) 铸模材料中的三维结构
KR102249874B1 (ko) 조절 가능한 강도를 갖는 결합형 스핀 홀 나노 발진기들
CN104517953B (zh) 用于无源部件的具有叠置体基板的管芯封装
CN104733436B (zh) 具有嵌入式桥的集成电路封装
CN106165092A (zh) 具有穿桥导电过孔信号连接的嵌入式多器件桥
CN105742270A (zh) 堆叠集成电路封装中的集成无源组件
CN105981159A (zh) 具有设置在封装体内的无源微电子器件的微电子封装件
CN104051420A (zh) 用于嵌入式互连桥封装的直接外部互连
JP6073375B2 (ja) ジャイロスコープ及び角速度決定方法
CN107646140A (zh) 用于形成封装结构中的沟槽的方法及由此形成的结构
TW202119439A (zh) 具有預製的鐵氧體磁心之同軸磁性電感器
CN105720049A (zh) 负鼠晶片封装叠加设备
CN107406248A (zh) 形成传感器集成封装的方法和由此形成的结构
TWI571894B (zh) 具有金屬虛擬特徵的電感器設計
US20210125944A1 (en) Package embedded magnetic inductor structures and manufacturing techniques for 5-50 mhz smps operations
TW201535667A (zh) 局部化高密度基板繞線
CN107431022A (zh) 具有带有整体附接结构的嵌入式迹线层的微电子衬底
CN115939082A (zh) 用于增强功率递送的玻璃贴片中的局部高磁导率磁性区域
CN107251216A (zh) 用于微电子结构中的互连垫的表面末道层
CN105190798A (zh) 能通过可变磁通密度组件来调谐的电感器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210729

Address after: California, USA

Patentee after: GOOGLE Inc.

Address before: California, USA

Patentee before: INTEL Corp.

TR01 Transfer of patent right