CN105742270A - 堆叠集成电路封装中的集成无源组件 - Google Patents

堆叠集成电路封装中的集成无源组件 Download PDF

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Publication number
CN105742270A
CN105742270A CN201510821263.3A CN201510821263A CN105742270A CN 105742270 A CN105742270 A CN 105742270A CN 201510821263 A CN201510821263 A CN 201510821263A CN 105742270 A CN105742270 A CN 105742270A
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wafer
crystalline film
coupled
electric power
substrate
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CN105742270B (zh
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R.斯特范
D.加德纳
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Intel Corp
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Intel Corp
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Abstract

本公开涉及堆叠集成电路封装中的集成无源组件。描述堆叠集成电路封装中的集成无源组件。在一个实施例中，装置具有衬底、在衬底上耦合于衬底的第一晶片、具有处理核并且在第一晶片上耦合于第一晶片的第二晶片和附连到第一晶片并且耦合于电力供应电路的无源设备，该第一晶片包括耦合于衬底以接收电力的电力供应电路，该第一晶片耦合于电力供应电路以对处理核供电。

Description

堆叠集成电路封装中的集成无源组件
技术领域
本描述涉及堆叠处理器封装中的集成无源组件的领域并且特别涉及用于功率传递的集成组件。
背景技术
高功率处理器封装正发展成具有更多处理核和不同类型的处理核。这些核需要来自外部电力供应的功率传递。在许多情况下，在晶片（die）上包括集成电压调节器作为处理核的一部分。电压调节器需要例如电感器和电容器等放置在某一外部位点中的大型无源组件。随着使用更多的核，需要更多的外部无源组件。
在其他示例中，电压调节器处于具有非核电路（例如I/O、存储器控制器和功率控制单元）的独立晶片中并且与晶片（其与晶片上的处理器核和对于每个核的电压调节器堆叠在一起）一起封装。这在具有微处理器核的晶片中允许有更多空间可用并且使电力电路与核处理电路隔离。对于电压调节器的大型无源电感器和电容器仍然被放置在某一外部位点中，其通过通孔、连接凸块或一些其他手段而被触及。无源组件在与高速数字电路和高密度互连网格隔离时提供更高Q因子。在它们与处理晶片的组件或甚至电压调节器晶片相比变大时它们也提供更高Q因子。无源组件在它们定位在核处理电路附近时也表现得更好。
发明内容
在一个实施例中，提供一种装置，其包括：衬底；第一晶片，其在所述衬底上耦合于所述衬底，所述第一晶片包括耦合于所述衬底以接收电力的电力供应电路；第二晶片，其具有处理核并且在所述第一晶片上耦合于所述第一晶片，所述第二晶片耦合于所述电力供应电路以对所述处理核供电；以及无源设备，其附连到所述第一晶片并且耦合于所述电力供应电路。
在一个实施例中，所述第一晶片具有：正面，其包括面对所述衬底的电路；和面对所述第二晶片的背面，并且其中所述无源设备安置在所述背面上。
在一个实施例中，所述第一晶片的正面使用通过所述第一晶片的穿硅通孔而耦合于所述第二晶片。
在一个实施例中，所述第一晶片的背面使用接合线耦合于所述衬底。
在一个实施例中，所述第一晶片具有：正面，其包括面对所述第二晶片的电路；和面对所述衬底的背面，并且其中所述无源设备安置在所述第一晶片的正面上。
在一个实施例中，所述第一晶片使用焊料凸块连接到所述第二晶片并且其中所述无源设备安置在所述第一晶片的正面上且在所述焊料凸块之间。
在一个实施例中，所述第一晶片使用微凸块、模塑突柱、热超声或热压缩接合部而连接到所述第二晶片并且其中所述无源设备安置在所述第一晶片的正面上且在所述接合部之间。
在一个实施例中，所述第一晶片的正面在所述焊料凸块之间具有凹陷并且其中所述无源设备安置在所述凹陷内部。
在一个实施例中，所述凹陷具有底层和侧壁，其中所述侧壁朝所述底层锥形化，并且其中所述无源设备在锥形化侧壁上具有磁性层。
在一个实施例中，所述第一晶片是硅晶片并且其中所述无源设备是具有在所述硅晶片的表面上形成的磁性材料的电感器。
在一个实施例中，所述无源设备包括耦合于电感器的电容器，所述电容器在所述第一晶片的表面上形成。
在一个实施例中，所述第一晶片是硅晶片并且其中所述电容器是金属-绝缘体-金属电容器。
在一个实施例中，所述无源设备包括3D金属-绝缘体-金属电容器、平面金属-绝缘体-金属电容器、磁芯电感器、条纹电感器、螺旋电感器、螺线管电感器或环形电感器。
在一个实施例中，所述衬底包括功率解耦电容器，其在外部电力供应与所述电力供应电路之间耦合。
在一个实施例中，所述电力供应电路包括电压转换器、开关电容器电压转换器、电压调节器或全集成电压调节器。
在一个实施例中，提供一种堆叠晶片封装，其包括：核晶片，其具有多个处理核；非核晶片，其对于每个处理核具有电力供应电路，每个电力供应电路独立耦合于每个相应处理核来向所述相应处理核供应电力；封装衬底，其耦合于所述非核晶片以从外部源接收电力并且向所述非核晶片的电力供应电路提供电力；多个通过所述非核晶片的穿硅通孔，用于将数据信号从所述核晶片运送到所述封装衬底；以及多个无源设备，其在所述非核晶片与所述核晶片之间附连到所述非核晶片，所述多个无源设备每个耦合于电力供应电路。
在一个实施例中，所述非核晶片具有面对所述核晶片的正面并且其中所述多个无源设备是附连到所述非核晶片的正面的电容器。
在一个实施例中，提供一种计算设备，其包括：系统板；通信封装，其连接到所述系统板；以及处理器封装，其具有：衬底；在所述衬底上耦合于所述衬底的非核晶片，所述非核晶片包括耦合于所述衬底以接收电力的电力供应电路；具有处理核并且在所述非核晶片上耦合于所述非核晶片的核晶片，所述非核晶片耦合于所述电力供应电路以对所述处理核供电；和附连到所述非核晶片并且耦合于所述电力供应电路的无源设备。
在一个实施例中，所述非核晶片包括：正面，其包括面对所述核晶片的电路；和面对所述衬底的背面，其中所述无源设备安置在所述非核晶片正面中的凹陷中。
在一个实施例中，所述非核晶片具有面对所述衬底的正面和面对所述核晶片的正面，其中所述无源设备附连到所述晶片的背面，其中所述电力供应电路在所述非核晶片的正面上形成并且经由通过所述非核晶片的背面的通孔耦合于所述无源设备和所述核晶片。
附图说明
本发明的实施例通过示例而非限制的方式在附图的图中图示，其中类似的标号指代相似的元件。
图1是根据实施例在第一和第二晶片上具有功率传递组件的3-D堆叠面对背封装的横截面侧视图。
图2是根据实施例的备选堆叠面对背封装的横截面侧视图。
图3是根据实施例的堆叠面对面封装的横截面侧视图。
图4是根据实施例的备选堆叠面对面封装的横截面侧视图。
图5是根据实施例在晶片的凹陷中形成的磁芯电感器的横截面侧视图。
图6是根据实施例在具有倾斜侧壁的晶片的凹陷中形成的磁芯电感器的横截面侧视图。
图7是根据实施例在晶片的孔中形成的磁芯电感器的横截面侧视图。
图8是根据实施例安装到衬底的堆叠面对背封装的横截面侧视图。
图9是根据实施例包含具有无源组件的封装的计算设备的框图。
具体实施方式
在实施例中，具有磁性材料的电感器（也称为磁芯电感器（MCI））在3D堆叠处理器的底部（非核）晶片上集成。堆叠处理器采用特别适合于将FIVR（全集成电压调节器）集成到晶片内的拓扑。非核晶片包括非核电路，例如输入/输出电路、存储器控制器、功率控制单元等。作为顶部（核）晶片上的多层MIM（金属-绝缘体-金属）电容器的备选或作为其补充，一些实施例还可包括在底部（非核）晶片的背面上的高密度电容器。该方法因为封装需要较少层和较少设计限制而简化封装设计。该方法还对于高效VIN（输入电压）解耦电容器在封装上开辟更多空间。尽管底部（非核）晶片通过添加电感器而变得更复杂，它通过去除在封装中的FIVR电路和电感器之间通过底部晶片的连接而简化。
磁芯电感器可在非核（底部）晶片的背面或正面上集成。这避免使FIVR输出从顶部或底部晶片回到封装以连接到封装中的电感器。它还使非核（底部）晶片上的连接凸块的数量减少。与封装中的ACI相比，底部晶片上的MCI可以提供二十或三十倍高的电感密度和明显更小的体积和厚度，这减轻对核面积定标的影响。对于定位在底部晶片上以向顶部晶片上的核供应电力的FIVR设计，对于电感器的最佳位点是相同的底部晶片。高密度3DMIM电容器和平面MIM电容器也可在底部（非核）晶片的背面或正面上添加以避免在顶部晶片上制造多层MIM电容器的成本和复杂性。另外，通过在具有FIVR的相同晶片中包括MCI，可独立于封装组件来测试FIVR。
图1是3D堆叠服务器配置封装102的侧面横截面图。存在要直接或通过插座连接到电路板的封装衬底104或衬底。衬底可由陶瓷、硅、内置层或任何其他材料形成以在衬底的顶表面132、136和底表面130、134上提供连接焊盘以及顶部和底部与衬底上或中的一些电路组件之间提供连接路由。非核晶片106连接到衬底并且定位在衬底上。核晶片108耦合于非核晶片并且定位在非核晶片上。非核晶片典型地对核晶片提供功率管理、输入/输出信令和其他功能。尽管下晶片在本文称为非核晶片，可使用执行相似功能的任何其他类型的支承晶片，并且晶片可起不同的名字。非核还可包括处理资源、无线电设备、放大器或例如在片上系统（SOC）中使用的其他类型的电路。
核晶片使用集成在晶片上的一个或多个处理核提供高速计算和处理功能。核晶片附连使得电路122面朝衬底，这允许散热器124附连到核晶片的背面。存在对不同功能优化的不同类型的核，其包括通用计算、数字信号处理和图形处理核。晶片的特定功能可适于适应不同应用。可存在更多的核晶片并且对于例如存储器、输入/输出信令、协处理等其他功能可在非核上存在额外晶片。
在非核（底部）晶片的每个着落槽（未示出）上存在FIVR块（未示出），其向直接定位它上面的核供电。还存在对非核晶片本身供电的FIVR块。本文提出的技术可适用于对于FIVR组件的集成LC滤波器组件，而不管组件是否被供电。另外，尽管本文的描述大体针对FIVR，描述的结构和技术可适用于其他类型的电压调节器或电压转换器。电压调节器可以是开关电压调节器（通常称为降压调节器）、开关电容器电压调节器、电荷泵、低下降电压调节器、线性电压调节器或这些类型的电压调节器的组合（例如组合的混合开关电容器）。不是所有这些类型的电压调节器都使用电感器，但电容器典型地在所有电压调节器中使用来减少来自电路开关的噪声。无源设备的特定选择可适于适应对应电力供应电路。术语“FIVR”的使用不意在需要任何特定电压调节器电路、连接或组件。
非核晶片106附连到衬底使得晶片的正面面对衬底。这允许晶片的正面的电路120通过配对连接焊盘132、136而直接耦合于衬底。如上文提到的，该电路可根据特定应用而包括电力、计时、输入/输出和其他电路。核晶片相似地附连到非核晶片，使得核晶片的正面面对非核晶片的背面。这可称为F2B（正对背或面对背）。核晶片的电路122直接耦合于非核晶片的背面并且可使用TSV（穿硅通孔）或多种其他技术中的任一个连接到非核晶片的电路。
磁芯电感器110在非核晶片的背面上集成，而高密度MIM电容器112在顶部晶片中集成。电容器可使用多种不同技术（其包括多层平面设计）中的任一个形成。来自外部源但典型地不必在电路板上的输入电压VIN通过焊盘134耦合于衬底104并且通过衬底连接136耦合于电压调节器电路114（例如FIVR）。电压调节器使电力耦合于MCI110并且然后通过电容器112来对核晶片的至少一部分供电。对于来自核晶片的电流的返回路径以及到电容器的连接被回送通过衬底连接132、通过衬底到接地连接GND130、通过非核晶片和衬底。
电压调节器电路由晶体管114表示来支持供应给核晶片108的电力的脉宽调制（PWM）。在一些实施例中，调节的电力供应将基于一个或多个开关功率晶体管以生成输入电压的可控占空比。开关功率晶体管的操作由接收控制信号来驱动晶体管栅极的功率调节电路（未示出）控制。电力供应脉冲然后供应给电感器110和电容器112来将脉冲功率拉平到恒定电压水平。其他类型的电力供应可用作适应特定核的备选。
尽管本公开在FIVR或其他类型的电压调节器的上下文中提供，描述的配置和实施例可适用于多种不同的电力供应电路和系统并且适用于对于任何这样的系统的无源组件。电力供应电路114可以是如描述的电压调节器、电压转换器或任何其他类型的电力供应电路。相似地，尽管既示出电感器110又示出电容器112，无源组件和它们与电路的连接的数量和类型可适于适应特定电力供应电路。尽管仅示出一个电压调节器，对于核晶片的每个处理核可存在一个或多个电压调节器。还可存在用于对非核晶片中的组件供电的电压调节器。核晶片可具有相似或不同类型的两个或以上处理核。在一个实施例中，可存在36个核，其包括单个核晶片中所包括的高速、低功率、图形、加速器和FPGA（现场可编程门阵列）处理器。根据特定实现可使用其他和额外核。
图1和其他实施例中的任一个的封装可通过添加覆盖物、散热器或一些其他或额外组件来完成。备选地，可使用围绕非核晶片外围的接合线而连接到封装。模塑化合物中可涵盖晶片以用于保护和稳定性。还可在封装上或中添加例如放大器、射频组件和数字信号处理器等额外部件。
图2是其中电容器212从核晶片208移到非核（底部）晶片206的背面的备选堆叠服务器配置封装202的横截面侧视图。电容器可在与电感器相同的空间中形成。封装具有封装衬底204或具有面对且耦合于衬底204的非核晶片的正面的电路220的衬底。核晶片208的正面的电路222耦合于非核晶片的背面。
衬底直接或通过插座耦合于VIN连接器234。通过电压调节器214对非核晶片的背面上的电感器210调节VIN。该电感器与图1的电感器110相似地构造和安置。电感器210耦合于电容器212（现在在非核晶片的背面上）以将电力路由到核晶片并且最终被回送通过非核晶片206和衬底204到GND连接230。电容器212在非核晶片上的安置进一步简化核晶片的构造并且进一步简化非核晶片与核晶片之间的连接。电容器212可以是平面MIM电容器或3DMIM电容器。
图3是适合于F2F（面对面）堆叠的封装的备选实现的相似横截面侧视图。在该实施例中，封装302具有衬底304，其具有对于例如数据和控制的电力、VIN、GND和其他外部连接。非核晶片306通过它的背面耦合于衬底。穿硅通孔338使衬底通过晶片的背面连接到晶片正面上的电压调节器314。备选地，连接到电路320、围绕非核晶片306外围的接合线可以用于连接到衬底。非核晶片的正面面对核晶片308的正面。两个晶片例如使用焊球网格或微凸块焊网格340连接。电感器310在非核晶片的正面上且在焊料凸块之间形成并且耦合于电压调节器。电容器312在核晶片的正面上形成并且通过焊球连接中的一个或多个耦合于电感器。电容器然后耦合于晶片正面的电路，其形成处理核。
在该示例中，第一晶片306的正面识别为这样的面，其包括通过光刻和其他工艺在晶片上形成的电路320。相似地，第二晶片308的正面识别为这样的面，其包括在第二晶片上形成的电路322。
电感器310可用磁性材料形成为例如MCI（磁芯电感器或具有磁性材料的电感器）并且电容器可形成为MIM（金属-绝缘体-金属）盖。两者都可在非核晶片的正面或顶部（在与晶体管相同的侧）上制造。在图3和4的实施例中，与承载电压调节器与电感器和电容器之间的电流的TSV相比，将降低对于VIN通过TSV338的电流。电压调节器之前的电力具有更高电压和更低电流。因此，与在衬底中具有电感器的系统相比之下，需要更少TSV并且晶片之间的信号具有更短距离行进。因为晶片到晶片信号可能具有更少的缓冲和更少的放大并且可能数量更多，使对于晶片到晶片信号的距离减少用更低成本提高性能。
图4是与图3的相似的横截面侧视图，其中电容器412从核晶片408的正面移到非核晶片406的正面。另外，3D高密度电容器可以包含在非核晶片的正面上以供电压调节器使用以及对于到电压调节器的输入Vcc包含在非核晶片的背面上用于解耦。
在图4中，使用图3的相同F2F配置。封装402具有第一晶片406，其耦合于衬底404并且在衬底404上。第二晶片408耦合于采用F2F配置的第一晶片使得第一晶片的电路420面对第二晶片的电路422。第一晶片包括电压调节器414（例如FIVR）、一个或多个电感器410和耦合于电压调节器的一个或多个电容器412。电感器和电容器在第一晶片的正面上且在使第一和第二晶片彼此连接的焊料凸块之间形成。在该实施例中（如与在图3的示例中一样），到外部电力的通孔338穿过第一晶片到第一晶片的背面以连接到衬底。额外通孔348穿过衬底以通过焊料凸块连接到外部电力供应。因此，电压调节器与对应处理核之间的连接是短的并且不需要任何穿硅通孔。到外部电力的连接是比较长的。备选地，接合线可以沿非核晶片的外围使用以电连接到衬底。
在图1-4中，电感器和电容器被放置在非核与核晶片之间的间隙中。该空间的垂直高度典型地通过两个晶片之间的连接的高度来确定。这些连接可以是金属微凸块连接、焊料凸块、模塑突柱、使用铜-铜、金-金或其他金属的热超声或热压缩、或导电聚合物或带盘式工艺接合部。使用例如热超声接合或楔形接合部的线接合还可以用于使非核晶片连接到衬底。在一些实施例中，小的空间由非核晶片与衬底之间的接合产生，其中没有金属到金属接触。电绝缘粘合物可在该空间中用作底部填充。该底部填充提供更强机械连接、提供热桥并且确保焊料接点不会由于芯片（chip）的差别加热而被施加应力。底部填充还通过传导热来分配芯片之间的热膨胀失配。
根据电感器和电容器的构造以及需要的L、C和其他值，L和C组件的高度可大于由微凸块连接创建的垂直间隙。为了对L和C组件提供更多空间，可在合适晶片的对应表面上形成凹陷。L和C组件然后可在这些凹陷中形成或安置在这些凹陷中。
图5示出在晶片的凹陷中形成的磁芯电感器的示例。相同方法可适用于电容器和其他类型的电感器。晶片502以横截面示出。在晶片中用垂直壁512和底层510切出缺口504。缺口通过蚀刻、钻削、激光加工或通过将材料从晶片去除来形成凹陷或凹口的另一个工艺而形成为凹陷或凹进。缺口使在非核晶片中从顶部晶片到缺口底层的距离增加。根据封装配置，集成无源组件可在背面上或甚至在底部晶片的正面上内置到一个或多个不同缺口中。
如示出的，磁芯电感器506形成或安置在缺口中。电感器具有被磁芯材料514环绕的铜绕组516。电感器可采用多种不同方式中的任一个形成。电感器设备可以是条纹电感器、螺旋电感器、螺线管电感器、环形电感器、在蚀刻到硅内的V型槽中形成的电感器，或可以是耦合电感器或变压器。在一些实施例中，首先沉积下半部磁性材料。铜导体在下半部上形成并且然后沉积上半部。绝缘体可用于使铜线与磁性材料隔离。电感器耦合于布线迹线（未示出），其从缺口横越到非核晶片的合适布线或焊料凸块。该布线允许电感器在一侧上耦合于电压调节器并且在另一侧上耦合于一个或多个电容器或任何其他组件，如可根据实现而期望的。
图6是其中硅晶片602中的缺口604可锥形化来提高电感器608的磁性材料614的阶梯覆盖（其提高电感器的品质因子）的另外的变化的横截面侧视图。缺口具有底层610和侧壁612，但在该情况下该侧壁以一定角度形成使得壁朝缺口底部锥形化。磁芯材料614然后可通过直接将芯材料直接沉积在缺口底层上并且沿着缺口的倾斜侧壁向上而形成为下半部。这将通过对磁通量提供更好路径而提高电感器的阶梯覆盖和性能。铜绕组616在芯的下半部上形成并且然后电感器上半部在铜绕组上形成。如示出的，每个缺口可以适应单个电感器的大小形成。形成缺口的过程可用于控制电感器的大小。如与在图5的示例中一样，布线迹线可采用使电感器连接到其他组件的任何其他方式沉积或形成。
高密度电容器也可在硅晶片的表面中形成。图7示出硅晶片702。孔704可如示出的那样蚀刻到非核晶片702的正面或背面以示出一系列并行通道或槽。通道然后可内衬第一导体层708，例如TiN、TaN、Cu或任何其他期望材料。该第一导体层然后可被覆盖在介电层710中，例如Al2O3、HfO2、SiN、SiO2或任何其他期望电介质。电介质然后可用具有与第一层708相同或不同材料的第二导体层712覆盖。在图7的示例中，孔完全用第二导体层填充。用于在3D沟槽中或在平面上形成这些层的沉积技术包括原子层沉积（ALD）、电镀、化学镀（electrolessplating）、化学气相沉积（CVD）溅射和蒸发。
所得的MIM电容器因为它的材料中的大部分嵌入了切入晶片的孔内而占用晶片之间很少的垂直空间。可形成金属和绝缘体的交替层以产生特定电容。这些电容器可以在非核（如在图2和4中）或在核晶片上（如在图1和3中）形成。它们可用于电压调节器输出。它们还可用于作为解耦电容器的微晶片的输入电压VIN。可调整电介质的厚度以适应与输出电压分离的输入电压的较高电压。
图8是3-D堆叠F2B封装802（其包括使用面对背堆叠而在3D堆叠系统中集成的磁芯电感器810和3DMIM电容器812）的部分的横截面侧视图。电感器和电容器两者都嵌入底部晶片806的背面中，以实现从底部晶片的电路层816中的FIVR电路到顶部晶片的电路层818中的负载的自然路径。
可在晶片的背面上形成再分布层822以连接底部晶片806上的TSV820与顶部晶片808上的微凸块824之间的电感器和电容器。TSV使电感器和电容器连接到底部晶片正面上的电压调节器。特定路由层826可用于使电感器810连接到电容器812。底部晶片还耦合于衬底804用于连接到外部组件。再分布层822也可用作均热器来帮助去除由非核晶片产生的热。可添加散热器（未示出）以与非核晶片的外围接触。非核晶片可比核晶片更大以提供与非核晶片的更简单物理接触。
本文描述的堆叠封装提供明显的益处。作为示例，对于必须装进一个核的占用空间的FIVRLC滤波器组件的面积定标问题得到缓解。通过在底部晶片上或中形成或安置LC滤波器组件，可以获得高Q因子而未对更简单衬底施加更高精度并且没有在高速致密制造技术处理核上消耗大量空间。
通过从衬底去除LC组件，衬底的成本和复杂性降低。另外，在非核晶片上需要更少连接凸块来支承FIVR支承。代替使用凸块连接到衬底中的LC无源组件，FIVR使用顶部核中的TSV和再分布层而直接连接到LC组件。不再需要到顶部晶片的衬底的连接凸块。
图9图示根据本发明的一个实现的计算设备100。该计算设备100容置系统板2。该板2可包括许多组件，其包括但不限于处理器4和至少一个通信封装6。该通信封装耦合于一个或多个天线16。处理器4物理且电耦合于板2。
根据它的应用，计算设备100可包括可或可未物理且电耦合于板2的其他组件。这些其他组件包括但不限于易失性存储器（例如，DRAM）8、非易失性存储器（例如，ROM）9、闪速存储器（未示出）、图形处理器12、数字信号处理器（未示出）、密码处理器（未示出）、芯片集14、天线16、显示器18（例如触屏显示器）、触屏控制器20、电池22、音频编解码器（未示出）、视频编解码器（未示出）、功率放大器24、全球定位系统（GPS）设备26、罗盘28、加速计（未示出）、陀螺仪（未示出）、扬声器30、拍摄装置32和大容量存储设备（例如硬盘驱动）10、压缩盘（CD）（未示出）、数字多功能盘（DVD）（未示出）等。这些组件可连接到系统板2、安装到系统板或与其他组件中的任一个组合。
通信封装6实现无线和/或有线通信用于数据到和从计算设备100的传输。术语“无线”和它的派生词可用于描述电路、设备、系统、方法、技术、通信信道等，其可通过使用通过非固体介质的调制电磁辐射来传递数据。术语并不意味着关联的设备不包含任何线，但在一些实施例中它们可不包括线。通信封装6可实现许多无线或有线标准或协议中的任一个，其包括但不限于Wi-Fi（IEEE802.11系列）、WiMAX（IEEE802.16系列）、IEEE802.20、长期演进（LTE）、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、Bluetooth、其以太网衍生物，以及定名为3G、4G、5G及以后的任何其他无线和有线协议。计算设备100可包括多个通信封装6。例如，第一通信封装6可专用于较短程无线通信，例如Wi-Fi和Bluetooth，并且第二通信封装6可专用于更远程无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
芯片中的任一个或多个可如本文描述的那样封装或若干个芯片可如本文描述的那样使用用于功率传递的无源组件组合成单个封装。
在各种实现中，计算设备100可以是服务器、工作站、膝上型电脑、上网本、笔记本、超级本、智能电话、平板、个人数字助理（PDA）、超级移动PC、移动电话、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字拍摄装置、便携式音乐播放器或数字录像机或称作物联网（IoT）的设备。在另外的实现中，计算设备100可以是任何其他电子设备，例如笔、钱包、手表或处理数据的器具。
实施例可实现为使用母板、专用集成电路（ASIC）和/或现场可编程门阵列（FPGA）而互连的一个或多个存储器芯片、控制器、CPU（中央处理单元）、微芯片或集成电路。
对“一个实施例”、“实施例”、“示例实施例”、“各种实施例”的引用意指这样描述的本发明的实施例可包括特定特征、结构或特性，但不是每个实施例都一定包括特定特征、结构或特性。此外，一些实施例可具有对其他实施例描述的特征中的一些、全部或没有。
在下面的描述和权利要求中，可使用术语“耦合”连同它的派生词。“耦合”用于指示两个或以上元件彼此协同操作或交互，但它们可具有或可不具有在它们之间的介入物理或电组件。
如在权利要求中使用的，除非另外规定，用于描述公共元件的序数词“第一”、“第二”、“第三”等的使用仅仅指示所参考的类似元件的不同实例，并且不意在暗指这样描述的元素必须在时间上、空间上、在排序上或采用任何其它方式处于给定序列中。
附图和前面的描述给出实施例的示例。本领域内技术人员将意识到描述的元件中的一个或多个可很好地组合成单个功能元件。备选地，某些元件可分成多个功能元件。来自一个实施例的元件可添加到另一个实施例。例如，本文描述的过程的顺序可改变并且不限于本文描述的方式。此外，任何流程图的动作不必按示出的顺序实现；也不必执行动作中的全部。而且，不依赖于其他动作的那些动作可与其他动作并行执行。实施例的范围绝不由这些特定示例限制。例如结构、尺寸和材料使用中的差异等许多改动，无论是否在说明书中明确给出，都是可能的。实施例的范围至少与由下面的权利要求给出的一样广。
下列示例关于另外的实施例。不同实施例的各种特征可多方面地与所包括的一些特征和排除的其他特征组合来适应多种不同应用。一些实施例关于这样的实施例，其具有衬底、在衬底上耦合于衬底的第一晶片、第二晶片（其具有处理核并且在第一晶片上耦合于第一晶片）和无源设备（其附连到第一晶片并且耦合于电力供应电路），该第一晶片包括耦合于衬底以接收电力的电力供应电路，该第一晶片耦合于电力供应电路以对处理核供电。
在另外的实施例中，第一晶片具有正面（其包括面对衬底的电路）和面对第二晶片的背面并且其中无源设备安置在背面上。
在另外的实施例中，第一晶片的正面使用通过第一晶片的穿硅通孔而耦合于第二晶片。
在另外的实施例中，第一晶片的背面使用接合线耦合于衬底。
在另外的实施例中，第一晶片具有正面（其包括面对第二晶片的电路）和面对衬底的背面并且其中无源设备安置在第一晶片的正面上。
在另外的实施例中，第一晶片使用焊料凸块连接到第二晶片并且其中无源设备安置在第一晶片的正面上且在焊料凸块之间。
在另外的实施例中，第一晶片使用微凸块、模塑突柱、热超声或热压缩接合部而连接到第二晶片并且其中无源设备安置在第一晶片的正面上且在接合部之间。
在另外的实施例中，第一晶片的正面在焊料凸块之间具有凹陷并且其中无源设备安置在该凹陷内部。
在另外的实施例中，凹陷具有底层和侧壁，其中侧壁朝底层锥形化，并且其中无源设备在锥形化侧壁上具有磁性层。
在另外的实施例中，第一晶片是硅晶片并且其中无源设备是具有在硅晶片的表面上形成的磁性材料的电感器。
在另外的实施例中，无源设备包括耦合于电感器的电容器，这些电容器在第一晶片的表面上形成。
在另外的实施例中，第一晶片是硅晶片并且其中电容器是金属-绝缘体-金属电容器。
在另外的实施例中，无源设备包括3D金属-绝缘体-金属电容器、平面金属-绝缘体-金属电容器、磁芯电感器、条纹电感器、螺旋电感器、螺线管电感器或环形电感器。
在另外的实施例中，衬底包括功率解耦电容器，其在外部电力供应与电力供应电路之间耦合。
在另外的实施例中，电力供应电路包括电压转换器、开关电容器电压转换器、电压调节器或全集成电压调节器。
一些实施例关于堆叠芯片封装，其具有：核晶片，其具有多个处理核；非核晶片，其对于每个处理核具有电力供应电路，每个电力供应电路独立耦合于每个相应处理核来向相应处理核供应电力；封装衬底，其耦合于非核晶片以从外部源接收电力并且向非核晶片的电力供应电路提供电力；多个通过非核晶片的穿硅通孔，用于将数据信号从核晶片运送到封装衬底；和多个无源设备，其在非核晶片与非核晶片之间附连到非核晶片，该多个无源设备每个耦合于电力供应电路。
在另外的实施例中，非核晶片具有面对核晶片的正面并且其中多个无源设备是附连到非核晶片正面的电容器。
一些实施例关于计算设备，其具有系统板、连接到该系统板的通信封装以及处理器封装，其具有衬底、在衬底上耦合于衬底的非核晶片（该非核晶片包括耦合于衬底以接收电力的电力供应电路）、具有处理核并且在非核晶片上耦合于非核晶片的核晶片（该非核晶片耦合于电力供应电路以对处理核供电）和附连到非核晶片并且耦合于电力供应电路的无源设备。
在另外的实施例中，非核晶片具有正面（其包括面对核晶片的电路）和面对衬底的背面，其中无源设备安置在非核晶片正面中的凹陷中。
在另外的实施例中，非核晶片具有面对衬底的正面和面对核晶片的正面，其中无源设备附连到晶片的背面，其中电力供应电路在非核晶片的正面上形成并且通过通孔（通过非核晶片的背面）耦合于无源设备和核晶片。

Claims (20)

1.一种装置，其包括：
衬底；
第一晶片，其在所述衬底上耦合于所述衬底，所述第一晶片包括耦合于所述衬底以接收电力的电力供应电路；
第二晶片，其具有处理核并且在所述第一晶片上耦合于所述第一晶片，所述第一晶片耦合于所述电力供应电路以对所述处理核供电；以及
无源设备，其附连到所述第一晶片并且耦合于所述电力供应电路。
2.如权利要求1所述的装置，其中所述第一晶片具有：正面，其包括面对所述衬底的电路；和面对所述第二晶片的背面，并且其中所述无源设备安置在所述背面上。
3.如权利要求2所述的装置，其中所述第一晶片的正面使用通过所述第一晶片的穿硅通孔而耦合于所述第二晶片。
4.如权利要求2或3所述的装置，其中所述第一晶片的背面使用接合线耦合于所述衬底。
5.如权利要求1-4中任一项所述的装置，其中所述第一晶片具有：正面，其包括面对所述第二晶片的电路；和面对所述衬底的背面，并且其中所述无源设备安置在所述第一晶片的正面上。
6.如权利要求5所述的装置，其中所述第一晶片使用焊料凸块连接到所述第二晶片并且其中所述无源设备安置在所述第一晶片的正面上且在所述焊料凸块之间。
7.如权利要求5或6所述的装置，其中所述第一晶片使用微凸块、模塑突柱、热超声或热压缩接合部而连接到所述第二晶片并且其中所述无源设备安置在所述第一晶片的正面上且在所述接合部之间。
8.如权利要求6所述的装置，其中所述第一晶片的正面在所述焊料凸块之间具有凹陷并且其中所述无源设备安置在所述凹陷内部。
9.如权利要求8所述的装置，其中所述凹陷具有底层和侧壁，其中所述侧壁朝所述底层锥形化，并且其中所述无源设备在锥形化侧壁上具有磁性层。
10.如权利要求1-9中任一项所述的装置，其中所述第一晶片是硅晶片并且其中所述无源设备是具有在所述硅晶片的表面上形成的磁性材料的电感器。
11.如权利要求1-10中任一项所述的装置，其中所述无源设备包括耦合于电感器的电容器，所述电容器在所述第一晶片的表面上形成。
12.如权利要求11所述的装置，其中所述第一晶片是硅晶片并且其中所述电容器是金属-绝缘体-金属电容器。
13.如权利要求11或12所述的装置，其中所述无源设备包括3D金属-绝缘体-金属电容器、平面金属-绝缘体-金属电容器、磁芯电感器、条纹电感器、螺旋电感器、螺线管电感器或环形电感器。
14.如权利要求1-13中任一项所述的装置，其中所述衬底包括功率解耦电容器，其在外部电力供应与所述电力供应电路之间耦合。
15.如权利要求1-14中任一项所述的装置，其中所述电力供应电路包括电压转换器、开关电容器电压转换器、电压调节器或全集成电压调节器。
16.一种堆叠晶片封装，其包括：
核晶片，其具有多个处理核；
非核晶片，其对于每个处理核具有电力供应电路，每个电力供应电路独立耦合于每个相应处理核来向所述相应处理核供应电力；
封装衬底，其耦合于所述非核晶片以从外部源接收电力并且向所述非核晶片的电力供应电路提供电力；
多个通过所述非核晶片的穿硅通孔，用于将数据信号从所述核晶片运送到所述封装衬底；以及
多个无源设备，其在所述非核晶片与所述非核晶片之间附连到所述非核晶片，所述多个无源设备每个耦合于电力供应电路。
17.如权利要求16所述堆叠晶片封装，其中所述非核晶片具有面对所述核晶片的正面并且其中所述多个无源设备是附连到所述非核晶片的正面的电容器。
18.一种计算设备，其包括：
系统板；
通信封装，其连接到所述系统板；以及
处理器封装，其具有：衬底；在所述衬底上耦合于所述衬底的非核晶片，所述非核晶片包括耦合于所述衬底以接收电力的电力供应电路；具有处理核并且在所述非核晶片上耦合于所述非核晶片的核晶片，所述非核晶片耦合于所述电力供应电路以对所述处理核供电；和附连到所述非核晶片并且耦合于所述电力供应电路的无源设备。
19.如权利要求18所述的设备，其中所述非核晶片包括：正面，其包括面对所述核晶片的电路；和面对所述衬底的背面，其中所述无源设备安置在所述非核晶片正面中的凹陷中。
20.如权利要求18所述的设备，其中所述非核晶片具有面对所述衬底的正面和面对所述核晶片的正面，其中所述无源设备附连到所述晶片的背面，其中所述电力供应电路在所述非核晶片的正面上形成并且经由通过所述非核晶片的背面的通孔耦合于所述无源设备和所述核晶片。
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