JP6476132B2 - 基板内結合インダクタ構造 - Google Patents
基板内結合インダクタ構造 Download PDFInfo
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- JP6476132B2 JP6476132B2 JP2015557138A JP2015557138A JP6476132B2 JP 6476132 B2 JP6476132 B2 JP 6476132B2 JP 2015557138 A JP2015557138 A JP 2015557138A JP 2015557138 A JP2015557138 A JP 2015557138A JP 6476132 B2 JP6476132 B2 JP 6476132B2
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- 239000000758 substrate Substances 0.000 title claims description 259
- 238000004804 winding Methods 0.000 claims description 80
- 230000005294 ferromagnetic effect Effects 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 51
- 230000005291 magnetic effect Effects 0.000 claims description 25
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- 238000004891 communication Methods 0.000 claims description 6
- 230000006698 induction Effects 0.000 claims 3
- 229910052751 metal Inorganic materials 0.000 description 60
- 239000002184 metal Substances 0.000 description 60
- 230000008878 coupling Effects 0.000 description 41
- 238000010168 coupling process Methods 0.000 description 41
- 238000005859 coupling reaction Methods 0.000 description 41
- 239000003302 ferromagnetic material Substances 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 15
- 239000010949 copper Substances 0.000 description 15
- 238000005530 etching Methods 0.000 description 15
- 230000006870 function Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000011248 coating agent Substances 0.000 description 10
- 238000000576 coating method Methods 0.000 description 10
- 230000035699 permeability Effects 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 238000005553 drilling Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000003486 chemical etching Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910001289 Manganese-zinc ferrite Inorganic materials 0.000 description 2
- JIYIUPFAJUGHNL-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[Mn++].[Mn++].[Mn++].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Zn++].[Zn++] Chemical compound [O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[O--].[Mn++].[Mn++].[Mn++].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Fe+3].[Zn++].[Zn++] JIYIUPFAJUGHNL-UHFFFAOYSA-N 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005415 magnetization Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910000976 Electrical steel Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000889 permalloy Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
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- H—ELECTRICITY
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2871—Pancake coils
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- H—ELECTRICITY
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
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- H01L23/64—Impedance arrangements
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- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/004—Printed inductances with the coil helically wound around an axis without a core
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/4902—Electromagnet, transformer or inductor
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Description
いくつかの新規の特徴は、第1のインダクタ巻線と、第2のインダクタ巻線と、基板とを含む基板内インダクタ構造に関する。第1のインダクタ巻線は導電性材料を含む。第2のインダクタ巻線は導電性材料を含む。基板は、横方向において第1のインダクタ巻線と第2のインダクタ巻線との間に位置する。基板は、第1のインダクタ巻線と第2のインダクタ巻線の構造上の結合を実現するように構成される。いくつかの実装形態では、第1のインダクタ巻線は、横方向において第2のインダクタ巻線と同一平面内に位置する。いくつかの実装形態では、第1のインダクタ巻線は第1のらせん形状を有し、第2のインダクタ巻線は第2のらせん形状を有する。いくつかの実装形態では、第1のインダクタ巻線および第2のインダクタ巻線は、細長い円形形状を有する。いくつかの実装形態では、基板はシリコン基板である。
図2〜図3は、横結合インダクタ構造の例を示す。いくつかの実装形態では、横結合インダクタ構造は、図1に示しかつ図1で説明したはしご型構造よりも優れておりならびに/あるいは改善された結合を有する小さい有効フットプリント/面積を占有するように設計/配置される。より具体的には、いくつかの実装形態は、図1に示すはしご型構造よりも薄くなるように設計/配置された横結合インダクタ構造を実現する。
図4A、図4Bは、横結合インダクタ構造/基板内インダクタ構造を提供/製造するためのシーケンスを示す。図2、図3の横結合インダクタ構造200を参照しながら、図4A、図4Bのシーケンスについて説明する。しかしながら、図4A、図4Bのシーケンスを、他の横結合インダクタ構造(たとえば、他の基板内結合インダクタ構造)に適用してもよい。
いくつかの実装形態では、結合インダクタ構造を薄くして、結合インダクタ構造の厚さ(たとえば、高さ)をさらに減少させることができる。図5A、図5Bは、薄くされた横結合インダクタ構造/基板内インダクタ構造を提供/製造するためのシーケンスを示す。図2、図3の横結合インダクタ構造200を参照しながら、図5A、図5Bのシーケンスについて説明する。しかしながら、図5A、図5Bのシーケンスを他の横結合インダクタ構造(たとえば、他の基板内結合インダクタ構造)に適用してもよい。
図6は、横結合インダクタ構造を提供/製造するための方法の流れ図である。いくつかの実装形態では、図6の方法を使用して図2および図3の横結合インダクタ構造200ならびに/または図4Bおよび図5Bのインダクタ構造430および530を製造/提供する。
図7は、横結合インダクタ構造を製造するための方法の流れ図である。いくつかの実装形態では、図7の方法を使用して、図2、図3の横結合インダクタ構造200および/または図4B、図5Bのインダクタ構造430、530を製造/提供する。
いくつかの実装形態では、1つまたは複数の結合インダクタ構造(たとえば、インダクタ構造200、430、530)をパッケージオンパッケージ(PoP)構造内の基板上に結合してよい。図8は、結合インダクタ構造を含むパッケージオンパッケージ(PoP)構造800の側面図を示す。図8に示すように、PoP構造800は、第1のパッケージ基板802と、第1の1組のはんだボール804と、第1のダイ806と、第2のパッケージ基板808と、第2の1組のはんだボール810と、第2の1組のダイ812と、第1のインダクタ構造814と、第2のインダクタ構造816とを備える。第1のインダクタ構造814および第2のインダクタ構造816は、図2、図3、図4B、図5Bのインダクタ構造200、430および/または530であってよい。第1のダイ806は論理ダイであってよい。第2の1組のダイ812は、いくつかの実装形態ではスタッキングされたメモリダイであってよい。
いくつかの実装形態では、1つまたは複数の結合インダクタ構造(たとえば、インダクタ構造200、430、530)を半導体パッケージ内の基板上に結合してよい。図9に示すように、ダイ/チップ900はパッケージ基板902上に取り付けられてよい。図9は、パッケージ基板902の表面上の2つの結合インダクタ構造も示す。具体的には、図9は、パッケージ基板902上の第1のインダクタ構造904および第2のインダクタ構造906を示す。第1および第2のインダクタ構造904、906は、1組の配線(たとえば、トレース)を介してダイ900に結合される。いくつかの実装形態では、第1および第2のインダクタ構造904、906は、図2、図3、図4B、および図5Bに示しかつ説明したインダクタ構造200、430、530のうちの1つであってよい。
いくつかの実装形態では、1つまたは複数の結合インダクタ構造(たとえば、インダクタ構造200、430、530)を半導体パッケージ内の基板(たとえば、パッケージ基板)内部に結合してよい。図10および図11は、いくつかの実装形態における基板内の結合インダクタ構造の例を示す。具体的には、図10は、本開示の一態様による、ICパッケージ1000の概略断面図を示す。ICパッケージ1000は、限定はしないが、モバイルフォン、ラップトップコンピュータ、タブレットコンピュータ、パーソナルコンピュータなどの電子デバイス用のICダイ1002(たとえば、メモリ回路、処理回路、アプリケーションプロセッサなど)を含む。ICパッケージ1000、特にICダイ1002は、電子デバイスに関連付けられた電源供給ネットワーク(PDN)(ICパッケージ基板1000の外部のPDNの部分は示されていない)を介して電力管理集積回路(PMIC)(図示せず)から電力を供給され(たとえば、公称供給電圧および電流が与えられ)てよい。
図12は、上述の集積回路、ダイ、またはパッケージのいずれかと統合され得る様々な電子デバイスを示す。たとえば、携帯電話1202、ラップトップコンピュータ1204、および固定位置端末1206は、本明細書で説明する集積回路(IC)1200を含み得る。IC1200は、たとえば、本明細書で説明する集積回路、ダイ、またはパッケージのうちのいずれかであり得る。図12に示されたデバイス1202、1204、1206は、例にすぎない。他の電子デバイスは、限定しないが、モバイルデバイス、ハンドヘルドパーソナル通信システム(PCS)ユニット、携帯情報端末などのポータブルデータユニット、GPS対応デバイス、ナビゲーションデバイス、セットトップボックス、音楽プレーヤ、ビデオプレーヤ、娯楽ユニット、メータ読取り機器などの固定位置データユニット、通信デバイス、スマートフォン、タブレットコンピュータ、またはデータもしくはコンピュータ命令の記憶もしくは取り出しを行う任意の他のデバイス、またはそれらの任意の組合せを含むIC1200を採用することもできる。
104 コア
106a〜106d インダクタ巻線
200 横結合インダクタ構造
202、402、502 基板
204、404、504 第1のインダクタ
206、406、506 第2のインダクタ
208、210、212、214、408、410、412、414、508、510、512、514 端子
401、403、407、409、411、413、501、503、507、509、511、513 キャビティ
420、520 第1の層
430、530 インダクタ構造
422、522 第2の層
800 PoP構造
802 第1のパッケージ基板
804 第1の1組のはんだボール
806 第1のダイ
808 第2のパッケージ基板
810 第1の1組のはんだボール
812 第2の1組のダイ
814 第1のインダクタ構造
816 第2のインダクタ構造
900 ダイ/チップ
902 基板
904 第1の構造
906 第2の構造
908 第1のEVR
910 第2のEVR
1000 ICパッケージ
1002 ICダイ
1004 多層パッケージ基板
1006 はんだボール
1010 離散回路構成要素
1022 第1の金属層
1024 第2の金属層
1026 第3の金属層
1028 第4の金属層
1032、1034、1036 絶縁層
1035 キャビティ
1040 ビア結合構成要素
1200 集積回路
1202 携帯電話
1204 ラップトップコンピュータ
1206 固定位置端末
Claims (14)
- 第1の誘導手段と、
第2の誘導手段と、
シリコンである基板であって、前記第1の誘導手段および前記第2の誘導手段が前記基板におけるキャビティにおいて導電性材料を含み、前記第1の誘導手段および前記第2の誘導手段が前記基板内で横方向において同一平面内に位置し、横方向において前記第1の誘導手段と前記第2の誘導手段との間に前記基板のみが位置する、基板とを備える誘導装置。 - 前記第1の誘導手段は第1のらせん形状を有し、前記第2の誘導手段は第2のらせん形状を有する、または、
前記第1の誘導手段および前記第2の誘導手段は、細長い円形形状を有する、請求項1に記載の誘導装置。 - 前記第1の誘導手段は、第1の端子と第2の端子とを含み、前記第2の誘導手段は、第3の端子と第4の端子とを含む、請求項1に記載の誘導装置。
- 前記第1の誘導手段の厚さは0.2ミリメートル未満である、請求項1に記載の誘導装置。
- 前記基板の第1の側の上に第1の強磁性層をさらに含み、前記第1の強磁性層は前記誘導装置のための磁気遮蔽を実現するように構成される、請求項1に記載の誘導装置。
- 前記基板の前記第1の側と反対の前記基板の第2の側の上に第2の強磁性層をさらに含み、前記第2の強磁性層は前記誘導装置のための磁気遮蔽を実現するように構成される、請求項5に記載の誘導装置。
- 前記誘導装置は、パッケージオンパッケージ(PoP)構造上に集積される、または、前記誘導装置は、パッケージ基板の表面上に集積される、または、前記誘導装置は、パッケージ基板内部に集積される、請求項1に記載の誘導装置。
- 前記誘導装置は、音楽プレーヤ、ビデオプレーヤ、娯楽ユニット、ナビゲーションデバイス、通信デバイス、モバイルデバイス、モバイルフォン、スマートフォン、携帯情報端末、固定位置端末、タブレットコンピュータ、および/またはラップトップコンピュータのうちの少なくとも1つに組み込まれる、請求項1に記載の誘導装置。
- インダクタ構造を提供するための方法であって、
シリコンである基板を設けるステップと、
前記基板においてキャビティを形成するステップと、
導電性材料で前記キャビティを充填して、第1のインダクタ巻線および第2のインダクタ巻線を設けて、前記第1のインダクタ巻線および前記第2のインダクタ巻線が前記基板内で横方向において同一平面内に位置し、前記基板のみが、横方向において前記第1のインダクタ巻線と前記第2のインダクタ巻線との間に位置する、ステップとを含む方法。 - 前記基板を薄くするステップをさらに含む、請求項9に記載の方法。
- 前記基板の第1の側の上に第1の強磁性層を設けるステップをさらに含み、前記第1の強磁性層は前記インダクタ構造のための磁気遮蔽を実現するように構成される、請求項9に記載の方法。
- 前記基板の前記第1の側と反対の前記基板の第2の側の上に第2の強磁性層を設けるステップをさらに含み、前記第2の強磁性層は前記インダクタ構造のための磁気遮蔽を実現するように構成される、請求項11に記載の方法。
- 前記インダクタ構造をパッケージオンパッケージ(PoP)構造上に設けるステップをさらに含む、請求項9に記載の方法。
- 前記誘導装置が、パッケージ基板の第1の表面の上であり、前記パッケージ基板の前記第1の表面の上に取り付けられたダイに電気的に結合される、請求項1に記載の誘導装置。
Applications Claiming Priority (5)
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US201361764310P | 2013-02-13 | 2013-02-13 | |
US61/764,310 | 2013-02-13 | ||
US13/794,558 US20140225706A1 (en) | 2013-02-13 | 2013-03-11 | In substrate coupled inductor structure |
US13/794,558 | 2013-03-11 | ||
PCT/US2014/015380 WO2014126812A1 (en) | 2013-02-13 | 2014-02-07 | In substrate coupled inductor structure |
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US (1) | US20140225706A1 (ja) |
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KR (1) | KR102108707B1 (ja) |
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2013
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2014
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- 2014-02-07 KR KR1020157024507A patent/KR102108707B1/ko active IP Right Grant
- 2014-02-07 ES ES14706428T patent/ES2778872T3/es active Active
- 2014-02-07 WO PCT/US2014/015380 patent/WO2014126812A1/en active Application Filing
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