WO2023232050A1 - 一种晶圆级功率模组及其制作方法 - Google Patents

一种晶圆级功率模组及其制作方法 Download PDF

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Publication number
WO2023232050A1
WO2023232050A1 PCT/CN2023/097285 CN2023097285W WO2023232050A1 WO 2023232050 A1 WO2023232050 A1 WO 2023232050A1 CN 2023097285 W CN2023097285 W CN 2023097285W WO 2023232050 A1 WO2023232050 A1 WO 2023232050A1
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Prior art keywords
wafer
power module
passive component
level power
chip
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PCT/CN2023/097285
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English (en)
French (fr)
Inventor
曾剑鸿
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上海沛塬电子有限公司
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Publication of WO2023232050A1 publication Critical patent/WO2023232050A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the invention belongs to the field of semiconductor technology, and in particular relates to a wafer-level power module and a manufacturing method thereof.
  • Bluetooth headsets people hope that they will be smaller and more beautiful in appearance; like smart watches, they hope that their functions will be more powerful; like smart phones, they hope that they will become thinner and lighter.
  • One of the main factors limiting their development is that the size of the power supply used is too large and too thick, which puts higher requirements on the design of the power supply.
  • FIG. 1A The cross-sectional view of the circuit shown in Figure 1A is shown in Figure 1B and Figure 1C.
  • the chip is embedded in a substrate, and then an inductor is placed above the substrate to form a power module.
  • the substrate is usually made into a large continuous piece, and then the inductor is mounted on the large continuous piece, and finally the large continuous piece substrate is divided into independent units, which has to make the size of the inductor smaller.
  • the size of the substrate is smaller than the size of the substrate to reserve a cutting distance, such as 0.2mm on one side. This waste of extra size leads to performance degradation.
  • the substrate will be pre-cut from the front, that is, the cutting depth is about half the thickness of the substrate.
  • the substrate is still a large continuous piece structure, and then the inductor will be mounted on the substrate, and finally the inductor will be mounted on the substrate.
  • the large connected chip structure is divided into independent units, as shown in Figure 1C. Therefore, the inductor utilization rate of this structure is very high. Compared with Figure 1B, the efficiency will be significantly improved.
  • the thickness that the industry can achieve is basically controlled below 1mm, and the packaging thickness of the substrate is at least 0.15mm, and the thickness of the chip within the substrate is at least 0.15mm, which is the total thickness of the entire substrate.
  • H2 is at least 0.3mm, which accounts for at least 30% of the total thickness of the entire module.
  • the power module is developing in a thinner direction, such as 0.8mm or even 0.5mm.
  • the packaging structure shown in Figure 1C is no longer suitable for future occasions.
  • the purpose of the present invention is to provide a wafer-level power module and a manufacturing method thereof to solve the above technical problems.
  • a first aspect of the present invention provides a wafer-level power module, including: a wafer, the wafer includes a wafer functional area, and the wafer functional area is located on the first surface of the wafer;
  • the passive component includes at least one power pin, the passive component is stacked on the second surface of the wafer, and the wafer functional area is electrically connected from the first surface of the wafer to the second surface of the wafer through a conductive path. Surface, and electrically connected to the power pins of passive components;
  • the conductive paths are attached to the wafer.
  • the conductive path includes at least one conductive hole, and the conductive hole penetrates the wafer substrate.
  • the conductive path forms a pin structure on the second surface of the wafer through the conductive hole for electrical connection with the passive component.
  • the conductive hole is located in the area of the wafer functional area of the wafer.
  • the conductive hole is located outside the area of the wafer functional area of the wafer.
  • the conductive holes are located at the dicing lanes of the wafer.
  • the conductive path includes at least one conductive hole, and the conductive hole extends from the lower surface to the upper surface of the power module.
  • the conductive path includes at least one conductive hole, and the conductive hole is located on a side wall of the power module.
  • the conductive path includes at least one connection layer, and the connection layer is used to electrically connect the chip functional area of the chip and the power pin of the passive component through welding or electroplating.
  • the first surface, the second surface of the wafer substrate and the inner wall of the conductive hole each form a first insulating layer.
  • the conductive hole also has a metal diffusion barrier layer, and the metal diffusion barrier layer is located inside the first insulating layer.
  • a second insulating layer is formed on the surface of the wafer functional area, and the second insulating layer is used to block the SW power pins.
  • the planar size of the power module is the same as the planar size of the chip.
  • the planar size of the passive component is the same as the planar size of the wafer.
  • the passive component is pre-formed, the passive component includes a passive component functional area and a complete power pin, and the passive component is electrically connected to the chip through welding.
  • the preformed passive component is welded to the wafer, and the passive component is molded to form a support above the second surface of the wafer.
  • the passive component is pre-formed, the passive component includes a passive component functional area but does not have a complete power pin, and the passive component is electrically connected to the wafer through electroplating.
  • the passive component is grown and formed on a wafer, and is electrically connected to the wafer through sintering or electroplating.
  • the passive element includes a first passive element and a second passive element, and the wafer, the second passive element and the first passive element are stacked in sequence in the vertical direction.
  • the planar size of the second passive component is the same as the planar size of the wafer.
  • the interconnections between the chip and the second passive component and between the second passive component and the first passive component are respectively formed by welding.
  • the interconnection is formed between the wafer and the second passive component, and/or between the second passive component and the first passive component through sintering or electroplating.
  • the wafer includes a first wafer and a second wafer, and the first wafer, the second wafer and the passive component are stacked in sequence in the vertical direction.
  • the second wafer includes at least one conductive path, the conductive path penetrates the substrate of the second wafer, and the conductive path is located inside or on a side wall of the second wafer.
  • the first wafer is used to implement the power switch function
  • the second wafer is used to implement the control function
  • the planar size of the first wafer is the same as the planar size of the second wafer.
  • the first passive component and the second passive component include an inductor, a capacitor, a transformer, a radio frequency antenna and a filter respectively.
  • a wafer-level power module including: the chip includes a wafer functional area, and the wafer functional area is located on the first surface of the wafer;
  • the passive component includes at least one functional conductive layer and a functional dielectric layer;
  • the passive components are stacked with the chip, and the stacked area is equal to the area of the chip;
  • the wafer functional area and the functional conductive layer are electrically connected through a conductive path; at least one of the conductive paths Part of it is realized by through-hole or semi-through-hole electroplating; the conductive path is placed on the side or middle position of the module;
  • the wafer and the passive component are bonded together through filling materials or directly, and the passive component provides mechanical strength support for the wafer;
  • the functional dielectric layer is disposed between at least one functional conductive layer of the passive component and the first surface of the wafer.
  • the passive element includes a first passive element and a second passive element, and the first passive element and the second passive element are vertically stacked on the second surface of the wafer respectively.
  • the first passive component and the second passive component include an inductor, a capacitor, a transformer, a radio frequency antenna and a filter respectively.
  • the passive component is a multi-channel counter-coupled inductor.
  • the multi-channel counter-coupled inductor includes at least two magnetic units, and the windings of at least two magnetic units share the same magnetic column, so that the lengths of the windings are equal.
  • the input pins and output pins of the windings of the multi-channel anti-coupled inductor are arranged in a staggered manner.
  • the winding of each path of the multi-path anti-coupling inductor has a single turn or multiple turns, and the winding of each path has a multi-strand parallel winding structure.
  • the pin structure of the power module is a pad structure or a ball mounting structure, and the power pins of the power module are distributed on at least one of the upper surface and the lower surface of the power module.
  • the power pins include AC voltage pins and DC voltage pins, the AC voltage pins are located in the middle area of the power module, and the DC voltage pins are located around the power module.
  • the power pins include capacitor power pins, and the capacitor power pins are located in the middle area of the power module.
  • the wafer includes at least one power region.
  • the wafer further includes at least one control area and/or power management area and/or data processing area, and the planar size of the wafer is the same as the planar size of the passive component.
  • the switching frequency of the power region of the wafer is greater than 20 MHz.
  • the switching frequency of the power region of the wafer is greater than 50 MHz, and the planar size of the passive component is the same as the planar size of the wafer.
  • the wafer includes two power areas, and the two power areas are interconnected through a rewiring layer.
  • the redistribution layer includes at least one TSV hole, and the TSV hole is located on a side wall of the wafer.
  • an adhesive layer or a metal shielding layer is provided between the chip and the passive component.
  • the thickness of the wafer is less than 100 ⁇ m.
  • the wafer-level power module includes power pins, the power pins are arranged on the first surface of the wafer, and the second surface of the wafer is between the first surface of the wafer and the passive component. .
  • the wafer-level power module includes power pins placed on the outer surface of the passive component, and the first surface of the wafer is between the second surface of the wafer and the passive component.
  • the passive component includes a capacitor electrically interconnected with the DC power pin of the wafer, and/or the passive component includes a capacitor or magnetic component electrically interconnected with the AC power pin of the wafer.
  • the component, and or the passive component includes a capacitor electrically interconnected with the DC pin of the magnetic component.
  • the output capacitor is integrated with the pin of the wafer-level power module and is arranged on the lower surface of the wafer-level power module.
  • the wafer-level power module further includes a silicon chip capacitor array, and the silicon chip capacitor array includes the output capacitor and part of the capacitance required by the chip during operation.
  • Another aspect of the present invention provides a method for manufacturing a wafer-level power module.
  • the manufacturing method is used to manufacture the wafer-level power module as claimed in claim 46.
  • the manufacturing method includes the following steps:
  • step S3 is also included between steps S2 and S4:
  • the passive component functional conductive layer is electroplated after the wafer and the passive component layer are combined into an integrated stack.
  • Another aspect of the present invention provides a method for manufacturing a wafer-level power module, which includes the following steps:
  • step S6 is specifically:
  • step S7 requires scribing and cutting from the first surface of the wafer
  • the passive component is a pre-formed panel, the passive component and the wafer need to be sealed and fixed.
  • the step S6 specifically includes: growing and forming a passive component on the second surface of the wafer.
  • Another aspect of the present invention provides a method for manufacturing a wafer-level power module, which includes the following steps:
  • S2 Form a first metal layer on the first surface of the wafer, and the first surface of the wafer is a functional surface;
  • step S7 is specifically:
  • step S7 requires scribing and cutting from the first surface of the wafer
  • the passive component is a pre-formed panel, the passive component and the wafer need to be sealed and fixed.
  • the TSV hole is located on the cutting track of the wafer.
  • Another aspect of the present invention provides a method for manufacturing a wafer-level power module, which includes the following steps:
  • S8 Divide from the position of the via hole to form an independent power module.
  • the planar size of the power module is the same as the planar size of the chip.
  • Another aspect of the present invention provides a method for manufacturing a wafer-level power module, which includes the following steps:
  • S8 Divide from the position of the via hole to form an independent power module.
  • the planar size of the power module is the same as the planar size of the chip.
  • the present invention has the following beneficial effects:
  • the present invention directly connects a passive component to the chip. Compared with the existing technology, the chip does not go through the embedding process, thus eliminating the waste of height and size caused by chip packaging. The present invention eliminates the need for embedding. The size of the chip package reduces the thickness by 50% except for passive components.
  • the substrate thickness of the wafer can be made very thin.
  • the total thickness can also be controlled at 50 ⁇ m. Within, it can even be controlled within 30 ⁇ m.
  • the embedding process requires the thickness of the wafer to be at least 150 ⁇ m to ensure that the wafer will not be damaged during the embedding process.
  • the present invention uses passive components as supports to fix the wafer, so the wafer can be made very thin, so that The height of the power module will be significantly reduced.
  • the 30 ⁇ m thickness chip accounts for a very small proportion of the entire power module and can basically be ignored.
  • the thickness of the final power module is basically the same as the thickness of the passive component itself, and the total height can be less than 0.5mm or even less than 0.3mm. , and a wafer-level power module with an area equivalent to that of a chip.
  • the chip thickness accounts for a very small proportion in the entire module, and can even be ignored, especially in situations where module size requirements are very high, such as vertical power supply in data centers and wearables. Power supply and so on.
  • Passive components are mainly related to cross-sectional area.
  • the plane size of the module can be appropriately relaxed to increase the plane size of the passive components and reduce the size of the passive components.
  • Figure 1A is a circuit diagram of a power module in the prior art
  • FIGS. 1B and 1C are schematic structural diagrams of power modules in the prior art
  • Figure 2A is a schematic structural diagram of a wafer-level power module disclosed in an embodiment of the present invention.
  • 2B is a schematic structural diagram of the second metal layer of the wafer-level power module disclosed in an embodiment of the present invention.
  • 2C is a schematic structural diagram of the second insulating layer of the wafer-level power module disclosed in an embodiment of the present invention.
  • Figure 2D is a schematic structural diagram of a wafer-level power module disclosed in another embodiment of the present invention.
  • 3A and 3B are schematic structural diagrams of the second metal layer and conductive holes of the wafer-level power module disclosed in another embodiment of the present invention.
  • 4A and 4B are schematic structural diagrams of conductive holes of a wafer-level power module disclosed in another embodiment of the present invention.
  • 4C is a schematic structural diagram of the third metal layer of the wafer-level power module disclosed in an embodiment of the present invention.
  • Figure 5 is a schematic structural diagram of the first chip and the second chip of the wafer-level power module disclosed in an embodiment of the present invention
  • 6A to 6E are schematic structural diagrams of windings of passive components of a wafer-level power module disclosed in an embodiment of the present invention.
  • FIGS. 7A to 7C are schematic structural diagrams of power pins of a wafer-level power module disclosed in an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of the first passive component and the second passive component of the wafer-level power module disclosed in an embodiment of the present invention.
  • Figure 9 is a schematic structural diagram of the first passive component and the second passive component of the wafer-level power module disclosed in another embodiment of the present invention.
  • 10A to 10C are schematic structural diagrams of a wafer-level power module disclosed in another embodiment of the present invention.
  • FIGS. 11A and 11B are schematic structural diagrams of a wafer-level power module disclosed in another embodiment of the present invention.
  • Figure 12 is a schematic structural diagram of a metal shielding layer of a wafer-level power module disclosed in an embodiment of the present invention.
  • FIGS. 13A to 13F are schematic flow diagrams of a method for manufacturing a wafer-level power module disclosed in an embodiment of the present invention.
  • 14A to 14F are schematic flow diagrams of a method for manufacturing a wafer-level power module disclosed in another embodiment of the present invention.
  • 15A to 15E are schematic flow diagrams of a method for manufacturing a wafer-level power module disclosed in another embodiment of the present invention. picture.
  • 1 passive component 1-1 first passive component; 1-2 second passive component; 2 wafer; 2-1 first wafer; 2-2 second wafer; 3 second metal layer; 4 conductive holes; 5 First metal layer; 6 connection layer; 7 adhesive layer; 8 winding; 9 first insulation layer; 10 second insulation layer; 11 third metal layer; 12 magnetic column; 13 capacitor; 14 power area; 15 control area; 16 power management area; 17 metal shielding layer; 18 TSV hole; 19 via hole; 20 internal metal layer; 21 functional conductive layer; 22 functional dielectric layer.
  • the embodiment of the present invention discloses a wafer-level power module, as shown in Figure 2A, including a chip 2 and a passive component 1.
  • the chip 2 includes a chip functional area, and the chip functional area is located on the first surface of the chip 2 (in the figure is the lower surface of the wafer 2);
  • the passive component 1 includes at least one power pin, the passive component 1 is stacked on the second surface of the wafer 2 (the upper surface of the wafer in the figure), and the wafer functional area is connected from the wafer 2 through a conductive path
  • the first surface of the chip is electrically connected to the second surface of the chip 2 and is electrically connected to the power pin of the passive component 1.
  • the functional area of the chip includes the first metal layer 5; the conductive path is attached to the chip 2, and the conductive path passes through the conductive hole. 4.
  • the pin structure is the second metal layer 3.
  • An adhesive layer 7 is provided between the wafer 2 and the passive component 1.
  • the conductive path is placed on the side or in the middle of the module, and part or all of the conductive path is realized by through-hole or semi-through-hole plating, which can reduce the module soldering points and achieve extremely high reliability.
  • the passive component 1 is a magnetic component, including a magnetic core body and a winding 8.
  • the first end and the second end of the winding 8 of the passive component 1 are connected to the third end of the chip 2 through a connection layer 6.
  • the planar dimensions (X, Y) of the wafer 2 are the same as the planar dimensions (X, Y) of the passive component 1.
  • the same includes approximately the same, which can be defined as the size deviation between the two can be controlled within 0 to 100 ⁇ m. Since the power module is formed by wafer cutting, the planar size of the power module is the planar size of the chip 2 .
  • the SW power pin of the power module is connected to the first end of the winding 8 through a conductive path.
  • Layer 6 is connected, and the VO power pin is connected to the second end of winding 8 through a conductive path through connection layer 6. Since the chip 2 is relatively thin and can be easily damaged by external force, an adhesive layer 7 is provided between the chip 2 and the passive component 1 to firmly bind the passive component 1 and the chip 2. Since the thickness of the passive component 1 is relatively thin, The large and therefore relatively weak wafer 2 can rely on the support of the passive element 1 without being bent. Furthermore, it can be ensured that the pins of the power module have good enough flatness.
  • the pins located on the back of the chip 2 can be the pins of the second metal layer 3 connected to the passive component 1 through the connection layer 6; they can also be long on the second metal layer 3. bump or ball-plant, and then connect to the winding 8 of the passive component 1.
  • the pins of the power module can be directly defined by a solder resist layer on the first metal layer 5 , or they can be grown via bumps or balls.
  • the structure of the embodiment of the present invention is to directly connect a passive component 1 to the chip 2.
  • the chip 2 does not go through the embedding process, thus eliminating the waste of height and size caused by the packaging of the chip 2.
  • the thickness of the chip 2 is required to be at least 150 ⁇ m. If the package of the chip 2 only requires an upper and lower metal layer and an insulating layer, the thickness must be at least 150 ⁇ m. That is to say, the total substrate thickness must be 300 ⁇ m.
  • the embodiment of the present invention eliminates the size of the embedded package, reducing the thickness except for the passive component 1 by 50%.
  • the passive component 1 is mainly related to the cross-sectional area.
  • the plane size of the power module can be appropriately relaxed to increase the area of the passive component 1
  • the plane size reduces the thickness of the passive component 1; if the plane size is extremely strict, the plane size of the chip 2 can be appropriately reduced and the thickness of the passive component 1 can be increased, so that the design of the entire power module is very flexible.
  • the thickness of wafer 2 is less than 100 ⁇ m or even less than 50 ⁇ m. Since the wafer functional area of the substrate of wafer 2 is often less than 10 ⁇ m, the thickness of the substrate of wafer 2 can be made very thin. In addition, The total thickness of the passivation layer and conductive paths on the substrate surface can also be controlled within 50 ⁇ m, or even within 30 ⁇ m. Compared with the existing technology, the embedding process requires the thickness of the wafer 2 to be at least 150 ⁇ m to ensure that the wafer 2 will not be damaged during the embedding process.
  • the passive component 1 is used as a support to fix the wafer 2, so the wafer can be 2 is made very thin, which greatly reduces the height of the power module.
  • the 30 ⁇ m-thick chip 2 accounts for a very small proportion of the entire power module and is basically negligible.
  • the thickness of the final power module is basically the same as the thickness of the passive component 1 itself. Consistent, it is possible to achieve a WLCSM (Wafer Level Chip Size Module) with a total height less than 0.5mm or even less than 0.3mm and an area equivalent to that of wafer 2.
  • WLCSM Wafer Level Chip Size Module
  • the structure of the embodiment of the present invention makes the thickness of the chip 2 account for a very small proportion in the entire power module, and can even be ignored. This is especially the case where the size of the power module is very demanding, such as vertical power supply in data centers, power supply for wearables, etc.
  • a first insulating layer 9 is formed on the first surface, the second surface of the substrate of the wafer 2 and the inner wall of the conductive hole 4 respectively.
  • the substrate is a semiconductor, which is between a conductor and an insulator, a first insulating layer 9 is formed on both the inner wall of the conductive hole 4 and the first and second surfaces of the substrate of the wafer 2 to achieve conductivity.
  • the hole 4 is electrically insulated from the substrate and the second metal layer 3 is electrically isolated from the substrate.
  • the conductive hole 4 can be a through hole or a semi-through hole formed by laser or etching, and the through hole or semi-through hole is electroplated to electrically connect the wafer functional area and the functional conductive layer; or the wafer functional area and the functional conductive layer can be electrically connected through wiring. Electrical connection between functional conductive layers.
  • the metal diffusion barrier layer is located inside the first insulating layer 9.
  • the metal diffusion barrier layer is located between the first insulating layer 9 and the conductive hole 4.
  • the purpose is to further prevent copper atoms from diffusing to the substrate at high temperatures (such as 400° C.) and avoid forming a path between the conductive hole 4 and the substrate.
  • Ti, Ta, TaN and TiN can be used to make the metal diffusion barrier layer.
  • the material of the first insulating layer 9 includes silicon dioxide (SiO2) or silicon nitride (Si3N4).
  • a second insulating layer 10 is formed on the surface of the wafer functional area.
  • the second insulating layer 10 is used to block the SW power pin. As shown in FIG. 2C, since the SW power pin is the middle point, and Generally, the transition is not induced, so a second insulating layer 10 is provided on the surface of the first metal layer 5 to achieve insulation between the power module and the system board. This will allow the system board to route its wiring more freely without having to avoid that midpoint.
  • the second metal layer 3 is omitted on the second surface of the wafer 2, so that the conductive hole 4 can be directly connected to the passive component 1 through the connection layer 6, resulting in the structure shown in Figure 2D.
  • the first insulating layer 9 does not exist on the second surface of the wafer 2.
  • the realization of this structure can be based on the structure of Figure 2B, mechanically grinding the second surface of the wafer 2, and removing the second metal layer. 3 and the first insulating layer 9 located on the second surface of the wafer 2 is removed, and the substrate layer can even be further polished to make it thinner.
  • the insulation between the passive component 1 and the substrate can be achieved through the adhesive layer 7 .
  • the adhesive layer 7 here not only plays the role of electrical insulation but also plays the role of fixing and supporting the wafer 2 .
  • the second surface of the wafer 2 does not necessarily only represent the initial surface of the substrate processing.
  • the substrate of the wafer 2 may be subsequently thinned through mechanical grinding, and the thinned surface may also be called the second surface.
  • the conductive circuit structure can also be as shown in Figure 3A.
  • the conductive holes 4 are located around the first wafer 2-1, and the first and second ends of the winding 8 of the passive component 1 are close to the middle area. , at this time, the connection between the first chip 2-1 and the passive component 1 needs to be transitioned through the second metal layer 3.
  • the conductive holes 4 of the first chip 2-1 and the pins of the winding 8 of the passive component 1 can be distributed more freely through the second metal layer 3 without being constrained by each other. For directly laying the capacitor 13 or the inductor on the first chip 2 - 1 , transition wiring can still be performed through the second metal layer 3 .
  • one end of the winding 8 needs to be connected to multiple conductive holes 4 to achieve smaller on-resistance, as shown in Figure 3B.
  • the conductive hole 4 is located at the dicing lane of the wafer. As shown in FIG. 4A , the conductive hole 4 is provided on the side wall of the wafer 2 and then extends to the first metal layer 5 on the wafer 2 and The second metal layer 3 forms two external end surfaces. This structure no longer occupies the internal space of the substrate, allowing the chip 2 to be more efficiently utilized, especially for applications with high pin density. Due to accuracy and contamination issues, chip drilling will damage the functional area of the chip. For example, fast and low-cost laser drilling, light will diffract and damage the functional area. Therefore, it is often necessary to avoid a large distance. If you want high precision and little pollution, you need a very expensive dry etching method.
  • the conductive holes 4 are formed on the dicing lanes of the entire wafer. After dicing, half of the conductive holes 4 are allocated to two adjacent units, such as the metal on both sides of the middle wafer unit in Figure 4B. That is the side metal on the left and right sides of Figure 4A. Therefore, in comparison, this embodiment will further reduce the area occupied by the conductive hole 4 . Because the dicing channel wafer itself has it, and the functional area only needs to be avoided on one side of the via hole.
  • the conductive holes 4 shown in FIG. 4B are square. Of course, they can also be in a circular array, elliptical shape, etc., and are not limited here.
  • the chip unit can be multiple switch tubes connected in parallel or in series.
  • the corresponding cutting method may be two chip units cut off as a whole, or four chip units as a whole, or six chips.
  • the unit is a whole and so on.
  • the third metal layer can be continuously grown on the periphery of the first metal layer 5 of each wafer unit.
  • Metal layer 11 this third metal layer 11 interconnects multiple units to achieve a complete multi-phase circuit, as shown in Figure 4C.
  • the wafer 2 includes a first wafer 2-1 and a second wafer 2-2. As shown in Figure 5, the second wafer 2- is disposed between the first wafer 2-1 and the passive component 1. 2.
  • the first chip 2-1 is defined as a switching device containing a driver
  • the second chip 2-2 is defined as a control device.
  • the power module of the present invention can also integrate control functions. In this way, the connection between the control device and the switching device can be solved inside the power module, and the entire power module will have fewer pins, making it more flexible and convenient for customers to use.
  • an adhesive layer 7 can be respectively provided between them.
  • the first end of the winding 8 will be connected to the conductive path of the second chip 2-2 through the connection layer 6, and then connected to the conductive path of the first chip 2-1 through the connection layer 6, and finally an AC voltage will be formed at the bottom of the power module (Take SW as an example) and DC voltage (take VO as an example) power pin.
  • the passive component 1 is a multi-channel integrated inductor
  • the inductor structure is a four-channel coupled inductor or a coupling transformer.
  • the multi-channel integrated inductor includes at least two magnetic units, and the windings 8 of at least two magnetic units are shared. The same magnetic column 12 is used to make the lengths of the windings 8 equal.
  • the input pins and output pins of the winding 8 of the multi-channel integrated inductor are staggered. Taking Figure 6A as an example, the cross-sectional structure along the AA' direction is shown in Figure 6C.
  • the formed output pins can be AC and DC.
  • SW1-VO1-SW3-VO3 are arranged in a staggered manner, and the pin arrangement of the corresponding power module is also staggered.
  • the winding 8 of each channel of the multi-channel integrated inductor has a single turn or multiple turns, and the winding 8 of each channel of the multi-channel integrated inductor has a multi-strand parallel winding structure, as shown in Figure 6D.
  • the windings 8 corresponding to the two magnetic columns 12 can share one magnetic column 12 .
  • SW and VO are arranged in a non-staggered manner, mainly to make the lengths of the two windings 8 approximately equal, so that the current sharing effect will be better.
  • each winding 8 can have a single turn, multiple turns, or multiple parallel windings; the multi-channel inductor can also be a multiple-channel uncoupled inductor or a multi-winding transformer, which will not be described again here.
  • the power pins of the power module are distributed on at least one of the upper surface and the lower surface of the power module.
  • the power pins include AC voltage pins and DC voltage pins.
  • the AC voltage pins It is located in the middle area of the power module, and the DC voltage pins are located around the power module.
  • the AC voltage pins are located in the middle of the power module, and the DC voltage pins are located at the edge of the power module.
  • the advantages of this embodiment That is, the DC voltage pins are located on the edge to facilitate customer wiring. Since the AC voltage pins are placed in the middle area, it will naturally not hinder the DC part from being wired outwards, making it very flexible for customers to use.
  • the conductive hole 4 can be formed by laser drilling first and then electroplating.
  • the cost of laser drilling is much lower than that of dry etching, but the energy of this method is relatively large and the damage to the functional area is obvious.
  • the AC voltage pin is set in the middle of the power module. Compared with the dispersed setting, this centralized setting will greatly reduce its footprint, as shown in Figure 7B. In other words, if it is dispersedly arranged, each conductive hole 4 requires an area of a safe area. If multiple holes are superimposed, the area of the safe area will be very large. However, if it is arranged in a centralized manner, all the holes can be Just need a safe area.
  • the devices stacked on the chip 2 can be passive components 1, such as inductors, transformers, capacitors 13, etc.
  • the passive component 1 includes a first passive component 1-1 and a second passive component 1-2.
  • the first passive component 1-1 and the second passive component 1-2 are vertically stacked on the wafer 2 respectively. on the second surface.
  • an inductor and a capacitor 13 can be placed above the chip 2 to form a complete closed loop.
  • capacitor 13 is the input capacitor; for boost, capacitor 13 is the output capacitor.
  • the gaps between the components should be filled with filling material, such as using the same adhesive material, to avoid stress on the wafer 2.
  • the wafer 2, the second passive component 1-2 and the first passive component 1-1 are stacked sequentially in the vertical direction, and the planar size of the second passive component 1-2 is equal to the planar size of the wafer 2.
  • interconnections are formed through welding between the chip 2 and the second passive component 1-2, and between the second passive component 1-2 and the first passive component 1-1.
  • the capacitor 13 can be laid on the wafer 2 first, and then the inductor can be laid. At this time, the capacitor layer 13 is located between the inductor and the chip 2, forming a complete closed loop.
  • the area of tiled capacitor 13 is equivalent to the area of chip 2, and the capacitance value of capacitor 13 can be made very large to fully meet the decoupling requirements of the power module.
  • Making the two capacitive electrodes as close as possible can make the input loop very small and reduce the loop inductance.
  • the capacitor 13 is close to the chip 2 and the magnetic element is above the capacitor 13. Therefore, the capacitor 13 not only has a capacitor electrode, but also a transition electrode that assists the interconnection between the magnetic element and the chip 2.
  • the capacitor 13 may be a silicon chip capacitor array, and the silicon chip capacitor array includes an output capacitor and/or a part of the capacitance required by the chip during operation.
  • each passive component 1 can be preformed first and then stacked on the wafer 2 .
  • the stacking accuracy will lead to larger apertures, or the need to lay copper on the back to enlarge the pads. This results in complex processes and waste of space.
  • the required magnetic elements or capacitive elements can be grown on the back side of the wafer 2 using the wafer 2 as a carrier to form a functional conductive layer 21; adjacent to the functional conductive layer 21, include at least one functional medium Layer 22, this functional dielectric layer can be provided with the magnetic material of the magnetic element or the dielectric material of the capacitor.
  • a semi-formed passive device (with a functional area but no complete lead-out electrode) is connected to the wafer 2 through electroplating.
  • the wafer semiconductor process precision can be used for interconnection, that is, the chip 2 and the passive device are electrically interconnected through drilling and electroplating processes. Accuracy, space utilization, reliability and even production efficiency are greatly improved.
  • the same process manufacturing method can be used to dispose the capacitor 13 on the bottom surface of the chip 2 .
  • the pins of the capacitor 13 are integrated with the power pins of the power module, and both are disposed on the power module. The lower surface of the module.
  • connection between the capacitor 13 and the chip 2 or the connection between the inductor and the capacitor 13 can not only be through welding, in which case the material of the connection layer 6 is different from the material of the conductive hole 4; it can also be based on the chip. 2.
  • the main body grows the connection layer 6 from bottom to top. At this time, the connection layer 6 and the conductive hole 4 are made of the same material.
  • wafer technology is used to produce complete functional power modules, but it is not limited to power supply modules.
  • a radio frequency power amplifier has a filter and even an antenna on the back, that is, the power module is cut by a wafer process, and the plane size of the power module is the plane size of chip 2; in the power module, as much space as possible is provided for passive components.
  • the thickness of the device, that is, the wafer 2 is as thin as possible, 100 ⁇ m or even less than 50 ⁇ m.
  • the area of the chip 2 is also required to be equivalent to the passive device.
  • the operating frequency of the power area 14 of the chip 2 of the present invention is above 20 MHz or even 100 MHz, that is, reducing the area of the passive device so that it is equivalent to the area of the chip 2; second, as much as possible in the chip 2 Integrate more non-power functions, such as the control area 15 and the power management area 16.
  • the power management area 16 is the intelligent management function of the power module, that is, Power Management, or other digital management and data processing functions, so that the area of the chip 2 is the same as that of the power module.
  • the area of passive components is comparable.
  • the wafer 2 may include two power regions 14 interconnected through a rewiring layer that includes at least one TSV hole located on a sidewall of the wafer.
  • the chip functional area is electrically connected to the top surface of the power module to achieve Double-sided pinout or double-sided wiring makes the pin distribution more flexible.
  • the heat dissipation effect has also been improved.
  • More functions can also be set, such as the top wiring being set up as an antenna for RF transmitting and receiving.
  • a structural support is provided between the passive component 1 and the wafer 2, especially if the wafer 2 is very thin, in this way its mechanical strength can be reinforced.
  • the metal shielding layer 17 in the support member can play a shielding role, isolating the inductor and the chip, and preventing the chip 2 from electromagnetic interference.
  • FIGS 13A to 13F illustrate a method of manufacturing a wafer-level power module in an embodiment of the present invention. The steps are as follows:
  • S2 Form the TSV hole 18 on the wafer substrate. In this step, the TSV hole 18 does not penetrate the wafer substrate, as shown in Figure 13A;
  • S7 Divide to form an independent power module.
  • the plane size of the power module is the same as that of the wafer 2, as shown in Figure 13F, to form a power module structure as shown in Figure 2D.
  • the TSV hole 18 is usually formed by dry etching, but it can also be achieved by laser drilling;
  • step S6 is specifically:
  • step S7 requires scribing and cutting from the first surface of the wafer
  • the passive component 1 is a preformed panel, the passive component 1 and the wafer need to be fixed by caulking.
  • step S6 specifically includes: growing the passive component 1 on the second surface of the wafer.
  • the power module structure shown in Figure 2A is formed by the following manufacturing method:
  • S6 Fill the inside of the TSV hole 18 with metal, and form the second metal layer 3 on the second surface of the wafer;
  • S8 Divide to form an independent power module.
  • the plane size of the power module is the same as the plane size of the chip.
  • the power module structure as shown in FIG. 4A can be manufactured.
  • Figures 14A to 14F show a method of manufacturing a wafer-level power module in another embodiment of the present invention. The steps are as follows:
  • S8 Divide from the position of the via hole 19 to form an independent power module.
  • the plane size of the power module is the same as the plane size of the chip 2 to form a power module structure as shown in Figure 11B.
  • the passive component 1 can be an inductor, a capacitor 13, a transformer, etc., and the passive component 1 can be laid using LTCC (low-temperature sintering ceramics, CVD vapor deposition and other processes).
  • LTCC low-temperature sintering ceramics, CVD vapor deposition and other processes.
  • FIGS 15A to 15E show a method of manufacturing a wafer-level power module in another embodiment of the present invention. The steps are as follows:
  • S8 Divide from the position of the via hole 19 to form an independent power module.
  • the plane size of the power module is the same as the plane size of the chip 2 to form a power module structure as shown in Figure 11A.
  • etching can be performed by laser etching or chemical etching.
  • Processes S6 and S7 can also be combined into one process, that is, using a fully additive metallization method.
  • a metal wiring layer with patterns is directly electroplated on the first surface of the wafer.
  • the patterns represent different of pins.
  • the "equal” or “same” or “equal to” disclosed in the present invention must consider the parameter distribution of the project, and the error distribution is within ⁇ 30%.

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Abstract

本发明公开了一种晶圆级功率模组及其制作方法，包括晶片和被动元件，晶片包括一晶片功能区，晶片功能区位于晶片的第一表面；被动元件包括至少一功率引脚，被动元件堆叠于晶片的第二表面上，晶片功能区通过一导电通路从晶片的第一表面电性连接至晶片的第二表面，并与被动元件的功率引脚电性连接；导电通路依附于晶片。本发明直接在晶片上连接一被动元件，相比现有技术，该晶片未经过埋入工序，省去了晶片封装带来的高度尺寸的浪费，本发明省去了嵌埋晶片封装的尺寸，使得除被动元件之外的厚度降低了至少50％；本发明对晶圆进行切割形成功率模组，功率模组的平面尺寸与晶圆切割后的晶片平面尺寸相同，省去了埋入工序带来的平面尺寸的浪费。

Description

一种晶圆级功率模组及其制作方法 技术领域
本发明属于半导体技术领域，尤其涉及一种晶圆级功率模组及其制作方法。
背景技术
随着经济社会的不断发展，人们对智能设备的依赖越来越强，像蓝牙耳机、智能手机、智能手表等。如蓝牙耳机，人们更加希望它能更加小巧，外观更加精美；如智能手表，希望它的功能更加强大；如智能手机，希望它能越来越薄，越来越轻。而限制它们发展的一大主要因素就是所用电源的尺寸太大而且太厚，这就对电源的设计提出了更高的要求。
如图1A所示的电路，其结构的截面图如图1B、图1C所示。从图中可以看出，晶片是埋入到一基板内，然后在基板的上方放置电感组成一电源模块。如图1B所示，为满足更加高效的生产，通常会将基板做成大连片，然后大连片上贴装电感，最后分割大连片的基板使其成为独立的单元，这就不得不让电感的尺寸小于基板的尺寸以预留切割距离，例如单边预留0.2mm，这种额外尺寸的浪费导致性能下降。因此，为解决该问题，会将基板先从正面预切，即切割深度为基板厚度的一半左右，此时基板仍是大连片的结构，然后再该基板上贴装电感，最后从基板的底面将大连片结构分割成独立的单元，如图1C所示，因此该结构的电感利用率非常高，相比图1B来说，效率会得到明显提升。
然而，对于图1C所示的电源模块，业界能做到的厚度基本都控制在1mm以下，而其中基板的封装厚度至少0.15mm，基板内晶片的厚度至少0.15mm，也就是整个基板的总厚度H2至少0.3mm，这就占了整个模块总厚度的至少30％。根据市场需求，该电源模块正往更薄的方向发展，例如0.8mm甚至0.5mm，图1C所示的封装结构已不再适用于未来场合。
发明内容
有鉴于此，本发明的目的在于提供一种晶圆级功率模组及其制作方法，以解决上述技术问题。
本发明第一方面提供了一种晶圆级功率模组，包括：晶片，所述晶片包括一晶片功能区，所述晶片功能区位于晶片的第一表面；
被动元件，所述被动元件包括至少一功率引脚，所述被动元件堆叠于晶片的第二表面上，所述晶片功能区通过一导电通路从晶片的第一表面电性连接至晶片的第二表面，并与被动元件的功率引脚电性连接；
所述导电通路依附于晶片。
优选的，所述导电通路包括至少一导电孔，所述导电孔贯穿晶片衬底。
优选的，所述导电通路通过导电孔在晶片的第二表面形成用于与被动元件电性连接的引脚结构。
优选的，所述导电孔位于晶片的晶片功能区的区域内。
优选的，所述导电孔位于晶片的晶片功能区的区域外。
优选的，所述导电孔位于晶圆的切割道位置。
优选的，所述导电通路包括至少一导电孔，所述导电孔从功率模组的下表面延伸至上表面。
优选的，所述导电通路包括至少一导电孔，所述导电孔位于功率模组的侧壁。
优选的，所述导电通路包含至少一连接层，所述连接层用于将晶片的晶片功能区与被动元件的功率引脚通过焊接或电镀的方式电性连接。
优选的，所述晶片衬底的第一表面、第二表面以及导电孔的内壁分别形成一第一绝缘层。
优选的，所述导电孔内还具有一金属扩散阻挡层，所述金属扩散阻挡层位于第一绝缘层内侧。
优选的，所述晶片功能区的表面形成有第二绝缘层，所述第二绝缘层用于阻挡SW功率引脚。
优选的，所述功率模组的平面尺寸与晶片的平面尺寸相同。
优选的，所述被动元件的平面尺寸与晶片的平面尺寸相同。
优选的，所述被动元件预先成型，所述被动元件包括被动元件功能区和完整的功率引脚，所述被动元件通过焊接与晶片电性连接。
优选的，在晶圆切割前，预先成型的所述被动元件焊接在晶圆上，所述被动元件在晶片的第二表面上方塑封形成支撑。
优选的，所述被动元件预先半成型，所述被动元件包括被动元件功能区，但不具有完整的功率引脚，所述被动元件通过电镀与晶片电性连接。
优选的，所述被动元件在晶圆上生长成型，并通过烧结或电镀与晶片电性连接。
优选的，所述被动元件包括第一被动元件和第二被动元件，所述晶片、第二被动元件和第一被动元件在垂直方向上依次堆叠设置。
优选的，所述第二被动元件的平面尺寸与晶片的平面尺寸相同。
优选的，所述晶片与第二被动元件之间、第二被动元件与第一被动元件之间，分别通过焊接形成互联。
优选的，所述晶片与第二被动元件之间，和/或，第二被动元件与第一被动元件之间，通过烧结或电镀形成互联。
优选的，所述晶片包括第一晶片和第二晶片，所述第一晶片、第二晶片和被动元件在垂直方向上依次堆叠设置。
优选的，所述第二晶片包括至少一导电通路，所述导电通路贯穿第二晶片的衬底，所述导电通路位于第二晶片的内部或侧壁。
优选的，所述第一晶片用于实现功率开关功能，所述第二晶片用于实现控制功能，所述第一晶片的平面尺寸与第二晶片的平面尺寸相同。
优选的，所述第一被动元件和第二被动元件分别包括电感、电容、变压器、射频天线和滤波器。
本发明另一方面提供了一种晶圆级功率模组，包括：所述晶片包括一晶片功能区，所述晶片功能区位于晶片的第一表面；
被动元件，所述被动元件包括至少一功能导电层和功能介质层；
所述被动元件与晶片堆叠，堆叠后的占地面积与晶片面积相等；
所述晶片功能区与所述功能导电层通过一个导电通路电性连接；所述导电通路的至少 一部分由通孔或者半通孔电镀实现；所述导电通路置于模组侧面或者中间位置；
所述晶片与被动元件通过填充材料贴合或者直接贴合，且被动元件为晶片提供机械强度支撑；
所述功能介质层设置于所述被动元件的至少一功能导电层与所述晶片的第一表面之间。
优选的，所述被动元件包括第一被动元件和第二被动元件，所述第一被动元件和第二被动元件分别垂直堆叠在晶片的第二表面上。
优选的，所述第一被动元件和第二被动元件分别包括电感、电容、变压器、射频天线和滤波器。
优选的，所述被动元件为多路反耦合电感。
优选的，所述多路反耦合电感包括至少两个磁性单元，至少两个所述磁性单元的绕组共用同一磁柱，以使绕组的长度相等。
优选的，所述多路反耦合电感的绕组的输入引脚和输出引脚交错排布。
优选的，所述多路反耦合电感的每一路的绕组为单匝或多匝，且每一路的绕组为多股并绕结构。
优选的，所述功率模组的引脚结构为焊盘结构或植球结构，所述功率模组的功率引脚分布在功率模组的上表面和下表面中的至少一个表面。
优选的，所述功率引脚包括交流电压引脚和直流电压引脚，所述交流电压引脚位于功率模组的中间区域，所述直流电压引脚位于功率模组的四周。
优选的，所述功率引脚包括电容功率引脚，所述电容功率引脚位于功率模组的中间区域。
优选的，所述晶片包括至少一功率区。
优选的，所述晶片还包括至少一控制区和/或电源管理区和/或数据处理区，所述晶片的平面尺寸与被动元件的平面尺寸相同。
优选的，所述晶片的功率区的开关频率大于20MHz。
优选的，所述晶片的功率区的开关频率大于50MHz，所述被动元件的平面尺寸与晶片的平面尺寸相同。
优选的，所述晶片包括两个功率区，两个所述功率区通过再布线层进行互联。
优选的，所述再布线层包括至少一TSV孔，所述TSV孔位于所述晶片的侧壁。
优选的，所述晶片与被动元件之间设置有粘结层或金属屏蔽层。
优选的，所述晶片的厚度小于100μm。
优选的，所述晶圆级功率模组包括功率引脚，所述功率引脚设置在所述晶片的第一表面，所述晶片的第二表面在晶片第一表面和所述被动元件之间。
优选的，所述晶圆级功率模组包括功率引脚所述功率引脚放置于所述被动元件的外侧表面，所述晶片的第一表面在晶片第二表面和所述被动元件之间。
优选的，所述被动元件包括与所述晶片的直流功率引脚电性互连的电容，和/或，所述被动元件包括与所述晶片的交流功率引脚电性互连的电容或磁性元件，和或，所述被动元件包括与磁性元件的直流引脚电性互连的电容。
优选的，还包括输出电容，所述输出电容集成所述晶圆级功率模组的引脚设置于所述晶圆级功率模组的下表面。
优选的，所述晶圆级功率模组还包括硅片电容阵列，所述硅片电容阵列包括所述输出电容和所述晶片在工作时所需的部分电容。
本发明另一方面提供一种晶圆级功率模组的制造方法，所述制造方法用于制造如权利要求46所述的晶圆级功率模组，所述制造方法包括如下步骤：
S1.将多个所述晶片依附于治具减薄后，与多个所述被动元件层紧密结合，形成一体叠构；
S2.通过激光或者蚀刻等工艺开通孔或者半通孔，并对通孔或半通孔电镀，将所述晶片功能区和所述功能导电层进行电性连接；
S4.通过晶片切割工艺，将多个模组分离、测试、包装。
优选的，在步骤S2和S4之间还包括步骤S3：
S3.将晶圆的第二表面处进行减薄。
优选的，所述被动元件功能导电层在所述晶圆和被动元件层结合为一体叠构后电镀而成。
本发明另一方面提供了一种晶圆级功率模组的制作方法，包括如下步骤：
S1：提供一整张晶圆；
S2：在所述晶圆的衬底上形成TSV孔，在该步骤中所述TSV孔不贯穿晶圆衬底；
S3：在所述TSV孔的内壁形成第一绝缘层；
S4：在所述TSV孔内部填充金属，并在晶圆衬底的第一表面形成第一金属层；
S5：减薄晶圆的第二表面，使TSV孔内部的金属外露，将空间留给被动元件；
S6：在所述晶圆的第二表面设置被动元件；
S7：划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
优选的，所述步骤S6具体为：
若被动元件是分立的，则还需要将被动元件塑封形成塑封体，以支撑晶圆，且步骤S7需要从晶圆的第一表面进行划片切割；
若被动元件是预成型的拼板，则需要将被动元件与晶圆填缝固定。
优选的，所述步骤S6具体为：在所述晶圆的第二表面生长形成被动元件。
本发明另一方面提供了一种晶圆级功率模组的制作方法，包括如下步骤：
S1：提供一整张晶圆；
S2：在所述晶圆的第一表面上形成第一金属层，所述晶圆的第一表面为功能面；
S3：将所述晶圆的第一表面固定在载具上后，对晶圆进行减薄，将空间留给被动元件；
S4：从所述晶圆的第二表面向内形成TSV孔，所述TSV孔延伸至第一金属层；
S5：在所述TSV孔的内壁及晶圆的第二表面上形成第一绝缘层；
S6：在所述TSV孔内部填充金属，并在晶圆的第二表面上形成第二金属层；
S7：在所述晶圆的第二表面设置被动元件；
S8：划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
优选的，所述步骤S7具体为：
若被动元件是分立的，则还需要将被动元件塑封形成塑封体，以支撑晶圆，且步骤S7需要从晶圆的第一表面进行划片切割；
若被动元件是预成型的拼板，则需要将被动元件与晶圆填缝固定。
优选的，所述TSV孔的位置位于晶圆的切割道上。
本发明另一方面提供了一种晶圆级功率模组的制作方法，包括如下步骤：
S1：提供一整张晶圆；
S2：在所述晶圆的第二表面铺设被动元件；
S3：形成导通孔，所述导通孔贯穿晶圆和被动元件；
S4：在所述导通孔内形成第一绝缘层；
S5：在被动元件的表面控深钻孔，在导通孔的一端形成一宽度更宽的导通孔；
S6：在晶圆的第一表面、被动元件的表面和导通孔内形成金属层；
S7：蚀刻，在晶圆的第一表面和被动元件的表面分别形成所需的引脚；
S8：从导通孔位置进行划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
本发明另一方面提供了一种晶圆级功率模组的制作方法，包括如下步骤：
S1：提供一整张晶圆；
S2：在所述晶圆的第二表面铺设被动元件，所述被动元件内部具有内部金属层；
S3：从晶圆的第一表面向内形成导通孔，使得内部金属层外露；
S4：在所述导通孔内形成第一绝缘层；
S5：去除位于内部金属层外的部分第一绝缘层，使得部分内部金属层外露；
S6：在所述导通孔内填充金属，在晶圆的第一表面形成金属层；
S7：蚀刻，在晶圆的第一表面形成所需的引脚；
S8：从导通孔位置进行划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
与现有技术相比，本发明具有以下有益效果：
(1)本发明直接在晶片上连接一被动元件，相比现有技术，该晶片未经过埋入工序，也就省去了晶片封装带来的高度尺寸的浪费，本发明省去了嵌埋晶片封装的尺寸，使得除被动元件之外的厚度降低了50％。
(2)由于晶片衬底的有效功能区往往只有不到10μm，使得晶片的衬底厚度能做的非常薄，加上衬底表面的钝化层以及导电层，总的厚度也能控制在50μm以内，甚至可以控制在30μm以内。对比现有技术，埋入工艺需要晶片的厚度至少150μm，才能保证埋入过程中晶片不会受损，而本发明因为以被动元件做支撑，固定晶片，所以可以将晶片做的非常薄，使得功率模组的高度会有大幅度的降低。换句话说，30μm厚度的晶片在整个功率模组中占比微乎其微，基本可以忽略不计，最终形成的功率模组厚度基本与被动元件本身的厚度一致，可以实现总高度小于0.5mm甚至小于0.3mm，而面积与晶片相当的晶圆级功率模组。
(3)通过本发明所述的结构，使得晶片厚度在整个模组中占比非常小，甚至可以忽略不计，尤其是对模组尺寸要求很高的场合，比如数据中心的垂直供电，穿戴品供电等等。
(4)被动元件主要和截面积有关，针对不同的应用场合，如果对厚度要求极为严苛，可以将模组的平面尺寸适当放开，以此来增大被动元件的平面尺寸，降低被动元件的厚度；如果对平面尺寸较为极为严苛，可以适当的将晶片平面尺寸缩小，增加被动元件的厚度，这样整个模组的设计就非常灵活。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为现有技术中的功率模组的电路图；
图1B和图1C为现有技术中的功率模组的结构示意图；
图2A为本发明一实施例所公开的晶圆级功率模组的结构示意图；
图2B为本发明一实施例所公开的晶圆级功率模组的第二金属层的结构示意图；
图2C为本发明一实施例所公开的晶圆级功率模组的第二绝缘层的结构示意图；
图2D为本发明另一实施例所公开的晶圆级功率模组的结构示意图；
图3A和图3B为本发明另一实施例所公开的晶圆级功率模组的第二金属层及导电孔的结构示意图；
图4A和图4B为本发明另一实施例所公开的晶圆级功率模组的导电孔的结构示意图；
图4C为本发明一实施例所公开的晶圆级功率模组的第三金属层的结构示意图；
图5为本发明一实施例所公开的晶圆级功率模组的第一晶片和第二晶片的结构示意图；
图6A至图6E为本发明一实施例所公开的晶圆级功率模组的被动元件的绕组的结构示意图；
图7A至图7C为本发明一实施例所公开的晶圆级功率模组的功率引脚的结构示意图；
图8为本发明一实施例所公开的晶圆级功率模组的第一被动元件和第二被动元件的结构示意图；
图9为本发明另一实施例所公开的晶圆级功率模组的第一被动元件和第二被动元件的结构示意图；
图10A至图10C为本发明另一实施例所公开的晶圆级功率模组的结构示意图；
图11A和图11B为本发明另一实施例所公开的晶圆级功率模组的结构示意图；
图12为本发明一实施例所公开的晶圆级功率模组的金属屏蔽层的结构示意图；
图13A至图13F为本发明一实施例所公开的晶圆级功率模组的制作方法的流程示意图；
图14A至图14F为本发明另一实施例所公开的晶圆级功率模组的制作方法的流程示意图；
图15A至图15E为本发明另一实施例所公开的晶圆级功率模组的制作方法的流程示意 图。
其中：1被动元件；1-1第一被动元件；1-2第二被动元件；2晶片；2-1第一晶片；2-2第二晶片；3第二金属层；4导电孔；5第一金属层；6连接层；7粘结层；8绕组；9第一绝缘层；10第二绝缘层；11第三金属层；12磁柱；13电容；14功率区；15控制区；16电源管理区；17金属屏蔽层；18TSV孔；19导通孔；20内部金属层；21功能导电层；22功能介质层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例公开了一种晶圆级功率模组，如图2A所示，包括晶片2和被动元件1，晶片2包括一晶片功能区，晶片功能区位于晶片2的第一表面(图中为晶片2的下表面)；被动元件1包括至少一功率引脚，被动元件1堆叠于晶片2的第二表面(图中为晶片的上表面)上，晶片功能区通过一导电通路从晶片2的第一表面电性连接至晶片2的第二表面，并与被动元件1的功率引脚电性连接，晶片功能区包括第一金属层5；导电通路依附于晶片2，导电通路通过导电孔4在晶片2的第二表面形成用于与被动元件1电性连接的引脚结构，该引脚结构为第二金属层3，晶片2与被动元件1之间设置有粘结层7。导电通路放置于模组的侧面或者中间位置，并且导电通路的一部分或者全部由通孔或者半通孔电镀实现，可以减少模组焊接点，实现极致高可靠性。
如图2A所示，本实施例中被动元件1为磁性元件，包含磁芯本体和绕组8，被动元件1的绕组8第一端和第二端均通过一连接层6连接到晶片2的第二金属层3。晶片2的平面尺寸(X、Y)与被动元件1的平面尺寸(X、Y)相同，相同也包含近似相等，可定义为两者尺寸偏差能控制在0～100μm以内。由于该功率模组是由晶圆切割形成，因此功率模组的平面尺寸即为晶片2的平面尺寸。功率模组的SW功率引脚通过导电通路与绕组8第一端借由连接 层6连接，VO功率引脚通过导电通路与绕组8第二端借由连接层6连接。由于晶片2比较薄，外力很容易造成其损伤，因此会在晶片2与被动元件1之间设置一粘结层7，能将被动元件1与晶片2牢牢绑定，由于被动元件1厚度较大，因此相对较弱的晶片2可以依靠被动元件1的支撑而不被拉弯。更进一步，可以确保该功率模组的引脚有足够好的平整度。
为了能实现晶片2与被动元件1的连接，位于晶片2背面的引脚可以是第二金属层3通过连接层6与被动元件1的引脚连接；也可以是在第二金属层3上长bump或者植球，然后再与被动元件1的绕组8连接。
该功率模组的引脚可以是通过在第一金属层5上通过阻焊层进行直接定义，也可以是生长bump或者植球。
相比现有技术，本发明实施例的结构是直接在晶片2上连接一被动元件1，该晶片2未经过埋入工序，也就省去了晶片2封装带来的高度尺寸的浪费。如现有技术的结构，所需晶片2的厚度至少150μm，如果晶片2封装只需要上、下各一层金属层和绝缘层，至少也要150μm的厚度，也就是说总的基板厚度要达到300μm。而本发明实施例省去了嵌埋封装的尺寸，使得除被动元件1之外的厚度降低了50％。
在一些实施例中，被动元件1主要和截面积有关，针对不同的应用场合，如果对厚度要求极为严苛，可以将功率模组的平面尺寸适当放开，以此来增大被动元件1的平面尺寸，降低被动元件1的厚度；如果对平面尺寸较为极为严苛，可以适当的将晶片2平面尺寸缩小，增加被动元件1的厚度，这样整个功率模组的设计就非常灵活。
在一个较佳地实施例中，晶片2的厚度小于100μm甚至可以小于50μm，由于晶片2衬底的晶片功能区往往只有不到10μm，使得晶片2的衬底厚度能做的非常薄，加上衬底表面的钝化层以及导电通路，总的厚度也能控制在50μm以内，甚至可以控制在30μm以内。对比现有技术，埋入工艺需要晶片2的厚度至少150μm，才能保证埋入过程中晶片2不会受损，而本发明实施例因为以被动元件1做支撑，固定晶片2，所以可以将晶片2做的非常薄，使得功率模组的高度会有大幅度的降低。换句话说，30μm厚度的晶片2在整个功率模组中占比微乎其微，基本可以忽略不计，最终形成的功率模组厚度基本与被动元件1本身的厚度 一致，可以实现总高度小于0.5mm甚至小于0.3mm，而面积与晶片2相当的WLCSM(Wafer Level Chip Size Module)。
本发明实施例的结构，使得晶片2厚度在整个功率模组中占比非常小，甚至可以忽略不计。尤其是对功率模组尺寸要求很高的场合，比如数据中心的垂直供电，穿戴品供电等等。
在一较佳地实施例中，晶片2衬底的第一表面、第二表面以及导电孔4的内壁分别形成一第一绝缘层9。如图2B所示，由于衬底为半导体，介于导体和绝缘体之间，因此在导电孔4的内壁和晶片2衬底的第一表面和第二表面均形成第一绝缘层9以实现导电孔4与衬底以及第二金属层3与衬底的电气绝缘。导电孔4可为激光或蚀刻后形成通孔或者半通孔，并通孔或半通孔电镀，从而将晶片功能区和功能导电层进行电性连接；或者也可以通过布线实现晶片功能区和功能导电层之间的电性连接。
在一较佳地实施例中，导电孔4内还具有一金属扩散阻挡层，金属扩散阻挡层位于第一绝缘层9内侧，金属扩散阻挡层位于第一绝缘层9和导电孔4之间，其目的是更进一步防止铜原子在高温下(如400℃)往衬底扩散，避免导电孔4与衬底之间形成通路。Ti、Ta、TaN及TiN可以用来制作金属扩散阻挡层，第一绝缘层9的材质包含二氧化硅(SiO2)或氮化硅(Si3N4)等。
在其他的一些实施例中，晶片功能区的表面形成有第二绝缘层10，第二绝缘层10用于阻挡SW功率引脚，如图2C所示，由于SW功率引脚为中间点，且跳变，一般不会引出来，因此会在第一金属层5的表面设置一第二绝缘层10以实现功率模组与系统板之间的绝缘。这样一来，该系统板进行布线的时候就会更加自由，无需避让该中间点。
在其他的一些实施例中，晶片2第二表面上省去了第二金属层3，这样导电孔4就可以直接通过连接层6与被动元件1连接，得到图2D所示的结构。相比图2B，第一绝缘层9并不存在于晶片2的第二表面上，该结构的实现可以是基于图2B的结构，对晶片2的第二表面进行机械研磨，将第二金属层3和位于晶片2第二表面的第一绝缘层9去除，甚至可以将衬底层继续研磨，做的更薄。那被动元件1与衬底之间的绝缘就可以通过粘结层7来实现。因此 这里的粘结层7不仅起到电气绝缘的作用还起到固定支撑晶片2的作用。晶片2的第二表面不一定仅代表衬底加工的初始面，后续可能通过机械研磨将晶片2衬底减薄，减薄后的表面亦可称作第二表面。
在其他的一些实施例中，导通电路结构还可以如图3A所示，导电孔4位于第一晶片2-1的四周，而被动元件1绕组8的第一端和第二端靠近中间区域，这时第一晶片2-1和被动元件1的连接就需要通过第二金属层3进行过渡。结合前述几个实施例，可以明显看出，通过第二金属层3可以让第一晶片2-1的导电孔4以及被动元件1的绕组8引脚分布更加自由，不受彼此约束。对于直接在第一晶片2-1上铺设电容13或者电感，仍可以通过第二金属层3进行过渡走线。
在一较佳地实施例中，由于导电孔4的直径会比较小，因为绕组8的一端需要连接多个导电孔4，以此实现更小的导通电阻，如图3B所示。
在其他的一些实施例中，导电孔4位于晶圆的切割道位置，如图4A所示，导电孔4是设置于晶片2的侧壁，然后延伸至晶片2上的第一金属层5和第二金属层3形成外接的两个端面。这种结构不再占用衬底内部空间，可以让晶片2的利用率更高，尤其是针对引脚密度很高的应用场合。芯片挖孔由于有精度和污染问题，会损伤芯片功能区，比如快速且低成本的激光开孔，光会衍射损伤功能区。所以，往往需要避让较大距离。而如果希望精度高污染小，则需要很昂贵的干蚀方法。如图4B所示，导电孔4是在整张晶圆的切割道上形成，通过划片后该导电孔4的各一半分配给相邻的两个单元，如图4B中的中间晶片单元两侧的金属即为图4A左右两侧的侧边金属。因此相比之下，本实施例会进一步缩小导电孔4的占地面积。因为切割道晶圆本身就有，且功能区只需在过孔的一侧避让。
图4B所示导电孔4为方形，当然也可以为圆形阵列，椭圆形等，这里不做限制。
对于图4B，晶片单元可以是多个开关管并联或者串联，那对应的切割方式可能是两个晶片单元为一整体被切割下来，亦或者四个晶片单元为一整体，亦或者是6个晶片单元为一整体等等。
要实现每个晶片单元的互联，可以在每个晶片单元的第一金属层5外围继续生长第三金 属层11，该第三金属层11是互联多个单元以实现完整的多相电路，如图4C所示。
在其他的一些实施例中，晶片2包括第一晶片2-1和第二晶片2-2，如图5所示，在第一晶片2-1与被动元件1之间设置第二晶片2-2，如第一晶片2-1定义为含驱动的开关器件，第二晶片2-2定义为控制器件。这样本发明的功率模组除了主功率开关(含驱动)和被动元件1外，还可以集成控制功能。如此一来，控制器件与开关器件之间的连接就可以在功率模组内部解决，整个功率模块的引脚就会很少，客户使用也会更加灵活、方便。为了增强第一晶片2-1、第二晶片2-2以及被动元件1之间的可靠性，可以在它们之间分别设置粘结层7。绕组8的第一端会通过连接层6与第二晶片2-2的导电通路连接，然后再通过连接层6与第一晶片2-1的导电通路连接，最后在功率模组底部形成交流电压(以SW为例)和直流电压(以VO为例)功率引脚。
在其他的一些实施例中，被动元件1为多路集成电感，该电感结构为一四路耦合电感或者耦合变压器，多路集成电感包括至少两个磁性单元，至少两个磁性单元的绕组8共用同一磁柱12，以使绕组8的长度相等。多路集成电感的绕组8的输入引脚和输出引脚交错排布，以图6A为例，沿着A-A’方向的截面结构如图6C所示，所形成的出脚可为交流直流SW1-VO1-SW3-VO3交错的排列形式，那对应功率模组的引脚排布也是交错排布。
在一较佳地实施例中，多路集成电感的每一路的绕组8为单匝或多匝，多路集成电感的每一路的绕组8为多股并绕结构，如图6D所示，为了能实现更好的耦合效果以及更好的动态特性，可以将两个磁柱12对应的绕组8共用一个磁柱12。从图6E可以看出，SW与VO是非交错排列的，主要是为了让两个绕组8的长度近似相等，这样均流效果会更好。
需要注意的是每一路的绕组8可以是单匝也可以是多匝，也可以是多股并绕；该多路电感亦可以是多路非耦合电感及多绕组变压器，这里不再赘述。
在其他的一些实施例中，功率模组的功率引脚分布在功率模组的上表面和下表面中的至少一个表面，功率引脚包括交流电压引脚和直流电压引脚，交流电压引脚位于功率模组的中间区域，直流电压引脚位于功率模组的四周，如图7A所示，交流电压的引脚位于功率模组的中间位置，直流电压的引脚位于功率模组边缘。相比前述实施例，本实施例的好处 就是直流电压的引脚位于边缘方便客户走线，由于交流电压引脚放置在中间区域，自然就不会阻碍直流部分往外引线，客户使用会非常灵活。
导电孔4可以是先通过激光钻孔再电镀的方式形成，激光钻孔的成本相对于干法蚀刻会低很多，但是这种方式的能量相对较大，对功能区的损伤比较明显。采用本实施例的结构，交流电压引脚设置在功率模组中间位置，相比于分散设置，这种集中设置的方式会大大减少其占地面积，如图7B所示。换句话说，如果是分散设置，按每个导电孔4都需要一个安全区域的占地面积，多个孔叠加起来，安全区域占地面积就会非常大，而集中设置，可以让所有的孔只需要一个安全区域。
需要注意的是，晶片2上方堆叠的器件可以是被动元件1，如电感，也可以变压器，也可以是电容13等等。
在其他的一些实施例中，被动元件1包括第一被动元件1-1和第二被动元件1-2，第一被动元件1-1和第二被动元件1-2分别垂直堆叠在晶片2的第二表面上。如图8所示，可以将晶片2上方放置电感和电容13，形成完整的闭合回路。对于buck电路来说，电容13为输入电容；对于boost来说，电容13为输出电容。在晶片2上放置多元件时，各元件之间缝隙应该有填充材料，比如使用一样的粘结材料，避免在晶片2上产生应力。
在其他的一些实施例中，晶片2、第二被动元件1-2和第一被动元件1-1在垂直方向上依次堆叠设置，第二被动元件1-2的平面尺寸与晶片2的平面尺寸相同，晶片2与第二被动元件1-2之间、第二被动元件1-2与第一被动元件1-1之间，分别通过焊接形成互联。如图9所示，可以在晶片2上先铺设电容13，再铺设电感。此时，电容13层位于电感和晶片2之间，形成完整的闭合回路。相比于图8，将电容13平铺的面积与晶片2面积相当，可以将电容13容值做的很大，充分满足功率模组去耦需求。将两个容电极做的尽量近，可以让输入回路做的很小，降低loop电感。为了回路电感小，电容13靠近晶片2，磁性元件在电容13之上，因此，电容13不仅有电容电极，还有协助磁性元件与晶片2互联的过渡电极。本发明所揭示的实施例中，电容13可以为硅片电容阵列，硅片电容阵列包括输出电容和/或晶片在工作时所需的部分电容。
如图10A、图10B所示，前述的实施例中各被动元件1可以通过先预成型，再堆叠在晶片2之上。但堆叠精度，会导致孔径较大，或者需要背面铺铜扩大焊盘。导致工艺复杂和空间浪费。本发明实施例是可以在晶片2背面，以晶片2为载体，生长所需磁性元件或者电容元件(统称无源器件)，形成一个功能导电层21；邻近功能导电层21，包括至少一个功能介质层22，该功能介质层可以设置磁性元件的磁材料或者电容的介质材料。或者将半成型(有功能区，但尚无完整引出电极)的无源器件通过电镀与晶片2连接。这样就可以使用晶圆半导体工艺精度进行互联，即通过钻孔、电镀工艺进行晶片2和无源器件的电性互联。精度和空间利用率和可靠性乃至生产效率都大为提升。在图10C所示的实施例中，可以采用相同的工艺制作方法，将电容13设置于晶片2的底面，电容13的引脚与功率模组的功率引脚集成在一起，且都设置于功率模组的下表面。
对比前述几个实施例，可以明显看出，电容13与晶片2的连接或者电感与电容13的连接，不仅可以通过焊接，此时连接层6材质与导电孔4材质不同；也可以是基于晶片2本体自下而上生长连接层6，此时连接层6与导电孔4材质相同。
如图11A所示，使用晶圆工艺制作完整功能功率模组，但并不局限于电源功率模组。比如射频功放，在背面设置滤波器乃至天线，即功率模组由晶圆工艺切割而成，功率模组的平面尺寸就是晶片2的平面尺寸；功率模组中，空间尽可能的提供给无源器件，即晶片2的厚度尽可能的薄，100μm甚至50μm以下。
要达到这个目的，除了本发明的晶圆级功率模组的制作方法之外，还需要晶片2的面积与无源器件相当。有两种方法：其一，本发明晶片2的功率区14工作频率在20MHz乃至100MHz以上，即减小无源器件的面积，使其与晶片2面积相当；其二，尽可能在晶片2中集成更多的非功率功能，比如控制区15和电源管理区16，电源管理区16为电源功率模组的智能管理功能，即Power Management，或者其他数字管理和数据处理功能，使得晶片2面积与无源器件的面积相当。在其他的一些实施例中，晶片2可以包括两个功率区14，该两个功率区14通过再布线层进行互联，再布线层包括至少一个TSV孔，该TSV孔位于晶片的侧壁。
在一较佳地实施例中，如图11B所示，晶片功能区电性连接到功率模组的顶面，实现 双面pinout或者双面布线，使得引脚分布较为灵活。同时，散热效果也得到提升。也可以设置更多功能，比如顶部布线设置成射频发射和接收的天线。
在其他的一些实施例中，如图12所示，在被动元件1与晶片2之间设置结构支撑件，尤其是对于晶片2很薄，通过这种方式能加固其机械强度。该支撑件中金属屏蔽层17可以起到屏蔽作用，隔离电感和芯片，避免晶片2被电磁干扰。
图13A至图13F示出了本发明一实施例中的晶圆级功率模组的制作方法，步骤如下：
S1：提供一整张晶圆；
S2：在晶圆的衬底上形成TSV孔18，在该步骤中TSV孔18不贯穿晶圆衬底，如图13A所示；
S3：在TSV孔18的内壁形成第一绝缘层9，如图13B所示；
S4：在TSV孔18内部填充金属，并在晶圆衬底的第一表面形成第一金属层5，如图13C所示；
S5：减薄晶圆的第二表面，使TSV孔18内部的金属外露，将空间留给被动元件1，如图13D所示；
S6：在晶圆的第二表面设置被动元件1，如图13E所示；
S7：划片，形成独立的功率模组，功率模组的平面尺寸与晶片2的平面尺寸相同，如图13F所示，以形成如图2D所示的功率模组结构。
需要注意的是，步骤S2中，TSV孔18的形成方式通常为干法蚀刻，也可以采用激光钻孔的方式实现；
在一较佳地实施例中，步骤S6具体为：
若被动元件1是分立的，则还需要将被动元件1塑封形成塑封体，以支撑晶圆，且步骤S7需要从晶圆的第一表面进行划片切割；
若被动元件1是预成型的拼板，则需要将被动元件1与晶圆填缝固定。
在一较佳地实施例中，步骤S6具体为：晶圆的第二表面生长形成被动元件1。
可选的，如图2A所示的功率模组结构由以下的制作方法形成：
S1：提供一整张晶圆；
S2：在晶圆的第一表面上形成第一金属层5，晶圆的第一表面为功能面；
S3：将晶圆的第一表面固定在载具上后，对晶圆进行减薄，将空间留给被动元件1；
S4：从晶圆的第二表面向内形成TSV孔18，TSV孔18延伸至第一金属层5；
S5：在TSV孔18的内壁及晶圆的第二表面上形成第一绝缘层9；
S6：在TSV孔18内部填充金属，并在晶圆的第二表面上形成第二金属层3；
S7：在晶圆的第二表面设置被动元件1；
S8：划片，形成独立的功率模组，功率模组的平面尺寸与晶片的平面尺寸相同。
在上述制作方法的基础上，TSV孔18的位置可以位于晶片单元之间的切割道上时，可制作形成如图4A所示的功率模组结构。
图14A至图14F示出了本发明另一实施例中的晶圆级功率模组的制作方法，步骤如下：
S1：提供一整张晶圆；
S2：在晶圆的第二表面铺设被动元件1，如图14A所示；
S3：形成导通孔19，导通孔19贯穿晶圆和被动元件1，如图14B所示；
S4：在导通孔19内形成第一绝缘层9，如图14C所示；
S5：在被动元件1的表面控深钻孔，在导通孔19的一端形成一宽度更宽的导通孔19，如图14D所示，在该步骤中，更宽的导通孔19处的第一绝缘层9被去除；
S6：在晶圆的第一表面、被动元件1的表面和导通孔19内形成金属层，如图14E所示；
S7：蚀刻，在晶圆的第一表面和被动元件1的表面分别形成所需的引脚，如图14F所示；
S8：从导通孔19位置进行划片，形成独立的功率模组，功率模组的平面尺寸与晶片2的平面尺寸相同，以形成如图11B所示的功率模组结构。
需要注意的是，步骤S2中，被动元件1可以电感，电容13，变压器等，被动元件1的铺设可以用LTCC即低温烧结陶瓷、CVD气相沉淀等工艺。
图15A至图15E示出了本发明另一实施例中的晶圆级功率模组的制作方法，步骤如下：
S1：提供一整张晶圆；
S2：在晶圆的第二表面铺设被动元件1，被动元件1内部具有内部金属层20；
S3：从晶圆的第一表面向内形成导通孔19，使得内部金属层20外露，如图15A所示；
S4：在导通孔19内形成第一绝缘层9，如图15B所示；
S5：去除位于内部金属层20外的部分第一绝缘层9，使得部分内部金属层20外露，如图15C所示；
S6：在导通孔19内填充金属，在晶圆的第一表面形成金属层，如图15D所示；
S7：蚀刻，在晶圆的第一表面形成所需的引脚，如图15E所示；
S8：从导通孔19位置进行划片，形成独立的功率模组，功率模组的平面尺寸与晶片2的平面尺寸相同，以形成如图11A所示的功率模组结构。
需要注意的是，步骤S7中，可以通过激光刻蚀的方式，也可以通过化学方式进行蚀刻。
如流程S6和S7，也可以合并成一种工艺方式，即采用全加成的金属化方式，基于S5之后在晶圆的第一表面上直接电镀形成具有图形的金属布线层，所述图形代表不同的引脚。
本发明所揭示的“相等”或“相同”或“等于”，都须考虑工程的参数分布，误差分布在±30％以内。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其它实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (61)

  1. 一种晶圆级功率模组，其特征在于，包括：
    晶片，所述晶片包括一晶片功能区，所述晶片功能区位于晶片的第一表面；
    被动元件，所述被动元件包括至少一功率引脚，所述被动元件堆叠于晶片的第二表面上，所述晶片功能区通过一导电通路从晶片的第一表面电性连接至晶片的第二表面，并与被动元件的功率引脚电性连接；
    所述导电通路依附于晶片。
  2. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述导电通路包括至少一导电孔，所述导电孔贯穿晶片衬底。
  3. 根据权利要求2所述的晶圆级功率模组，其特征在于，所述导电通路通过导电孔在晶片的第二表面形成用于与被动元件电性连接的引脚结构。
  4. 根据权利要求2所述的晶圆级功率模组，其特征在于，所述导电孔位于晶片的晶片功能区的区域内。
  5. 根据权利要求2所述的晶圆级功率模组，其特征在于，所述导电孔位于晶片的晶片功能区的区域外。
  6. 根据权利要求5所述的晶圆级功率模组，其特征在于，所述导电孔位于晶圆的切割道位置。
  7. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述导电通路包括至少一导电孔，所述导电孔从功率模组的下表面延伸至上表面。
  8. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述导电通路包括至少一导电孔，所述导电孔位于功率模组的侧壁。
  9. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述导电通路包含至少一连接层，所述连接层用于将晶片的晶片功能区与被动元件的功率引脚通过焊接或电镀的方式电性连接。
  10. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述晶片衬底的第一表面、第二表面以及导电孔的内壁分别形成一第一绝缘层。
  11. 根据权利要求10所述的晶圆级功率模组，其特征在于，所述导电孔内还具有一金属扩散阻挡层，所述金属扩散阻挡层位于第一绝缘层内侧。
  12. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述晶片功能区的表面形成有第二绝缘层，所述第二绝缘层用于阻挡SW功率引脚。
  13. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述功率模组的平面尺寸与晶片的平面尺寸相同。
  14. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述被动元件的平面尺寸与晶片的平面尺寸相同。
  15. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述被动元件预先成型，所述被动元件包括被动元件功能区和完整的功率引脚，所述被动元件通过焊接与晶片电性连接。
  16. 根据权利要求15所述的晶圆级功率模组，其特征在于，在晶圆切割前，预先成型的所述被动元件焊接在晶圆上，所述被动元件在晶片的第二表面上方塑封形成支撑。
  17. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述被动元件预先半成型，所述被动元件包括被动元件功能区，但不具有完整的功率引脚，所述被动元件通过电镀与晶片电性连接。
  18. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述被动元件在晶圆上生长成型，并通过烧结或电镀与晶片电性连接。
  19. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述被动元件包括第一被动元件和第二被动元件，所述晶片、第二被动元件和第一被动元件在垂直方向上依次堆叠设置。
  20. 根据权利要求19所述的晶圆级功率模组，其特征在于，所述第二被动元件的平面尺寸与晶片的平面尺寸相同。
  21. 根据权利要求19所述的晶圆级功率模组，其特征在于，所述晶片与第二被动元件之间、第二被动元件与第一被动元件之间，分别通过焊接形成互联。
  22. 根据权利要求19所述的晶圆级功率模组，其特征在于，所述晶片与第二被动元件之间，和/或，第二被动元件与第一被动元件之间，通过烧结或电镀形成互联。
  23. 根据权利要求1所述的晶圆级功率模组，其特征在于，所述晶片包括第一晶片和第二晶片，所述第一晶片、第二晶片和被动元件在垂直方向上依次堆叠设置。
  24. 根据权利要求23所述的晶圆级功率模组，其特征在于，所述第二晶片包括至少一导电通路，所述导电通路贯穿第二晶片的衬底，所述导电通路位于第二晶片的内部或侧壁。
  25. 根据权利要求23所述的晶圆级功率模组，其特征在于，所述第一晶片用于实现功率开关功能，所述第二晶片用于实现控制功能，所述第一晶片的平面尺寸与第二晶片的平面尺寸相同。
  26. 根据权利要求19至22所述的晶圆级功率模组，其特征在于，所述第一被动元件和第二被动元件分别包括电感、电容、变压器、射频天线和滤波器。
  27. 一种晶圆级功率模组，其特征在于，包括：
    晶片，所述晶片包括一晶片功能区，所述晶片功能区位于晶片的第一表面；
    被动元件，所述被动元件包括至少一功能导电层和功能介质层；
    所述被动元件与晶片堆叠，堆叠后的占地面积与晶片面积相等；
    所述晶片功能区与所述功能导电层通过一个导电通路电性连接；所述导电通路的至少一部分由通孔或者半通孔电镀实现；所述导电通路置于模组侧面或者中间位置；
    所述晶片与被动元件通过填充材料贴合或者直接贴合，且被动元件为晶片提供机械强度支撑；
    所述功能介质层设置于所述被动元件的至少一功能导电层与所述晶片的第一表面之间。
  28. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述被动元件包括第一被动元件和第二被动元件，所述第一被动元件和第二被动元件分别垂直堆叠在晶片的第二表面上。
  29. 根据权利要求28所述的晶圆级功率模组，其特征在于，所述第一被动元件和第二被动元件分别包括电感、电容、变压器、射频天线和滤波器。
  30. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述被动元件为多路反耦合电感。
  31. 根据权利要求30所述的晶圆级功率模组，其特征在于，所述多路反耦合电感包括至少两个磁性单元，至少两个所述磁性单元的绕组共用同一磁柱，以使绕组的长度相等。
  32. 根据权利要求30所述的晶圆级功率模组，其特征在于，所述多路反耦合电感的绕组的输入引脚和输出引脚交错排布。
  33. 根据权利要求30所述的晶圆级功率模组，其特征在于，所述多路反耦合电感的每一路的绕组为单匝或多匝，且每一路的绕组为多股并绕结构。
  34. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述功率模组的引脚结构为焊盘结构或植球结构，所述功率模组的功率引脚分布在功率模组的上表面和下表面中的至少一个表面。
  35. 根据权利要求34所述的晶圆级功率模组，其特征在于，所述功率引脚包括交流电压引脚和直流电压引脚，所述交流电压引脚位于功率模组的中间区域，所述直流电压引脚位于功率模组的四周。
  36. 根据权利要求34所述的晶圆级功率模组，其特征在于，所述功率引脚包括电容功率引脚，所述电容功率引脚位于功率模组的中间区域。
  37. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述晶片包括至少一功率区。
  38. 根据权利要求37所述的晶圆级功率模组，其特征在于，所述晶片还包括至少一控制区和/或电源管理区和/或数据处理区，所述晶片的平面尺寸与被动元件的平面尺寸相同。
  39. 根据权利要求37所述的晶圆级功率模组，其特征在于，所述晶片的功率区的开关频率大于20MHz。
  40. 根据权利要求39所述的晶圆级功率模组，其特征在于，所述晶片的功率区的开关频率大于50MHz，所述被动元件的平面尺寸与晶片的平面尺寸相同。
  41. 根据权利要求37所述的晶圆级功率模组，其特征在于，所述晶片包括两个功率区，两个所述功率区通过再布线层进行互联。
  42. 根据权利要求37所述的晶圆级功率模组，其特征在于，所述再布线层包括至少一TSV孔，所述TSV孔位于所述晶片的侧壁。
  43. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述晶片与被动元件之间设置有粘结层或金属屏蔽层。
  44. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述晶片的厚度小于100μm。
  45. 根据权利要求44所述的晶圆级功率模组，其特征在于，所述晶片的厚度小于50μm。
  46. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述晶圆级功率模组包括功率引脚，所述功率引脚设置在所述晶片的第一表面，所述晶片的第二表面在晶片第一表面和所述被动元件之间。
  47. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述晶圆级功率模组包括功率引脚，所述功率引脚放置于所述被动元件的外侧表面，所述晶片的第一表面在晶片第二表面和所述被动元件之间。
  48. 根据权利要求27所述的晶圆级功率模组，其特征在于，所述被动元件包括与所述晶片的直流功率引脚电性互连的电容，和/或，所述被动元件包括与所述晶片的交流功率引脚电性互连的电容或磁性元件，和或，所述被动元件包括与磁性元件的直流引脚电性互连的电容。
  49. 根据权利要求27所述的晶圆级功率模组，其特征在于，还包括输出电容，所述输出电容集成所述晶圆级功率模组的引脚，并且设置于所述晶圆级功率模组的下表面。
  50. 根据权利要求49所述的晶圆级功率模组，其特征在于，所述晶圆级功率模组还包括硅片电容阵列，所述硅片电容阵列包括所述输出电容和所述晶片在工作时所需的部分 电容。
  51. 一种晶圆级功率模组的制造方法，其特征在于，所述制造方法用于制造如权利要求46所述的晶圆级功率模组，所述制造方法包括如下步骤：
    S1.将多个所述晶片依附于治具减薄后，与多个所述被动元件层紧密结合，形成一体叠构；
    S2.通过激光或者蚀刻等工艺开通孔或者半通孔，并对通孔或半通孔电镀，将所述晶片功能区和所述功能导电层进行电性连接；
    S4.通过晶片切割工艺，将多个模组分离、测试、包装。
  52. 根据权利要求51所述的制造方法，其特征在于，在步骤S2和S4之间还包括步骤S3：
    S3.将晶圆的第二表面处进行减薄。
  53. 根据权利要求51或52所述的晶圆级功率模组的制造方法，其特征在于，所述被动元件的功能导电层在所述晶圆和被动元件层结合为一体叠构后电镀而成。
  54. 一种晶圆级功率模组的制作方法，其特征在于，包括如下步骤：
    S1：提供一整张晶圆；
    S2：在所述晶圆的衬底上形成TSV孔，在该步骤中所述TSV孔不贯穿晶圆衬底；
    S3：在所述TSV孔的内壁形成第一绝缘层；
    S4：在所述TSV孔内部填充金属，并在晶圆衬底的第一表面形成第一金属层；
    S5：减薄晶圆的第二表面，使TSV孔内部的金属外露，将空间留给被动元件；
    S6：在所述晶圆的第二表面设置被动元件；
    S7：划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
  55. 根据权利要求54所述的制作方法，其特征在于，所述步骤S6具体为：
    若被动元件是分立的，则还需要将被动元件塑封形成塑封体，以支撑晶圆，且步骤S7需要从晶圆的第一表面进行划片切割；
    若被动元件是预成型的拼板，则需要将被动元件与晶圆填缝固定。
  56. 根据权利要求54所述的制作方法，其特征在于，所述步骤S6具体为：在所述晶圆的第二表面生长形成被动元件。
  57. 一种晶圆级功率模组的制作方法，其特征在于，包括如下步骤：
    S1：提供一整张晶圆；
    S2：在所述晶圆的第一表面上形成第一金属层，所述晶圆的第一表面为功能面；
    S3：将所述晶圆的第一表面固定在载具上后，对晶圆进行减薄，将空间留给被动元件；
    S4：从所述晶圆的第二表面向内形成TSV孔，所述TSV孔延伸至第一金属层；
    S5：在所述TSV孔的内壁及晶圆的第二表面上形成第一绝缘层；
    S6：在所述TSV孔内部填充金属，并在晶圆的第二表面上形成第二金属层；
    S7：在所述晶圆的第二表面设置被动元件；
    S8：划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
  58. 根据权利要求57所述的制作方法，其特征在于，所述步骤S7具体为：
    若被动元件是分立的，则还需要将被动元件塑封形成塑封体，以支撑晶圆，且步骤S7需要从晶圆的第一表面进行划片切割；
    若被动元件是预成型的拼板，则需要将被动元件与晶圆填缝固定。
  59. 根据权利要求54或57所述的制作方法，其特征在于，所述TSV孔的位置位于晶圆的切割道上。
  60. 一种晶圆级功率模组的制作方法，其特征在于，包括如下步骤：
    S1：提供一整张晶圆；
    S2：在所述晶圆的第二表面铺设被动元件；
    S3：形成导通孔，所述导通孔贯穿晶圆和被动元件；
    S4：在所述导通孔内形成第一绝缘层；
    S5：在被动元件的表面控深钻孔，在导通孔的一端形成一宽度更宽的导通孔；
    S6：在晶圆的第一表面、被动元件的表面和导通孔内形成金属层；
    S7：蚀刻，在晶圆的第一表面和被动元件的表面分别形成所需的引脚；
    S8：从导通孔位置进行划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
  61. 一种晶圆级功率模组的制作方法，其特征在于，包括如下步骤：
    S1：提供一整张晶圆；
    S2：在所述晶圆的第二表面铺设被动元件，所述被动元件内部具有内部金属层；
    S3：从晶圆的第一表面向内形成导通孔，使得内部金属层外露；
    S4：在所述导通孔内形成第一绝缘层；
    S5：去除位于内部金属层外的部分第一绝缘层，使得部分内部金属层外露；
    S6：在所述导通孔内填充金属，在晶圆的第一表面形成金属层；
    S7：蚀刻，在晶圆的第一表面形成所需的引脚；
    S8：从导通孔位置进行划片，形成独立的功率模组，所述功率模组的平面尺寸与晶片的平面尺寸相同。
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