CN105845656A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN105845656A
CN105845656A CN201610045107.7A CN201610045107A CN105845656A CN 105845656 A CN105845656 A CN 105845656A CN 201610045107 A CN201610045107 A CN 201610045107A CN 105845656 A CN105845656 A CN 105845656A
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China
Prior art keywords
pattern
mentioned
semiconductor device
island portion
metal
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CN201610045107.7A
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CN105845656B (zh
Inventor
田中义浩
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Amkor Technology Japan Inc
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J Devices Corp
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Priority to CN202110100677.2A priority Critical patent/CN112768428A/zh
Publication of CN105845656A publication Critical patent/CN105845656A/zh
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Abstract

本发明涉及半导体装置，当使用焊料等第一金属固定半导体元件来制造半导体装置时，控制熔融的焊料的流动方向及扩散方式，来防止发生不良等。作为本发明的一个实施方式，提供一种半导体装置，具有：半导体元件；以及岛部，使用第一金属将半导体元件固定于表面，在表面的一部分上，利用在第一金属熔融的情况下润湿特性比表面的润湿特性大的第二金属形成有图案。

Description

半导体装置
技术领域
本发明涉及在用于载置半导体元件的载置部(岛部(island))上形成有图案的半导体装置。
背景技术
有关半导体元件的封装方法的研究、开发日益发展。尤其是，已知的是，作为用于将半导体元件载置于引线框架(lead frame)的组装的一种，有利用引线框架的引线框架封装。已知在使用这种引线框架封装的情况下，尤其是在将功率半导体元件搭载于引线框架的岛部而进行固定时，有使用焊料(solder)的方法(例如，参照专利文献1至专利文献5)。
(现有技术文献)
(专利文献)
专利文献1：日本特开平8-172154号公报
专利文献2：日本特开2006-303216号公报
专利文献3：日本特开2008-294172号公报
专利文献4：日本特开2012-104709号公报
专利文献5：日本特开2012-125786号公报
在利用焊料将半导体元件固定于岛部的情况下，将熔融的焊料载置(配置)于岛部，并在熔融的焊料上载置(配置)半导体元件。这种情况下，难以控制熔融的焊料的流动方向及扩散方式。由此，焊料有可能从岛部流出，而发生污染或发生电特性的不良。
发明内容
因此，作为本发明的目的之一，提供一种控制熔融的焊料的流动方向及扩散方式来载置半导体元件的半导体装置等。
本发明一个实施方式的半导体装置具有：半导体元件；以及岛部，具有使用第一金属来固定半导体元件的表面，在上述表面的一部分上，利用在上述第一金属熔融的情况下润湿特性比上述表面的润湿特性大的第二金属形成有第一图案。
上述第一金属可以为焊料，上述第二金属可以为银。
上述第一图案可利用上述第二金属镀敷而形成。
上述第一图案可具有使多个矩形图案或直线状图案改变方向而交叉所成的放射状。
上述第一图案可以为使上述多个矩形图案或上述直线状图案的交叉位置从上述岛部的中心偏移的图案。
在上述第一图案中，可使上述多个矩形图案或上述直线状图案改变方向而在多个位置交叉。
上述第一图案可具有不同形状的多个图案。
上述第一图案可包括L字形状的图案及正方形或矩形的图案。
上述第一图案可具有多个圆形的图案。
上述第一图案可以为将上述多个圆形的图案配置成以下方式的图案：将规定的圆形的图案的中心与和上述规定的圆形的图案相邻的两个圆形的图案的中心分别连接起来的两个线段的长度相同、而上述两个线段的延长线不以直角相交。
上述半导体装置可具有第二图案，上述第二图案包围上述第一图案，且利用上述第二金属形成。
根据本发明，当制造半导体装置时，可控制熔融的焊料的流动方向及扩散方式，防止发生不良等。
附图说明
图1的(A)部分为本发明一个实施方式的半导体装置的一个制造工序的俯视图，图1的(B)部分为本发明一个实施方式的半导体装置的一个制造工序的截面侧视图，图1的(C)部分为本发明一个实施方式的半导体装置的另一个制造工序的截面侧视图。
图2的(A)部分为本发明一个实施方式的半导体装置的岛部上的图案的一例图，图2的(B)部分为在本发明一个实施方式的半导体装置的岛部上载置熔融的焊料的一例图，图2的(C)部分为在本发明一个实施方式的半导体装置的岛部上使用焊料固定半导体元件的一例图。
图3的(A)部分为本发明一个实施方式的半导体装置的岛部上的图案的一例图，图3的(B)部分为在本发明一个实施方式的半导体装置的岛部上载置熔融的焊料的一例图，图3的(C)部分为在本发明一个实施方式的半导体装置的岛部上使用焊料固定半导体元件的一例图。
图4的(A)部分为本发明一个实施方式的半导体装置的岛部上的图案的一例图，图4的(B)部分为在本发明一个实施方式的半导体装置的岛部上载置熔融的焊料的一例图，图4的(C)部分为在本发明一个实施方式的半导体装置的岛部上使用焊料固定半导体元件的一例图。
图5的(A)部分为本发明一个实施方式的半导体装置的岛部上的图案的一例图，图5的(B)部分为在本发明一个实施方式的半导体装置的岛部上载置熔融的焊料的一例图，图5的(C)部分为在本发明一个实施方式的半导体装置的岛部上使用焊料固定半导体元件的一例图。
图6的(A)部分为本发明一个实施方式的半导体装置的岛部上的图案的一例图，图6的(B)部分为在本发明一个实施方式的半导体装置的岛部上载置熔融的焊料的一例图，图6的(C)部分为在本发明一个实施方式的半导体装置的岛部上使用焊料固定半导体元件的一例图。
图7为本发明一个实施方式的半导体装置的岛部上的图案的一例图。
(附图标记的说明)
101：封装件本体；102：引线；103：岛部；104：半导体元件；105：引线键合；
106：密封材料；201：图案；202：交叉位置；203：子图案；301：图案；
302：交叉位置；303：子图案；401：图案；402：交叉位置；403：交叉位置；
404：交叉位置；405：子图案；501：图案；502：图案；503：图案；504：图案；
505：部分；601：图案；602：部分；603：子图案；701：图案
具体实施方式
通过多个实施方式对用于实施本发明的方式进行说明。此外，本发明不局限于以下说明的实施方式，而能够以进行各种变形等的方式实施以下说明的实施方式。进行了这种变形等的实施方式也可包含于本发明的技术范围。此外，在图中，纵横的比例尺有时与本发明的实施品不同。
(实施方式1)
图1的(A)部分及图1的(B)部分分别示出的是本发明一个实施方式的半导体装置的一个制造工序的俯视图及截面侧视图。
本发明一个实施方式的半导体装置具有封装件本体101、设置于封装件本体101上的多个引线(lead)102和半导体元件104。半导体元件104固定在设置于封装件本体101的上部面的岛部103上。在以下说明中，为了将半导体元件104固定于岛部103，主要使用金属(第一金属)。所使用的金属优选为熔点低的金属。例如，所使用的金属可举出焊料。
为了将半导体元件104固定于岛部103，将熔融的金属(例如焊料)载置于岛部103的用于固定半导体元件104的位置，并在熔融的金属上载置半导体元件104。或者，将固体金属载置于岛部103，通过加热或加压来使金属熔融，并在熔融的金属上载置半导体元件104。
图1的(C)部分示出的是如图1的(B)部分所示的制造工序的后续工序中，本发明一个实施方式的半导体装置的截面侧视图。如图1的(C)部分所示，可使用引线键合(wire bonding)105将半导体元件104与引线102电连接。在将半导体元件104与引线102电连接之后，使用树脂材料等作为密封材料106进行密封。
图2的(A)部分示出的是本发明一个实施方式的半导体装置的岛部103上的图案的一例。尤其是，图2的(A)部分为将半导体元件104固定于岛部103之前的附视图。
如图2的(A)部分所示，在岛部103上形成有使多个矩形图案改变方向而交叉的形状的图案(第一图案)201。在图2的(A)部分，图案201由4个矩形以每45度改变一次方向的方式交叉而成。换句话说，在岛部103上形成有放射状的图案201。此外，矩形图案的数量不局限于4个。另外，矩形的形状、大小无需相同，也可以不同。关于图案201的表面，采用在为了将半导体元件104固定于岛部103而使用的金属熔融时，润湿特性比未形成图案201的岛部103表面的润湿特性高的材料形成。换句话说，在为了将半导体元件104固定于岛部103而使用的金属的亲和性方面，与岛部103表面相比，图案201的表面更高。
此外，在构成图案201的形状的多个矩形图案的各自的宽度相比于长度可忽略的情况下，图案201可具有使多个线段(直线状图案)改变方向而成的形状。
图案201形成于岛部103的一部分的区域。即，可构成为并非岛部103的全部被图案201覆盖的方式。另外，在图2的(A)部分中，图案201为具有凹形状的形状。
在为了将半导体元件104固定于岛部103而使用的金属为焊料的情况下，图案201可例如将银用作金属(第二金属)来形成。这种情况下，图案201可通过在岛部103上进行镀银来形成。或者，图案201还可通过在岛部103进行银的蒸镀来形成。
在为了将半导体元件104固定于岛部103而使用熔融的焊料的情况下，将熔融的焊料载置于图案201的交叉位置202(或者构成图案201的多个矩形图案或线段的交点)。由此，如图2的(B)部分所示，熔融的焊料在图案201上从交叉位置202向矩形图案或线段的端部扩散。另外，熔融的焊料的相对于图案201表面的润湿特性比相对于岛部103的表面高，因而可防止熔融的焊料向图案201之外实质地再扩散。由此，如图2的(B)部分所示，熔融的焊料在图案201上形成子图案(sub pattern)203。
另外，还可将固体状的焊料配置于图案201的交叉位置202，通过加热或加压使其熔融。
之后，将半导体元件104配置于图案201的交叉位置202，使熔融的焊料凝固，据此将半导体元件104固定于岛部103。此外，半导体元件104无需严格地配置于图案201的交叉位置202处。
如上所述，在本实施方式中，在岛部103上配置有图案201。关于图案201，采用在将半导体元件104固定于岛部103而使用的金属熔融了的情况下，润湿特性比未形成图案201的岛部103表面的润湿特性高的材料形成。
由此，若将熔融的金属配置于图案201，则熔融的金属在图案201上扩散。因此，可控制熔融的金属的流动方向及扩散方式。由此，可防止因熔融的金属从岛部103流出而发生污染或发生电特性的不良。
另外，无需为了切削岛部103的表面来限定熔融的金属的扩散范围等而在岛部103的表面设置凹部或槽。因此，可使岛部103的表面平坦。此外，也可以切削岛部103的表面，形成图2的(A)部分所示的凹形状图案等的槽，并通过镀敷或蒸镀等在槽中形成金属(第二金属)膜，例如银膜，来作为图案201。
另外，如图2的(C)部分所示，还可以通过使半导体元件104的角部位于子图案203上，而更可靠地进行半导体元件104的固定。
(实施方式2)
图3的(A)部分示出的是本发明一个实施方式的半导体装置的岛部103上的图案的一例。
如图3的(A)部分所示，在岛部103上形成有使多个矩形图案改变方向而交叉的形状的图案301。图案301的材料或形成方法与实施方式1相同。但与实施方式1不同的是，图案301的交叉位置(构成图案301的多个矩形图案的交点)302从岛部103的中心偏移。此外，若岛部103的形状为正方形、长方形(矩形)或平行四边形，则岛部103的中心为对角线的交点。若岛部103的形状不是平行四边形(例如为梯形等平行四边形以外的形状的情况下)，则岛部103的中心例如可定义为岛部103的形状的重心等。
将半导体元件104固定于岛部103的步骤也与实施方式1相同。即，将熔融的焊料载置于图案301的交叉位置302。由此，如图3的(B)部分所示，熔融的焊料在图案301上从图案301的交叉位置302向端部扩散，来形成子图案303。
之后，如图3的(C)部分所示，将半导体元件104载置于图案301的交叉位置302，并使熔融的焊料凝固，据此将半导体元件104固定于岛部103。
如上所述，在本实施方式中，还可将半导体元件104固定于岛部103的中心之外的位置。另外，可以使图案301的交叉位置302从岛部103的中心偏移，使构成图案301的一个矩形图案的向一个方向延伸的长度大于向另一个方向延伸的长度，从而使更多的焊料流向矩形图案中的上述一个方向，而无需严格地调节焊料量。
(实施方式3)
图4的(A)部分示出的是本发明一个实施方式的半导体装置的岛部103上的图案的一例。
如图4的(A)部分所示，在岛部103上形成有使多个矩形图案改变方向而交叉的形状的图案401。图案401的材料或形成方法与实施方式1相同。但与实施方式1及实施方式2不同的是，在图案401中存在多个矩形图案交叉的多个交叉位置402、403、404。另外，两个交叉位置402、404从岛部103的中心偏移。
将半导体元件104固定于岛部103的步骤也与实施方式1及实施方式2相同。即，将熔融的焊料载置于图案401的交叉位置402。由此，如图4的(B)部分所示，熔融的焊料从图案401的交叉位置402扩散，而形成子图案405。
之后，如图4的(C)部分所示，将半导体元件104载置于图案401的交叉位置402，使熔融的焊料凝固，据此将半导体元件104固定于岛部103。
在本实施方式中，半导体元件104的固定位置不局限于交叉位置402。在图案401上存在交叉位置402、403、404，因而也可在其中的交叉位置404上载置熔融的焊料，来固定另一个半导体元件。另外，还可在交叉位置403上载置熔融的焊料，而固定再一个半导体元件。另外，还可在多个交叉位置402、403、404中的两个以上处分别固定半导体元件。
根据本实施方式，图案401具有多个交叉位置402、403、404，因而可固定多个半导体元件。
(实施方式4)
在实施方式1至实施方式3中，岛部103上的图案具有使多个矩形图案改变方向而交叉的形状。但是在本发明中，岛部103上的图案形状不局限于实施方式1至实施方式3的图案的形状。例如，如图5的(A)部分所示，在岛部103的中心配置正方形或矩形的图案501。另外，在正方形或矩形的图案501的周围配置包围正方形或矩形的图案501的图案502。在正方形或矩形的图案501及包围它的图案502的周围，配置L字状的图案503、504。另外，在L字状的图案之间还可配置直线状的图案。这种情况下，可构成为在正方形或矩形的图案501及包围它的图案502、L字状的图案503、504、或在必要时除直线状图案之外的部分505中不形成图案。
在本实施方式中，为了将半导体元件104固定于岛部103，可在岛部103上的图案501、502、503、504上的任意位置载置熔融的焊料。由此，如图5的(B)部分所示，熔融的焊料向多个图案501、502、503、504分散，而形成分散的子图案。如图5的(C)部分所示，在分散的子图案上配置半导体元件104。
如上所述，在本实施方式中，可将半导体元件104固定于岛部103的图案上的任意位置。另外，这种情况下，可提高图案在岛部103上所占面积的比率，并防止焊料扩散至必要以上。
(实施方式5)
在本发明中，岛部103上的图案并不限于诸如正方形的形状、矩形的形状、L字状的形状或直线状的形状这样的直线的形状或它们的组合。可形成配置有多个圆形的图案601的图案。这种情况下，例如可将多个圆形的图案601分别配置于相互平行且等间隔的多个直线的各个上。另外，也可以如图6的(A)部分所示，使将规定的圆形的图案601a的中心与和该规定的圆形的图案601a相邻的两个圆形的图案601b、601c的中心分别连接起来的两个线段L1、L2的长度相同，而该两个线段L1、L2的延长线不以直角相交。另外，在图6的(A)部分中，附图标记602表示岛部103的未形成图案601的部分。
本实施方式中，为了将半导体元件104固定于岛部103，可在岛部103上的图案601上的任意位置载置熔融的焊料。由此，如图6的(B)部分所示，熔融的焊料即使载置于包括附图标记602的部分在内的部分上，也以被圆形的图案601吸引的方式扩散，而绘制子图案603。之后，如图6的(C)部分所示，可在子图案603上固定半导体元件104。
根据本实施方式，可在岛部103的任意位置固定半导体元件104。另外，通过配置更多的圆形的图案601，可防止焊料扩散至必要以上。
(实施方式6)
图7示出的是本发明一个实施方式的半导体装置的岛部103上的图案的一例。在图7中，图案201的周围被另一图案(第二图案)701包围。换句话说，在被图案701包围的区域内配置有实施方式1的图案201。此外，在图7中，作为图案201，示出的是实施方式1的图案，但也可使用任意的图案，例如，实施方式2至实施方式5中的任一个或组合的图案，来代替图案201。
另外，为了固定半导体元件，如在实施方式1至实施方式5中所说明的那样，在被图案701包围的区域中载置熔融的焊料。
在本实施方式中，即使焊料过度扩散，焊料也是向另一个图案701扩散，从而可防止焊料从岛部103溢出。
(其他实施方式)
以上，对使用金属(例如，焊料)将半导体元件固定于岛部的情况进行了说明。但是，本发明不局限于使用金属的情况，还可用在使用粘结剂将半导体元件固定于岛部的情况。这种情况下，在岛部上，由对粘结剂的亲和性比对岛部的表面的粘结剂的亲和性高的材料形成图案。

Claims (11)

1.一种半导体装置，具有：
半导体元件；以及
岛部，具有使用第一金属来固定上述半导体元件的表面，在上述表面的一部分上，利用在上述第一金属熔融的情况下润湿特性比上述表面的润湿特性大的第二金属形成有第一图案。
2.根据权利要求1所述的半导体装置，其中，上述第一金属为焊料，上述第二金属为银。
3.根据权利要求1或2所述的半导体装置，其中，上述第一图案是利用上述第二金属的镀敷而形成的。
4.根据权利要求1所述的半导体装置，其中，上述第一图案具有使多个矩形图案或直线状图案改变方向而交叉所成的放射状。
5.根据权利要求4所述的半导体装置，其中，上述第一图案为使上述多个矩形图案或上述直线状图案的交叉位置从上述岛部的中心偏移的图案。
6.根据权利要求4或5所述的半导体装置，其中，在上述第一图案中，使上述多个矩形图案或上述直线状图案改变方向而在多个位置交叉。
7.根据权利要求1所述的半导体装置，其中，上述第一图案具有不同形状的多个图案。
8.根据权利要求7所述的半导体装置，其中，上述第一图案包括L字形状的图案及正方形或矩形的图案。
9.根据权利要求1所述的半导体装置，其中，上述第一图案具有多个圆形的图案。
10.根据权利要求9所述的半导体装置，其特征在于，上述第一图案为将上述多个圆形的图案配置成以下方式的图案：将规定的圆形的图案的中心与和上述规定的圆形的图案相邻的两个圆形的图案的中心分别连接起来的两个线段的长度相同、而上述两个线段的延长线不以直角相交。
11.根据权利要求1所述的半导体装置，其特征在于，具有第二图案，上述第二图案包围上述第一图案，且利用上述第二金属形成。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1501490A (zh) * 2002-08-07 2004-06-02 三洋电机株式会社 电路装置及其制造方法
JP2010245161A (ja) * 2009-04-02 2010-10-28 Denso Corp 電子装置およびその製造方法
JP2012125786A (ja) * 2010-12-14 2012-07-05 Denso Corp 半導体装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3412108B2 (ja) 1994-12-19 2003-06-03 株式会社神戸製鋼所 リードフレーム
JP3278055B2 (ja) * 1998-06-30 2002-04-30 セイコーインスツルメンツ株式会社 電子回路装置
US20030038366A1 (en) * 1999-03-09 2003-02-27 Kabushiki Kaisha Toshiba Three-dimensional semiconductor device having plural active semiconductor components
JP3495300B2 (ja) * 1999-12-10 2004-02-09 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2002184925A (ja) 2000-12-12 2002-06-28 Toshiba Corp 半導体モジュール用リード端子部材とその製造方法、およびそれを用いた半導体モジュール
WO2006009029A1 (ja) * 2004-07-15 2006-01-26 Dai Nippon Printing Co., Ltd. 半導体装置及び半導体装置製造用基板並びに半導体装置製造用基板の製造方法
JP4609172B2 (ja) 2005-04-21 2011-01-12 株式会社デンソー 樹脂封止型半導体装置
JP2008294172A (ja) 2007-05-24 2008-12-04 Panasonic Corp リードフレームおよび半導体装置ならびに半導体装置の製造方法
JP5056325B2 (ja) * 2007-10-04 2012-10-24 富士電機株式会社 半導体装置の製造方法および半田ペースト塗布用のメタルマスク
KR101481577B1 (ko) * 2008-09-29 2015-01-13 삼성전자주식회사 잉크 젯 방식의 댐을 구비하는 반도체 패키지 및 그 제조방법
JP5375708B2 (ja) * 2010-03-29 2013-12-25 パナソニック株式会社 半導体装置の製造方法
JP5577221B2 (ja) 2010-11-11 2014-08-20 新電元工業株式会社 リードフレーム及び半導体装置
JP6032414B2 (ja) * 2012-11-16 2016-11-30 東芝ライテック株式会社 発光モジュール

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1501490A (zh) * 2002-08-07 2004-06-02 三洋电机株式会社 电路装置及其制造方法
JP2010245161A (ja) * 2009-04-02 2010-10-28 Denso Corp 電子装置およびその製造方法
JP2012125786A (ja) * 2010-12-14 2012-07-05 Denso Corp 半導体装置

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