CN105684147B - 半导体模块及其制造方法 - Google Patents
半导体模块及其制造方法 Download PDFInfo
- Publication number
- CN105684147B CN105684147B CN201580002346.8A CN201580002346A CN105684147B CN 105684147 B CN105684147 B CN 105684147B CN 201580002346 A CN201580002346 A CN 201580002346A CN 105684147 B CN105684147 B CN 105684147B
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- Prior art keywords
- lead frame
- shell
- bonding agent
- bonding
- semiconductor module
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000007767 bonding agent Substances 0.000 claims abstract description 46
- 239000011347 resin Substances 0.000 claims description 33
- 229920005989 resin Polymers 0.000 claims description 33
- 238000009434 installation Methods 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 238000005266 casting Methods 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims 1
- 238000000465 moulding Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 10
- 239000004734 Polyphenylene sulfide Substances 0.000 description 9
- 229920000069 polyphenylene sulfide Polymers 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 206010037660 Pyrexia Diseases 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000006096 absorbing agent Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009950 felting Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
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Abstract
本发明提供一种具有能获得稳定的引线键合的引线框的半导体模块。对于通过引线框(2)和壳体(3)的一体成型而形成的端子壳体(1),其内部具有安装有引线框(2)的内表面(6b),并在外部具有固定电路块(11)的阶差部(6a),该电路块(11)的绝缘基板(7)上形成有半导体模块(13,14)。在该阶差部(6a)和内表面(6b)之间形成有贯通这两者的开口部(8),向该开口部(8)中填充将绝缘基板(7)粘接至阶差部(6a)的粘接剂(10)。由于引线框(2)的通过超声波接合来连接键合线(16)的连接面被固定,因此能降低引线框(2)的接合不良。
Description
技术领域
本发明涉及半导体模块及其制造方法,特别涉及用于电动机驱动装置等逆变器装置、开关电源装置等功率转换装置的用途的半导体模块及其制造方法。
背景技术
功率转换用的半导体模块是将用于进行功率转换的功率晶体管或二极管等功率用的多个半导体芯片集成于一个封装。该半导体模块预先在封装内部进行适用于所希望应用的电路布线,对应用装置整体的小型化作出贡献。在功率转换用的半导体模块中,作为功率晶体管,一般使用MOSFET(Metal Oxide Semiconductor Field-Effect Transistor:金属氧化物半导体场效应晶体管)或IGBT(Insulated-Gate Bipolar Transistor:绝缘栅双极晶体管)。
对于功率转换用的元件,为了通过散热来降低因其损耗而引起的发热,将其构成为通过绝缘基板上的铜箔面及绝缘基板而露出半导体模块的外部,使用散热体来从其露出面进行散热(例如参照专利文献1)。即,在该专利文献1中,在热传导性优异的金属板表面配置绝缘层,在该绝缘层上形成主电路布线图案,在该主线路布线图案上接合有半导体芯片。由该半导体芯片产生的热量会通过主电路布线图案及绝缘层而传导至金属板,通过与该金属板相接合的散热器进行散热。
另外,功率转换用的元件通过引线框、导电性引线或基板上所形成的布线图案而形成所希望的电路,这些电路与和外部进行电连接的电连接单元即端子之间直接连接或通过引线等间接连接。
而且,在半导体模块中安装有控制IC的被称为IPM(Intelligent Power Module:智能功率模块)的模块正在被产品化并得到广泛应用。控制IC具有用于驱动功率转换用元件的驱动器功能、检测过电流等异常状态并进行保护的功能。由于控制IC的发热量较小,且为了避开功率转换用元件的噪声,将控制IC安装在远离装载有功率转换用元件的基板的位置。在专利文献1中,控制IC安装于壳体内所形成的布线图案上。
另外,IPM中也存在有以下模块,即在模块内部安装有电流检测元件、温度检测元件、吸收元件、或为了向控制IC提供稳定功率而连接的电容器等无源元器件。然后,对安装了上述元件并进行了所希望的电连接后的半导体模块进行树脂密封,从而完成IPM。
例如,专利文献1中所记载的IPM中,在预先形成有布线图案的绝缘基板上通过焊接接合而安装有IGBT及FWD(Free Wheeling Diode:续流二极管)等功率转换用的元件。保持该绝缘基板的端子壳体通过插入成型来由引线框和PPS树脂(Polyphenylene SulfideResin:聚苯硫醚树脂)一体化形成。对于端子壳体,通过射出PPS树脂并使其成型于由固定销进行固定、设置的模具,上述固定销是为了避免引线框因成型时的树脂压力而发生位置偏移或变形而设置的固定销、或是推顶销等固定销,此时得到的开口部(固定销造成的孔)以使成型过程中固定销可动的方式被树脂密封。在端子壳体中,控制IC等元件通过银糊料等粘接单元安装于引线端子。之后,利用粘接剂将绝缘基板粘接于端子壳体,利用铝引线进行电接线(超声波接合)以使得在元件-绝缘基板的布线图案-引线框之间构成所希望的电路结构,然后利用树脂浇注进行密封,从而构成半导体模块。
此处,在将键合线通过超声波接合的方式接合于引线端子的情况下,已知可能会发生接合不良的情况(例如参照专利文献2)。在该专利文献2中,在制造端子壳体时,由于树脂和金属制的引线端子之间的线性膨胀系数不同的原因,在高温树脂发生冷却时,在端子壳体内部紧密接触的引线端子可能会脱离壳体。引线端子和PPS树脂并无附着力,因此即使形成为紧密接触,两者之间仍会产生稍许间隙。若在引线端子从壳体浮起的状态下,将键合线通过超声波接合的方式接合于引线端子,则超声波的振动能量会被引线端子吸收,该现象会成为接合不良的原因。
对于该问题,在专利文献2中,在成为引线端子的端子板中的超声波接合部位的正下方的壳体中形成贯通孔,在贴合于壳体的散热器中对应于贯通孔的位置上也形成有支承构件插入口。在对键合线进行超声波接合时,利用配置于支承构件插入口及贯通孔的固定销对端子板的超声波接合部位的下表面进行支承,并且使用杆状的工具将键合线通过超声波接合的方式接合于端子板的上表面。由于端子板面对贯通孔,因而端子板的下表面曝露于空气中,散热性得以提高。
在专利文献2中,在由中央部形成有开口的绝缘性树脂构成的框状的壳体的下表面配置由热传导性较高的金属形成的板状的散热器,利用该散热器来塞住开口。使用粘接剂来进行该树脂与金属之间的接合,但是若涂布超过所需量的多余的粘接剂,则虽然能获得较高的接合强度,但是粘接剂可能会从接合面溢出。粘接剂向外侧流出有损外观,而且其向内侧流入会导致利用超声波接合得到的接合部受到污染,从而使得强度下降。
作为抑制该粘接剂溢出的方法,已知有在壳体的与散热器相对的面上形成多个槽,将其中的中央附近的槽设为粘接剂涂布槽,将外侧及内侧的槽设为粘接剂流出防止槽(例如参照专利文献3)。由此,即使粘接剂从粘接剂涂布槽中溢出,该粘接剂也会被粘接剂流出防止槽所接纳,能防止其进一步流出。
现有技术文献
专利文献
专利文献1:日本专利特开2013-258321号公报(段落[0043]、图2)
专利文献2:日本专利特开2004-134518号公报(段落[0048]-[0056]、图4-图7)
专利文献3:日本专利特开2012-15349号公报(图1)
发明内容
发明所要解决的技术问题
在现有的半导体模块中,在将键合线通过超声波接合的方式接合于引线框时,需要按压超声波接合面的相反侧的面的销状的按压夹具,而且该按压夹具较为复杂,因此存在设备费用上升的问题。此外,在超声波接合工序时必须拆卸下按压夹具,由于该拆卸需要花费时间,因此还存在制造的生产量降低的问题。
本发明是鉴于上述问题而完成的,其目的在于提供一种能在制造阶段利用超声波进行稳定的引线键合的半导体模块及其制造方法。
解决技术问题所采用的技术手段
本发明为了解决上述问题而提供了一种半导体模块。该半导体模块包括:引线框,该引线框具有通过超声波接合的方式接合键合线的连接面;以及壳体,该壳体在内部具有安装引线框的安装面,在外部具有固定电路块的固定面,还具有以贯通安装面和固定面之间的方式形成的开口部,其中,所述电路块的绝缘基板上形成有半导体芯片。向开口部填充粘接剂,由此对引线框的连接面的附近部位与电路块进行粘接。
本发明提供了一种半导体模块的制造方法。该半导体模块的制造方法中,首先对壳体进行成型。将该壳体形成为:在内部具有安装引线框的安装面,以及在对应于安装面的外部具有固定电路块的固定面,其中,该引线框具有通过超声波接合的方式接合键合线的连接面,该电路块的绝缘基板上形成有半导体芯片。此时,利用推顶销或按压销,从引线框的背面对引线框的连接面的附近部位进行支承,并向模具注入树脂,从而成型得到壳体。接着,对利用推顶销或按压销形成有开口部的壳体的固定面涂布粘接剂并使粘接剂填充至开口部,将电路块载放于壳体的固定面,从而将电路块固定于壳体。然后,通过对键合线进行超声波接合来将其连接至通过粘接剂而固定于电路块的引线框的连接面。
根据上述半导体模块及其制造方法,通过超声波接合而接合有键合线的引线框的连接面的附近部位利用粘接剂并通过开口部而固定于电路块。由此,在对键合线进行超声波接合来使其连接至引线框时,引线框不会晃动从而不会发生接合不良。
发明效果
上述结构的半导体模块及其制造方法中,无需对现有工序进行变更或对现有工序追加任何工序,就能固定引线框的连接面的附近部位,因此具有能提高生产性(引线键合性)的优点。
另外,由于引线框通过高热传导率的粘接剂粘接至绝缘基板,因此绝缘基板和引线框之间的热阻降低,能进一步提高引线框的散热性。
而且,在载放于引线框的控制IC具有温度保护功能、温度输出功能的情况下,以较低的热阻连接有半导体芯片的绝缘基板与载放有控制IC的引线框之间的热阻也会降低。因此,半导体芯片和控制IC之间也会得到较低的热阻,从而控制IC能更正确地检测出温度,能更高精度地保护半导体芯片。
本发明的上述及其他目的、特征及优点能通过结合表示作为本发明的示例的优选实施方式的附图进行的以下说明而明确。
附图说明
图1是从本发明的半导体模块的底面侧对其进行观察的分解立体图。
图2是表示将绝缘基板安装前的半导体模块上下反转后的状态的剖视图。
图3是表示绝缘基板安装时的半导体模块的剖视图。
图4是表示利用键合线进行布线时的半导体模块的剖视图。
图5是表示树脂密封后的半导体模块的剖视图。
图6是表示半导体模块的制造方法的流程图。
图7是表示半导体模块的具体例的图。
具体实施方式
接下来,参照附图详细说明本发明的半导体模块的实施方式。此外,在以下实施方式的说明中所使用的附图中,对于相同结构要素附加相同标号并省略重复说明。
图1是从本发明的半导体模块的底面侧对其进行观察的分解立体图,图2是表示将绝缘基板安装前的半导体模块上下反转后的状态的剖视图,图3是表示绝缘基板安装时的半导体模块的剖视图。图4是表示利用键合线进行布线时的半导体模块的剖视图,图5是表示树脂密封后的半导体模块的剖视图。
如图1所示出的本发明的半导体模块的组装前的概要可知,该半导体模块具有端子壳体1。该端子壳体1通过对引线框2和壳体3进行一体成型(引线框插入成型)而形成。端子壳体1包括:插入有引线框2的相对的一对平行的侧壁部4a;以及与该侧壁部4a的长边方向两端相连接的相对的一对平行的侧壁部4b,在俯视时该端子壳体1形成为长方形的边框状。端子壳体1的侧壁部4a、4b具有L字形状的截面,在其底面(图1中为上表面)沿着中央开口部5的周围形成有阶差部6a。侧壁部4a、4b的阶差部6a是固定绝缘基板7的固定面,该阶差部6a的深度具有比绝缘基板7的厚度要薄的尺寸。
端子壳体1如图2所示那样形成为,引线框2的内侧安装于位于阶差部6a的相反侧的安装面即内表面6b,且引线框2的外侧为贯通侧壁部4a而向外方延伸的状态。引线框2中的安装到壳体3的内表面6b的安装面的相反侧成为利用超声波进行接合的连接面。
此处,在安装有引线框2的端子壳体1的内表面6b形成贯通至阶差部6a的开口部8。即,形成有阶差部6a的壳体部分构成为引线框2和绝缘基板7的粘接面位于开口部8的上下。该开口部8形成于引线框2的连接面的正下方的壳体部分,即形成于通过超声波接合来进行引线键合的部位附近的壳体部分。此外,通过超声波接合来进行引线键合的部位也是引线框2的主电流流过的部位。而且,开口部8也可以根据需要,出于将引线框2固定于绝缘基板7的目的,而形成在配置有引线框2的部位且不进行超声波接合的部位。
开口部8在引线框插入成型时形成。即,在将预先成型的引线框2设置于模具时,设置推顶销以对引线框2进行支承。在该状态下,向模具例如射出PPS树脂来对端子壳体1进行成型。此时,由于填充至模具内的树脂在推顶销并非可动的情况下被固化,因此树脂不会向推顶销回流。之后,利用推顶销使端子壳体1从模具突出,并进一步从端子壳体1拔出推顶销从而形成开口部8。
开口部8还可以由为了抑制插入成型时引线框2的弯曲、位置偏移而使用的所谓的按压销来形成,也可以同时使用推顶销和按压销这两者来形成。
接着,说明使用如上述那样形成的端子壳体1来构成半导体模块的顺序。首先,端子壳体1中,根据用途、目的的不同,在兼作为电路的引线框2上载放有控制IC、电容器、电阻等无源元件。在图2的例子中,示出了在引线框2上载放有控制IC9的例子。
在引线框2上载放有控制IC9的端子壳体1如图2所示,将上下反转,之后,如图3所示,对固定有绝缘基板7的阶差部6a涂布粘接剂10。该粘接剂10所使用的树脂的热传导率(例如,0.5[W/mK])高于形成壳体3的PPS树脂的热传导率(例如,0.3[W/mK])。该粘接剂10不仅涂布于阶差部6a的表面,也填充至开口部8。由此,引线框2的与开口部8相对的部分通过粘接剂10进行粘接。
接着,端子壳体1如图3所示那样,将绝缘基板7载放于涂布有粘接剂10的阶差部6a。该绝缘基板7可以使用AL(铝)绝缘基板或DCB(Direct Copper Bonding:直接铜接合)基板,在预先形成于表面的导电性布线图案12上安装功率用半导体芯片13、14来构成电路块11。这些半导体芯片13、14此处可以是IGBT及FWD。
该电路块11中,将半导体芯片13、14的安装面向下来载放于阶差部6a,由此绝缘基板7的外周部不仅通过粘接剂10而粘接至端子壳体1,还通过开口部8的粘接剂10而粘接至引线框2。由此,引线框2不仅通过填充在其正下方的开口部8中的粘接剂10与绝缘基板7进行固接,还通过粘接剂10与绝缘基板7进行热结合。
引线框2通过开口部8固定于绝缘基板7从而进行引线键合的部位附近也被固定,因此在进行超声波接合时无需复杂的按压夹具,且不会发生接合不良。
另外,引线框2通过开口部8与绝缘基板7进行热结合,因此因主电流流过而产生的发热会传导至绝缘基板7,从而引线端子能够进行散热。由此,与利用支承构件插入口及贯通孔作为开口部来使引线框曝露于热传导率为0.0241[W/mK]的空气中的现有例相比,能进一步提高引线框2的散热性。
此时,在载放于引线框2的控制IC9具有温度保护功能或温度输出功能的情况下,控制IC9能高精度地进行半导体芯片13、14的保护。即,与引线框2曝露于空气的现有例相比,以较低的热阻连接有半导体芯片13、14的绝缘基板7、与载放有控制IC9的引线框2之间的热阻会进一步降低。因此,半导体芯片13、14和控制IC9之间也会得到较低的热阻,从而控制IC9能更正确地检测出温度,能更高精度地保护半导体芯片13、14。
接着,固定有电路块11的端子壳体1如图4所示那样进行180度旋转,使端子壳体1的内表面6b及电路块11的半导体芯片13、14的安装面朝向上方。此时,沿箭头15所示的方向来按压端子壳体1的上端面,从而完成引线键合的准备。由此,与在进行超声波接合时,必须要在每一个进行引线键合的部位对从壳体浮起的引线框进行按压的现有例相比,具有压倒性的优势,能大幅简化按压夹具的结构。
在该状态下,半导体模块如图5所示,实施主电路的键合线16及控制电路的键合线17的引线键合。此时,由于端子壳体1的内表面6b与引线框2的界面紧密接触,因此在对键合线16进行超声波接合使其接合至引线框2时,超声波的振动能量不会被吸收而会有效地被传递。另外,还能进行将键合线16接合至半导体芯片13、14的引线键合以及将键合线17接合至半导体芯片13、控制IC9、及引线框2的引线键合。
然后,半导体模块如图5所示,向端子壳体1填充液状的浇注树脂18,对半导体芯片13、14及控制IC9进行树脂密封。该浇注树脂18能采用与将电路块11的绝缘基板7粘接至端子壳体1的粘接剂10相同的树脂。通过对浇注树脂18及粘接剂10采用相同的材料,从而能力图实现构件的共用。
接着,对该半导体模块的制作流程的具体例进行说明。
图6是表示半导体模块的制造方法的流程图,图7是表示半导体模块的具体例的图。
如图6所示,半导体模块的制造中,预先利用其他工序分别制成电路块11及端子壳体1。首先,对于电路块11,准备绝缘基板7(步骤S1),在绝缘基板7的一个面涂布焊料(步骤S2)。接着,准备采用IGBT及FWD的半导体芯片13、14(步骤S3),将这些半导体芯片13、14安装到绝缘基板7所涂布的焊料上(步骤S4),将其投入回流炉来进行焊接,从而构成电路块11(步骤S5)。
另一方面,对于端子壳体1,准备预先成型的引线框2(步骤S6),将该引线框2设置于射出成型的模具,通过向该模具射出PPS树脂从而成型得到端子壳体1(步骤S7)。此时,端子壳体1使用推顶销、按压销来形成开口部8。接着,在端子壳体1内引线框2的安装控制IC的安装位置涂布例如热固化型的银糊料(步骤S8)。接着,准备控制IC9(步骤S9),将该控制IC9安装到银糊料上,从而固定于引线框2(步骤S10)。
接着,将在引线框2上安装有控制IC9的端子壳体1进行上下反转(参照图2),在端子壳体1的中央开口部5的周围所形成的阶差部6a涂布粘接剂10。接着,将使半导体芯片13、14的安装面朝下的绝缘基板7安装于阶差部6a,由此,粘接端子壳体1和绝缘基板7(步骤S11)。在该粘接工序中,能使用与现有的端子壳体·绝缘基板粘接相同的工序、设备,因此不会出现因设备、单位工时增加而导致成本上升。
接着,使端子壳体1的上下反转,使绝缘基板7的半导体芯片13、14的安装面及引线框2的控制IC安装面朝上,进行键合线16、17的引线键合(步骤S12)。
接着,对端子壳体1填充作为PPS树脂的浇注树脂18来进行树脂密封(步骤S13)。
说明通过以上工序制造出的半导体模块的具体例。图7所例示的半导体模块20是从树脂密封前的壳体3的上表面进行观察而得的。该半导体模块20中,在电路块11的绝缘基板7上形成六个布线图案12,各布线图案12中安装有采用IGBT的半导体芯片13及采用FWD的半导体芯片14。成为内部布线的引线框2a中安装有三个控制IC9。
此处,布线图案12或半导体芯片13、14与成为引线端子的引线框2通过键合线16进行连接,在引线框2的与键合线16相接合的部位附近的正下方形成有开口部8。由此,引线框2在接合有键合线16的部位附近通过粘接剂10被固定于绝缘基板7。因此,在将键合线16通过超声波接合的方式接合至引线框2的连接面时,不会发生因引线框2晃动而导致接合不良的情况。由于粘接剂10的热传导率高于壳体3的热传导率,因此因引线框2中流过主电流而产生的发热会通过粘接剂10传导至绝缘基板7,从而引线框2的散热性能得以提高。
另一方面,对于形成于引线框2a正下方的开口部8,通过向其填充粘接剂10从而用于将引线框2a固定于绝缘基板7。引线框2a的两端由壳体3的侧壁部4a、4b进行固定,其中间部通过粘接剂10固定于绝缘基板7,由此,更牢固地将引线框2a固定于壳体3。
粘接剂10优选为与引线框2之间的密合性高于与壳体3之间的密合性。由此,即使在壳体3与引线框2之间因线膨胀系数的差异而产生间隙的情况下,也能使引线框2与绝缘基板7之间牢固地紧密接触,从而能提高散热性能。
此外,本发明并不限于上述结构,能根据需要进行适当组合。
上述内容仅示出了本发明的原理。本领域技术人员能进行大量的变形、变更,本发明并不限于上文所示出的或所说明的正确结构及应用例,相对应的所有变形例及等同物均被视为由所附权利要求及等同物所限定的本发明的保护范围。
标号说明
1 端子壳体
2,2a 引线框
3 壳体
4a,4b 侧壁部
5 中央开口部
6a 阶差部
6b 内表面
7 绝缘基板
8 开口部
9 控制IC
10 粘接剂
11 电路块
12 布线图案
13,14 半导体芯片
16,17 键合线
18 浇注树脂
20 半导体模块
Claims (7)
1.一种半导体模块,其特征在于,包括:
引线框,键合线通过超声波接合的方式接合于该引线框;以及
壳体,该壳体在内部具有安装所述引线框的安装面,在外部具有通过粘接剂固定电路块的固定面,在所述引线框的与所述键合线相接合的接合部位的正下方具有以贯通所述安装面和所述固定面之间的方式形成的开口部,其中,所述电路块的绝缘基板上形成有半导体芯片,
所述固定面是沿着形成为边框状的所述壳体的中央开口部的周围形成的阶差部,
向所述开口部填充所述粘接剂,由此对所述引线框与所述电路块进行粘接。
2.如权利要求1所述的半导体模块,其特征在于,
所述壳体还具有以贯穿未接合有所述键合线的所述引线框的正下方的所述安装面和所述固定面之间的方式形成的其他开口部,所述粘接剂填充于所述其他开口部,由此来对所述引线框与所述电路块进行粘接。
3.如权利要求1或2所述的半导体模块,其特征在于,
所述粘接剂是与将所述电路块固定至所述壳体的所述固定面的粘接剂相同的粘接剂。
4.如权利要求1所述的半导体模块,其特征在于,
所述粘接剂的热传导率高于所述壳体的热传导率。
5.如权利要求1所述的半导体模块,其特征在于,
所述粘接剂是与填充至所述壳体以对所述半导体芯片进行树脂密封的浇注树脂相同的树脂。
6.如权利要求1所述的半导体模块,其特征在于,
所述粘接剂与所述引线框之间的附着力高于所述粘接剂与所述壳体之间的附着力。
7.一种半导体模块的制造方法,其特征在于,
以使得壳体在内部具有安装引线框的安装面,以及在与所述安装面相对应的外部具有固定电路块的固定面的方式,利用推顶销或按压销支承所述引线框,并向模具注入树脂,从而成型得到所述壳体,其中,所述电路块的绝缘基板上形成有半导体芯片,
在通过所述推顶销或所述按压销而形成有开口部的所述壳体的所述固定面涂布粘接剂,并使所述粘接剂填充至所述开口部,
将所述电路块载放于涂布有粘接剂的所述壳体的所述固定面,并将所述电路块固定于所述壳体,且利用所述开口部的所述粘接剂将所述引线框固定于所述电路块,
在所述引线框的位于所述开口部的正上方的部位对键合线进行超声波接合。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9824980B2 (en) * | 2014-06-27 | 2017-11-21 | Nxp B.V. | Lead finger locking structure |
JP6824913B2 (ja) * | 2016-02-09 | 2021-02-03 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
JP6701926B2 (ja) * | 2016-04-28 | 2020-05-27 | 富士電機株式会社 | 半導体装置 |
EP3482915B1 (en) * | 2016-07-11 | 2022-06-29 | Zuiko Corporation | Ultrasonic welding device and ultrasonic welding method |
CN109427744B (zh) * | 2017-08-22 | 2023-11-24 | 比亚迪半导体股份有限公司 | Ipm模块、车辆及ipm模块的制作方法 |
JP7172338B2 (ja) | 2018-09-19 | 2022-11-16 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP7238330B2 (ja) * | 2018-10-18 | 2023-03-14 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
JP7038645B2 (ja) * | 2018-12-06 | 2022-03-18 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP7364168B2 (ja) | 2019-02-12 | 2023-10-18 | 住友電工デバイス・イノベーション株式会社 | 半導体モジュール及び半導体デバイス収容体 |
JP7298177B2 (ja) * | 2019-02-15 | 2023-06-27 | 富士電機株式会社 | 半導体モジュール及び半導体モジュールの製造方法 |
JP7392319B2 (ja) * | 2019-08-13 | 2023-12-06 | 富士電機株式会社 | 半導体装置 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313365A (en) * | 1992-06-30 | 1994-05-17 | Motorola, Inc. | Encapsulated electronic package |
CN1449583A (zh) * | 2000-07-25 | 2003-10-15 | Ssi株式会社 | 塑料封装基底、气腔型封装及其制造方法 |
CN101359645A (zh) * | 2007-07-31 | 2009-02-04 | 雅马哈株式会社 | 半导体装置、预模制封装结构及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03178151A (ja) * | 1989-12-06 | 1991-08-02 | Toshiba Corp | 樹脂パッケージ型半導体装置およびその製造方法 |
US5122858A (en) * | 1990-09-10 | 1992-06-16 | Olin Corporation | Lead frame having polymer coated surface portions |
JP3021070U (ja) * | 1995-07-28 | 1996-02-16 | 富士電機株式会社 | 半導体装置 |
US5689089A (en) | 1996-09-20 | 1997-11-18 | Motorola, Inc. | Electronic control module having fluid-tight seals of a polymer material which expands when wet |
JP3022393B2 (ja) * | 1997-04-21 | 2000-03-21 | 日本電気株式会社 | 半導体装置およびリードフレームならびに半導体装置の製造方法 |
JP3843185B2 (ja) * | 1998-10-30 | 2006-11-08 | 三菱電機株式会社 | 半導体装置 |
WO2000028589A1 (en) * | 1998-11-06 | 2000-05-18 | Festec Co., Ltd. | A plastic package having an air cavity and manufacturing method thereof |
JP2001244376A (ja) * | 2000-02-28 | 2001-09-07 | Hitachi Ltd | 半導体装置 |
US6774465B2 (en) * | 2001-10-05 | 2004-08-10 | Fairchild Korea Semiconductor, Ltd. | Semiconductor power package module |
JP4007143B2 (ja) * | 2002-10-09 | 2007-11-14 | 日産自動車株式会社 | 電子部品、電子部品の製造方法及び製造装置 |
DE10340974A1 (de) | 2003-09-05 | 2005-03-24 | Robert Bosch Gmbh | Steuergeräteeinheit und Verfahren zur Hestellung derselben |
DE102004021365A1 (de) | 2004-03-16 | 2005-10-06 | Robert Bosch Gmbh | Gehäuse für eine elektronische Schaltung und Verfahren zum Abdichten des Gehäuses |
JP2005332874A (ja) * | 2004-05-18 | 2005-12-02 | Hitachi Metals Ltd | 回路基板及びこれを用いた半導体装置 |
US20070257343A1 (en) * | 2006-05-05 | 2007-11-08 | Hauenstein Henning M | Die-on-leadframe (dol) with high voltage isolation |
JP4543089B2 (ja) * | 2008-01-11 | 2010-09-15 | 株式会社東芝 | 半導体装置 |
JP5310660B2 (ja) | 2010-07-01 | 2013-10-09 | 富士電機株式会社 | 半導体装置 |
JP2013258321A (ja) | 2012-06-13 | 2013-12-26 | Fuji Electric Co Ltd | 半導体装置 |
WO2014199764A1 (ja) * | 2013-06-10 | 2014-12-18 | 富士電機株式会社 | 半導体装置及びその製造方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5313365A (en) * | 1992-06-30 | 1994-05-17 | Motorola, Inc. | Encapsulated electronic package |
CN1449583A (zh) * | 2000-07-25 | 2003-10-15 | Ssi株式会社 | 塑料封装基底、气腔型封装及其制造方法 |
CN101359645A (zh) * | 2007-07-31 | 2009-02-04 | 雅马哈株式会社 | 半导体装置、预模制封装结构及其制造方法 |
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CN105684147A (zh) | 2016-06-15 |
WO2015166696A1 (ja) | 2015-11-05 |
DE112015000183T5 (de) | 2016-07-21 |
US9837338B2 (en) | 2017-12-05 |
JP6288254B2 (ja) | 2018-03-07 |
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US20160254215A1 (en) | 2016-09-01 |
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