CN105655323A - 半导体模块、电力变换装置 - Google Patents

半导体模块、电力变换装置 Download PDF

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CN105655323A
CN105655323A CN201510849321.3A CN201510849321A CN105655323A CN 105655323 A CN105655323 A CN 105655323A CN 201510849321 A CN201510849321 A CN 201510849321A CN 105655323 A CN105655323 A CN 105655323A
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shielding portion
magnetic shielding
semiconductor module
semiconductor
semiconductor element
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CN105655323B (zh
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米山玲
后藤章
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于提供一种半导体模块、以及具有该半导体模块的电力变换装置,该半导体模块能够将从半导体元件产生的磁场充分地屏蔽。该半导体模块的特征在于,具有:壳体;半导体元件,其设置于该壳体中,对电流进行通断;封装树脂,其设置于该壳体中,覆盖该半导体元件;磁屏蔽部,其与该封装树脂接触,含有磁体;以及填埋磁屏蔽部,其填埋于该壳体中,含有磁体。

Description

半导体模块、电力变换装置
技术领域
本发明涉及一种例如在大电流的通断中使用的半导体模块、和具有该半导体模块的电力变换装置。
背景技术
在专利文献1中公开了一种半导体装置,该半导体装置在覆盖半导体元件的绝缘性树脂上设置了导电性树脂。
专利文献1:日本特开平7-307416号公报
与半导体元件的通断相伴,在半导体元件的周边产生磁场。由于该磁场会对半导体元件的外围设备的动作造成不良影响,因此应当进行屏蔽。但是,在专利文献1公开的技术中存在不能将磁场充分地屏蔽的问题。
发明内容
本发明就是为了解决上述课题而提出的,其目的在于提供一种半导体模块、以及具备该半导体模块的电力变换装置,该半导体模块能够充分地屏蔽从半导体元件产生的磁场。
本发明所涉及的半导体模块的特征在于,具有:壳体;半导体元件,其设置于该壳体中,对电流进行通断;封装树脂,其设置于该壳体中,覆盖该半导体元件;磁屏蔽部,其与该封装树脂接触,含有磁体;以及填埋磁屏蔽部,其填埋于该壳体中,含有磁体。
本发明所涉及的其他半导体模块的特征在于,具有:壳体;半导体元件,其设置于该壳体中,对电流进行通断;封装树脂,其设置于该壳体中,覆盖该半导体元件;磁屏蔽部,其与该封装树脂接触,含有磁体;控制电路基板,其在该壳体中,设置于该磁屏蔽部上方;以及电子部件,其固定于该控制电路基板。
本发明所涉及的电力变换装置的特征在于,具有半导体模块以及控制电路,该半导体模块具有:壳体;半导体元件,其设置于该壳体中,对电流进行通断;封装树脂,其设置于该壳体中,覆盖该半导体元件;磁屏蔽部,其与该封装树脂接触,含有磁体;以及填埋磁屏蔽部,其填埋于该壳体中,含有磁体,该控制电路设置于该半导体模块的外部,向该半导体元件传送控制信号。
发明的效果
根据本发明,通过设置与封装树脂接触的磁屏蔽部、和填埋于壳体中的填埋磁屏蔽部,从而能够将磁场充分地屏蔽。
附图说明
图1是实施方式1所涉及的半导体模块的剖视图。
图2是变形例所涉及的半导体模块的剖视图。
图3是实施方式2所涉及的半导体模块的剖视图。
图4是表示微型变压器构造的图。
图5是实施方式3所涉及的半导体模块的剖视图。
图6是实施方式4所涉及的电力变换装置的概念图。
图7是对比例所涉及的电力变换装置的概念图。
标号的说明
10半导体模块,11基座板,12壁部,13壳体,14信号端子,16电力端子,20绝缘基板,24半导体元件,30封装树脂,32磁屏蔽部,50填埋磁屏蔽部,60控制电路基板,62、64电子部件
具体实施方式
参照附图,对本发明的实施方式所涉及的半导体模块和电力变换装置进行说明。对相同或者相对应的结构要素标注相同的标号,有时省略说明的重复。
实施方式1
图1是本发明的实施方式1所涉及的半导体模块10的剖视图。半导体模块10具备壳体13,该壳体13具有基座板11和壁部12。在壳体13中埋入有信号端子14和电力端子16。信号端子14具有露出至壳体13内部的部分和露出至壳体13外部的部分。电力端子16也是同样的。
在基座板11处利用焊料19固定有绝缘基板20。绝缘基板20具有:陶瓷基板20a;金属层20b,其形成于陶瓷基板20a的底面;以及金属图案20c,其形成于陶瓷基板20a的顶面。
在金属图案20c处利用焊料22固定有半导体元件24。半导体元件24例如是IGBT(InsulatedGateBipolarTransistor)等对电流进行通断的元件。也可以在半导体元件24的基础上搭载续流二极管等。导线28a将半导体元件24的栅极和信号端子14进行连接。导线28b将半导体元件24的发射极和金属图案20c进行连接。导线28c将连接于发射极的金属图案20c和电力端子16进行连接。此外,形成于半导体元件24的背面侧的集电极经由半导体元件24正下方的金属图案20c而与未图示的电力端子连接。
如上所述,绝缘基板20、半导体元件24、以及导线28a、28b、28c收容于壳体13中。在壳体13中设置有覆盖半导体元件24的封装树脂30。在封装树脂30上,以与封装树脂30接触的方式而形成有磁屏蔽部32。磁屏蔽部32形成于封装树脂30的顶面整体。磁屏蔽部32含有磁体。优选磁屏蔽部32是含有磁体的树脂。作为上述树脂,例如存在含有铁素体粉末的环氧树脂。
在壳体13中填埋有填埋磁屏蔽部50。填埋磁屏蔽部50以包围半导体元件24的侧面的方式形成。填埋磁屏蔽部50在俯视观察时,无缝地包围半导体元件24。填埋磁屏蔽部50含有磁体。此外,优选填埋磁屏蔽部50和磁屏蔽部32为相同的材料,将两者一起形成。
在磁屏蔽部32上设置有盖34。半导体元件24根据来自信号端子14的信号进行导通/截止,其主电流流向电力端子16。如果半导体元件24的EMI辐射噪声大,则会由于其磁场使外围设备进行误动作。例如在处理几~几百A数量级的电流的情况下,EMI辐射噪声也会变大。因此,应该使得与半导体元件24的通断相伴而产生的磁场不泄漏至半导体模块10外部。
根据本发明的实施方式1所涉及的半导体模块10,利用磁屏蔽部32和填埋磁屏蔽部50,能够防止由半导体元件24产生的磁场泄漏至外部。即,利用磁屏蔽部32,能够对产生于半导体元件24上方的磁场进行屏蔽,利用填埋磁屏蔽部50,能够对产生于半导体元件24旁侧的磁场进行屏蔽。
在假设磁屏蔽部32和填埋磁屏蔽部50是含有磁体的树脂的情况下,仅通过将该树脂流入至封装树脂30上,就能够容易地形成磁屏蔽部32和填埋磁屏蔽部50。因此,完全不需要用于固定磁屏蔽部32和填埋磁屏蔽部50的构造体。另外,如果使用具有一定程度的流动性的磁屏蔽部32,则通过将其流入至封装树脂30上,从而能够使磁屏蔽部32与封装树脂30的顶面整体和壳体13内壁接触。即,能够使磁屏蔽部32占有充分大的面积。此外,也可以使磁屏蔽部32和填埋磁屏蔽部50含有热硬化性树脂,对它们进行加热而发生硬化。
半导体模块10利用磁屏蔽部32和填埋磁屏蔽部50,对半导体元件24周边的磁场进行屏蔽。因此,在不丧失该特征的范围内,能够进行各种变形。例如,如果磁屏蔽部32和填埋磁屏蔽部50含有磁体,则不特别地予以限定。磁屏蔽部32和填埋磁屏蔽部50也可以是液体、胶体、橡胶、或者弹性体中的任意一种。另外,也可以将板状的固体状态的磁屏蔽部固定于封装树脂处。
磁屏蔽部32和填埋磁屏蔽部50的形成方法不特别地予以限定。例如,也可以将磁屏蔽部32涂敷或分散于封装树脂30。
也可以对半导体模块10的壳体13的构造、用于进行电连接的结构、以及用于进行电绝缘的结构等适当地进行变更。半导体元件24大多由Si形成,但也可以由宽带隙半导体形成。关于高速通断用途的半导体模块等,优选使用与硅相比低损耗且高温耐量高的宽带隙半导体。作为宽带隙半导体,例如存在碳化硅、氮化镓类材料或者金刚石。
通过使用宽带隙半导体,从而能够将半导体模块小型化。并且,磁屏蔽部32和填埋磁屏蔽部50不会增大半导体模块的规模。因此,适合于半导体模块10通过使用宽带隙半导体而实现小型化。
也可以对磁屏蔽部32进行喷雾喷射而喷向封装树脂30。另外,也可以在磁屏蔽部32的基础上,通过在磁屏蔽部32之上或之下形成导电性树脂,从而得到对电场进行屏蔽的效果。在该情况下,如果在壳体中设置有填埋导电性树脂,则能够提高对电场进行屏蔽的效果。
图2是变形例所涉及的半导体模块的剖视图。填埋磁屏蔽部50具有:第1部分50a,其包围半导体元件24的侧面;以及第2部分50b,其设置于半导体元件24的底面侧。由于能够利用磁屏蔽部32、第1部分50a和第2部分50b对半导体元件24进行覆盖,因此能够全方位地对磁场进行屏蔽。
这些变形还能够在以下的实施方式所涉及的半导体模块中应用。此外,关于以下的实施方式所涉及的半导体模块,由于与实施方式1的共同点较多,因此以与实施方式1的不同点为中心进行说明。
实施方式2
图3是实施方式2所涉及的半导体模块的剖视图。在壳体13中,在磁屏蔽部32上方设置有控制电路基板60。控制电路基板60例如是印刷基板。在控制电路基板60的顶面和底面分别固定有电子部件62、64。在控制电路基板60处,固定有伸出至半导体模块外部的端子66。从端子66向控制电路基板60传送的控制信号在电子部件62、64中得到预定的处理,经由信号端子14和导线28a而到达半导体元件24。
图4是表示由固定于控制电路基板60的电子部件所形成的电路的一部分的图。在图4中示出微型变压器构造。所谓微型变压器构造,是指下述构造,即,通过在绝缘的2个线圈74、76间接收/发送磁场,从而在发送电路70和接收电路72之间接收/发送信号。因此,微型变压器构造如果从外部受到磁场的影响,则会进行误动作。
在壳体13中存在半导体元件24和控制电路基板60的情况下,由于两者接近,因此形成于控制电路基板60的电路(构造)可能受到较强的磁场影响。但是,根据本发明的实施方式3所涉及的半导体模块,由于在控制电路基板60和成为磁场的产生源的半导体元件24之间存在磁屏蔽部32,因此能够防止微型变压器构造的误动作。此外,也可以在控制电路基板60处形成除了通过磁场的接收/发送而进行通信的微型变压器以外的电路。
实施方式3
图5是实施方式3所涉及的半导体模块的剖视图。在磁屏蔽部32中,混入与封装树脂30相比热传导率较高的物质。由此,磁屏蔽部32的热传导率变得大于封装树脂30的热传导率。例如,由环氧树脂形成的封装树脂30的热传导率为0.21[W×m-1×K-1],因此将具有比该热传导率高的热传导率的物质混入磁屏蔽部32中。在使磁屏蔽部32含有的磁体为铁素体粉末的情况下,该铁素体粉末大多相当于“与封装树脂相比热传导率较高的物质”。为了充分地提高磁屏蔽部的热传导率,优选使金、银、或者铜等热传导率非常高的物质混入磁屏蔽部中。
磁屏蔽部32的顶面的表面粗糙度大于封装树脂30的顶面的表面粗糙度。由此,磁屏蔽部32的顶面面积大于封装树脂30的顶面面积。
在通常的半导体模块中,由半导体元件产生的热量经由基座板而向半导体元件的下方进行散热。本发明的实施方式3所涉及的半导体模块使磁屏蔽部32采用如上述所示容易进行散热的材料及形状。因此,能够经由磁屏蔽部32而向半导体元件24的上方进行散热。因此,根据本发明的实施方式3所涉及的半导体模块,由于能够向半导体元件的上方和下方这两个方向进行散热,因此能够得到充分的散热性。此外,通过得到充分的散热性,从而能够实现半导体元件自身的小型化及半导体模块的小型化。
实施方式4
图6是本发明的实施方式4所涉及的电力变换装置的概念图。该电力变换装置具有框体90。在框体90中设置有在实施方式1中说明的半导体模块10。也可以将半导体模块10置换为实施方式2或3的半导体模块。在框体90中设置有向半导体元件传送控制信号的控制电路92。控制电路92设置于半导体模块10的外部。
电力变换装置如果是对大电流进行通断的装置,则不特别地予以限定,例如是逆变器电路、转换器电路、伺服放大器、或者电源单元。关于来自电力变换装置的输出,无论是单相、三相、直流、交流等种类均可。
图7是对比例所涉及的电力变换装置的概念图。对比例的电力变换装置具有框体90、以及设置于框体90中的半导体模块94及控制电路92。半导体模块94不具有磁屏蔽部。为了降低从半导体模块94对控制电路92造成的磁场影响,设置有噪声滤波器96a、96b、96c、96d。
在本发明的实施方式5所涉及的电力变换装置中,由于能够利用半导体模块10的磁屏蔽部对由半导体元件产生的磁场进行屏蔽,因此能够省略噪声滤波器,对电力变换装置进行简化。而且,由于不会因设置磁屏蔽部而导致半导体模块的体积增加,因此容易将电力变换装置小型化。此外,也可以对到此为止所说明的各实施方式所涉及的半导体模块或电力变换层的特征适当地进行组合。

Claims (14)

1.一种半导体模块,其特征在于,具有:
壳体;
半导体元件,其设置于所述壳体中,对电流进行通断;
封装树脂,其设置于所述壳体中,覆盖所述半导体元件;
磁屏蔽部,其与所述封装树脂接触,含有磁体;以及
填埋磁屏蔽部,其填埋于所述壳体中,含有磁体。
2.根据权利要求1所述的半导体模块,其特征在于,
所述磁屏蔽部形成于所述封装树脂的顶面整体。
3.根据权利要求1或2所述的半导体模块,其特征在于,
所述填埋磁屏蔽部包围所述半导体元件的侧面。
4.根据权利要求1或2所述的半导体模块,其特征在于,
所述填埋磁屏蔽部设置于所述半导体元件的底面侧。
5.根据权利要求1或2所述的半导体模块,其特征在于,具有:
控制电路基板,其在所述壳体中,设置于所述磁屏蔽部上方;以及
电子部件,其固定于所述控制电路基板。
6.一种半导体模块,其特征在于,具有:
壳体;
半导体元件,其设置于所述壳体中,对电流进行通断;
封装树脂,其设置于所述壳体中,覆盖所述半导体元件;
磁屏蔽部,其与所述封装树脂接触,含有磁体;
控制电路基板,其在所述壳体中,设置于所述磁屏蔽部上方;以及
电子部件,其固定于所述控制电路基板。
7.根据权利要求6所述的半导体模块,其特征在于,
所述电子部件具有通过接收/发送磁场而进行通信的微型变压器。
8.根据权利要求1、2、6中任一项所述的半导体模块,其特征在于,
所述磁屏蔽部的热传导率大于所述封装树脂的热传导率,
所述磁屏蔽部的顶面的表面粗糙度大于所述封装树脂的顶面的表面粗糙度。
9.根据权利要求1、2、6中任一项所述的半导体模块,其特征在于,
所述磁屏蔽部是含有磁体的树脂。
10.根据权利要求9所述的半导体模块,其特征在于,
所述磁屏蔽部是含有铁素体粉末的环氧树脂。
11.根据权利要求1、2、6中任一项所述的半导体模块,其特征在于,
所述磁屏蔽部是液体、胶体、橡胶、或者弹性体中的任一种。
12.根据权利要求1、2、6中任一项所述的半导体模块,其特征在于,
所述半导体元件由宽带隙半导体形成。
13.根据权利要求12所述的半导体模块,其特征在于,
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
14.一种电力变换装置,其具有半导体模块以及控制电路,
该半导体模块具有:壳体;半导体元件,其设置于所述壳体中,对电流进行通断;封装树脂,其设置于所述壳体中,覆盖所述半导体元件;磁屏蔽部,其与所述封装树脂接触,含有磁体;以及填埋磁屏蔽部,其填埋于所述壳体中,含有磁体,
该控制电路设置于所述半导体模块的外部,向所述半导体元件传送控制信号。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110753997A (zh) * 2017-06-21 2020-02-04 三菱电机株式会社 半导体装置、电力转换装置及半导体装置的制造方法
CN110770883A (zh) * 2017-06-22 2020-02-07 三菱电机株式会社 半导体装置及电力变换装置
CN112740401A (zh) * 2018-09-20 2021-04-30 三菱电机株式会社 功率半导体模块以及复合模块

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
WO2016174509A1 (en) * 2015-04-27 2016-11-03 Kabushiki Kaisha Toshiba Magnetic memory device
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10090262B2 (en) * 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
SG11201901194SA (en) 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
SG11201901196RA (en) 2016-08-12 2019-03-28 Qorvo Us Inc Wafer-level package with enhanced performance
JP7035014B2 (ja) 2016-08-12 2022-03-14 コーボ ユーエス,インコーポレイティド 性能が強化されたウェハレベルパッケージ
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10622909B2 (en) 2017-01-12 2020-04-14 Ford Global Technologies, Llc Power module for inverter switching devices having gate coils shielded from eddy currents
JP6790902B2 (ja) * 2017-02-17 2020-11-25 株式会社デンソー 電子装置
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
JP6800121B2 (ja) * 2017-09-21 2020-12-16 三菱電機株式会社 半導体装置および電力変換装置
JP6827404B2 (ja) * 2017-11-30 2021-02-10 三菱電機株式会社 半導体装置および電力変換装置
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
JP7038645B2 (ja) * 2018-12-06 2022-03-18 三菱電機株式会社 半導体装置および半導体装置の製造方法
KR20210129656A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11258356B2 (en) 2019-07-31 2022-02-22 Analog Devices International Unlimited Company Magnetic barrier for power module
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
DE102021105264B4 (de) * 2021-03-04 2024-05-29 Infineon Technologies Ag Leistungselektronikmodul und Verfahren zur Herstellung eines Leistungselektronikmoduls
FR3126571A1 (fr) * 2021-08-26 2023-03-03 Thales Composant de puissance à filtrage local

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893078A (en) * 1987-05-28 1990-01-09 Auchterlonie Richard C Absolute position sensing using sets of windings of different pitches providing respective indications of phase proportional to displacement
US5656857A (en) * 1994-05-12 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor device with insulating resin layer and substrate having low sheet resistance
US20060289970A1 (en) * 2005-06-28 2006-12-28 Dietmar Gogl Magnetic shielding of MRAM chips
US20110285312A1 (en) * 2010-05-18 2011-11-24 Luxera, Inc. Integrated Three Dimensional Inductor and Method of Manufacturing Same
CN102651354A (zh) * 2011-02-28 2012-08-29 株式会社丰田自动织机 半导体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63255945A (ja) 1987-04-13 1988-10-24 Matsushita Electric Ind Co Ltd モジユ−ル部品
US5312674A (en) * 1992-07-31 1994-05-17 Hughes Aircraft Company Low-temperature-cofired-ceramic (LTCC) tape structures including cofired ferromagnetic elements, drop-in components and multi-layer transformer
JP4662324B2 (ja) 2002-11-18 2011-03-30 太陽誘電株式会社 回路モジュール
JP4492454B2 (ja) 2005-06-20 2010-06-30 富士電機システムズ株式会社 パワー半導体モジュール
JP2011151372A (ja) 2009-12-25 2011-08-04 Murata Mfg Co Ltd 電子部品モジュールの製造方法及び電子部品モジュール
JP5195828B2 (ja) 2010-06-15 2013-05-15 三菱電機株式会社 半導体装置
CN102339763B (zh) * 2010-07-21 2016-01-27 飞思卡尔半导体公司 装配集成电路器件的方法
JP5633496B2 (ja) * 2011-09-29 2014-12-03 三菱電機株式会社 半導体装置及びその製造方法
JP5855285B2 (ja) * 2013-01-18 2016-02-09 三菱電機株式会社 信号伝送絶縁デバイス及びパワー半導体モジュール
JP6010005B2 (ja) * 2013-09-09 2016-10-19 株式会社東芝 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4893078A (en) * 1987-05-28 1990-01-09 Auchterlonie Richard C Absolute position sensing using sets of windings of different pitches providing respective indications of phase proportional to displacement
US5656857A (en) * 1994-05-12 1997-08-12 Kabushiki Kaisha Toshiba Semiconductor device with insulating resin layer and substrate having low sheet resistance
US20060289970A1 (en) * 2005-06-28 2006-12-28 Dietmar Gogl Magnetic shielding of MRAM chips
US20110285312A1 (en) * 2010-05-18 2011-11-24 Luxera, Inc. Integrated Three Dimensional Inductor and Method of Manufacturing Same
CN102651354A (zh) * 2011-02-28 2012-08-29 株式会社丰田自动织机 半导体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110753997A (zh) * 2017-06-21 2020-02-04 三菱电机株式会社 半导体装置、电力转换装置及半导体装置的制造方法
CN110770883A (zh) * 2017-06-22 2020-02-07 三菱电机株式会社 半导体装置及电力变换装置
CN110770883B (zh) * 2017-06-22 2023-08-22 三菱电机株式会社 半导体装置、电力变换装置及半导体装置的制造方法
CN112740401A (zh) * 2018-09-20 2021-04-30 三菱电机株式会社 功率半导体模块以及复合模块
CN112740401B (zh) * 2018-09-20 2023-11-03 三菱电机株式会社 功率半导体模块以及复合模块

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