CN105047634A - 半导体部件之间的隔离 - Google Patents

半导体部件之间的隔离 Download PDF

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Publication number
CN105047634A
CN105047634A CN201510015097.8A CN201510015097A CN105047634A CN 105047634 A CN105047634 A CN 105047634A CN 201510015097 A CN201510015097 A CN 201510015097A CN 105047634 A CN105047634 A CN 105047634A
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CN
China
Prior art keywords
semiconductor element
bridger
conductive
buffer circuit
character buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510015097.8A
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English (en)
Inventor
约翰·康斯坦丁诺
蒂姆瓦·卢克
艾哈迈德·阿什拉夫扎德
罗伯特·L·克劳泽
埃坦·莎萨穆
玛丽亚·克莱门斯·伊皮尔·基诺内斯
雅努什·布雷泽克
吴钟林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Suzhou Co Ltd
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Suzhou Co Ltd
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Suzhou Co Ltd, Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Suzhou Co Ltd
Publication of CN105047634A publication Critical patent/CN105047634A/zh
Pending legal-status Critical Current

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Abstract

本发明涉及半导体部件之间的隔离。在一些一般方面，一种装置可包括设置为邻近第一引线框部分的第一半导体管芯、设置为邻近第二引线框部分的第二半导体管芯，以及耦接到所述第一半导体管芯和所述第二半导体管芯的电容性隔离电路。所述电容性隔离电路可设置在所述第一半导体管芯和所述第二半导体管芯外部。所述第一半导体管芯、所述第二半导体管芯和所述电容性电路可包括在半导体封装的模制物中。<pb pnum="1" />

Description

半导体部件之间的隔离
相关申请
本专利申请要求于2014年1月10日提交的美国临时专利申请61/926,030的优先权和权益，该专利申请据此全文以引用方式并入本文。
技术领域
本说明涉及半导体器件的隔离。
背景技术
可在以不同电压电平工作的多个半导体电路之间使用隔离器，以便隔离这些电路但准许这些电路之间的数据交换。常规地，这些隔离可包括光耦合器、电容器、变压器、小型磁性线圈或巨磁寄存器(GMR)作为半导体电路之间的隔离元件。然而，在一些常规方法中，隔离器可被集成(或构建)在半导体部件本身内，其使用顶部金属层与底部金属层(以及中间层)之间的金属电容来形成基于电容的绝缘体，并且此绝缘是由半导体部件主体内的金属层之间的氧化物层或薄聚酰亚胺条带提供的。电容器顶部隔离触点与底部隔离触点之间的电介质堆叠的厚度决定了绝缘穿透距离并且限制了能够实现的最大隔离电压。常规地，这些隔离器已经在其绝缘穿透距离方面受到限制，这可能会降低绝缘性能并增加静电放电(ESD)风险，从而降低器件的绝缘特性。
发明内容
在一些一般方面，一种装置可包括设置为邻近第一引线框部分的第一半导体管芯、设置为邻近第二引线框部分的第二半导体管芯，以及耦接到第一半导体管芯和第二半导体管芯的电容性隔离电路。电容性隔离电路可设置在第一半导体管芯和第二半导体管芯外部。第一半导体管芯、第二半导体管芯和电容性电路可包括在半导体封装的模制物中。
在附图和以下说明中给出了一个或多个具体实施的细节。其他特征从说明和附图中以及从权利要求中将显而易见。
附图说明
图1示出了用于提供多个半导体管芯之间的隔离的装置；
图2A至图2E示出了使用反转基板和倒装芯片构型的半导体封装的各种视图；
图3示出了用于构造图2A至图2E的半导体封装的预处理流程；
图4示出了用于构造图2A至图2E的半导体封装的封装组装流程；
图5示出了用于构造图2A至图2E的半导体封装的处理流程；
图6A和图6B示出了半导体封装的视图；
图7A至图7C示出了隔离基板桥接器的透视图；
图8A至图8C示出了隔离基板桥接器的各种视图；
图9A至图9E示出了半导体封装的各种视图；
图10示出了半导体封装；并且
图11示出了用于构造图9或图10的半导体封装的处理流程。
具体实施方式
本文的公开与一种半导体装置相关，该半导体装置在第一半导体管芯与第二半导体管芯之间提供基于非光学的电容性隔离电路，使得电容性隔离电路不仅提供第一半导体管芯与第二半导体管芯之间的电流隔离，而且充当用以跨越电容性隔离电路传送数据的传输系统。另外，电容性隔离电路被提供在第一半导体管芯和第二半导体管芯外部但在半导体封装的模制物内。第一半导体管芯和第二半导体管芯可耦接到引线框(或其部分)。换句话讲，与常规技术相反，不是在半导体管芯本身的主体内形成(或构建)隔离器，而是在半导体管芯外部(但仍在半导体模制物内)设置电容性隔离电路，使得能够增大绝缘穿透距离。因此，具有电容性隔离电路的半导体装置可支持在相对紧凑封装内具有相对较高电压电平的应用，从而在多个半导体管芯之间提供充分的隔离，同时准许以安全方式跨越绝缘屏障进行相对快速的传输。
图1示出了用于提供多个半导体管芯之间的隔离的装置100。在一些具体实施中，装置100提供多个半导体管芯之间的电流隔离。电流隔离可以是指这样的概念：隔离电子器件的功能区段以阻止或基本上阻止电流流动(例如，没有直接导电路径)但允许通过其他方式(诸如电容)进行信息交换。装置100可包括设置为邻近(例如，设置在其上、耦接到、直接耦接到)第一引线框部分110的第一半导体管芯102、设置为邻近(例如，设置在其上、耦接到、直接耦接到)第二引线框部分112的第二半导体管芯108，以及经由第一导电部件104-1耦接到第一半导体管芯102并且经由第二导电部件104-2耦接到第二半导体管芯108的电容性隔离电路106。在一些具体实施中，装置100可包括在半导体封装的模制物(未示出)内。例如，半导体封装的模制物可包括一个或多个类型的材料(例如，在包括多种类型材料的情况下，呈模制化合物形式)，诸如金属、塑料、树脂、环氧树脂、酚类硬化剂、硅基材料、颜料、玻璃、陶瓷壳体和/或诸如此类，并且可含有(或包封)至少图1的部件。
第一半导体管芯102和/或第二半导体管芯108可为或包括具有集成电路、处理器、微处理器、存储器和/或任何半导体器件或电路的半导体材料。在一些具体实施中，半导体管芯102、108中的一者或多者可包括多种半导体器件。在一些具体实施中，第一半导体管芯102可在与第二半导体管芯108不同的电压电平下工作。在一些具体实施中，半导体管芯102、108中的一者或多者可为或可包括分立半导体器件。具体地说，半导体管芯102、108中的一者或多者可为或可包括横向取向的晶体管器件(例如，横向金属氧化物半导体场效应晶体管(MOSFET)器件)和/或纵向取向的晶体管器件(例如，纵向MOSFET器件)。在一些具体实施中，半导体管芯102、108中的一者或多者可为或可包括双极结型晶体管(BJT)器件、二极管器件、绝缘栅双极型晶体管(IGBT)器件和/或诸如此类。在一些具体实施中，半导体管芯102、108中的一者或多者可为或可包括电路，诸如滤波器电路、控制器电路、驱动电路、通信电路(例如，接收器和/或发射器)和/或诸如此类。在一些具体实施中，半导体管芯102、108中的一者或多者可为用于任何类型的功能的任何类型的电路。在一些具体实施中，半导体管芯102、108中的一者或多者可包括专用逻辑电路、组合逻辑、现场可编程门阵列(FPGA)、专用集成电路(ASIC)。在一些具体实施中，半导体管芯102和/或半导体管芯108可替代地为模块(例如，分立器件模块、封装器件模块)。在一些具体实施中，第一半导体管芯102和第二半导体管芯108中的每者可包括单个集成电路或可为独立集成电路。在一些具体实施中，在半导体封装(例如，混合选项或3管芯构型)内以参考图27所描述的方式提供额外半导体管芯。在一些具体实施中，半导体材料可为电子级硅或任何其他类型的半导体基板。作为具体例子，第一半导体管芯102可为包括形成在半导体材料上的控制器器件的控制器管芯，并且第二半导体管芯108可为包括形成在半导体材料上的驱动器器件的驱动器管芯，反之亦然。在一些具体实施中，驱动器管芯可被视为或可充当输出管芯。
在一些具体实施中，第一引线框部分110和第二引线框部分112可包括在同一引线框中，但可为同一引线框的不同部分。在其他具体实施中，第一引线框部分110和第二引线框部分112可涉及两个独立引线框。例如，第一引线框部分110可包括在第一引线框的一部分中，并且第二引线框部分112可包括在第二引线框的与第一引线框分开的一部分中。在任一种情况下，第一引线框部分110和第二引线框部分112可为可在半导体封装内使用的任何类型的导电结构，包括铜、铜合金、铝和/或诸如此类。
在一些具体实施中，如图1所示，第一半导体管芯102可设置在第一引线框部分110的顶表面上，并且第二半导体管芯108可设置在第二引线框部分112的顶表面上。如本文所论述，术语“顶部”和“底部”是指当装置100/半导体封装在某个取向内时对应部件的相对位置。在一些具体实施中，装置100的一部分或远离引线框部分110、112的方向(基本上沿着方向A1)可称为顶部部分或向上方向。在一些具体实施中，装置100的一部分或远离引线框部分110、112的方向(基本上沿着方向A1)可称为底部部分或向下方向。垂直于纸面向内的方向A3(示为圆点)沿着平面A4对准或与平面A4平行并且与方向A1和A2正交。在本文所述的具体实施中，竖直方向垂直于某个平面，半导体管芯102、108沿着该平面(例如，平面A4)对准。为简单起见，在所有图中描述的具体实施的各个视图中的若干视图均使用方向A1、A2、A3以及平面A4。
另外，值得注意的是，尽管图1描绘第一半导体管芯102和第二半导体管芯108在顶部并且分别与第一引线框部分110的内边缘103和第二引线框部分112的内边缘105对准，但第一半导体管芯102和第二半导体管芯108可设置在沿着其相应引线框部分110、112的顶表面的任何位置处。例如，可通过在沿着方向A2远离引线框部分110、112的内边缘103、105的位置设置这些半导体管芯102、108，来使第一半导体管芯102与第二半导体管芯108进一步间隔开。不管沿着引线框部分的顶表面的位置如何，使用任何类型的管芯附接材料(例如，导电环氧树脂、焊料凸块、粘合剂等)，第一半导体管芯102可耦接到第一引线框部分110的顶表面，并且第二半导体管芯108可耦接到第二引线框部分112的顶表面。
在其他具体实施中，第一半导体管芯102可设置在第一引线框部分110上方(沿着竖直方向)、在第一引线框部分110下方(沿着竖直方向)和/或相邻于第一引线框部分110(沿着横向方向)，并且第二半导体管芯108可设置在第二引线框部分112上方、在第二引线框部分112下方或相邻于第二引线框部分112。在一些具体实施中，第一半导体管芯102和第二半导体管芯108可至少部分地由电容性隔离电路106支撑，并且第一半导体管芯102和第二半导体管芯108可使用导电环氧树脂、导电板、焊料凸块或大体上任何类型的附接材料耦接到其相应引线框部分。
如图1所示，电容性隔离电路106可经由第一导电部件104-1耦接到第一半导体管芯102，并且电容性隔离电路106可经由第二导电部件104-2耦接到第二半导体管芯108。在一些具体实施中，第一导电部件104-1和第二导电部件104-2可为键合引线、焊料或环氧树脂，或者它们的任何组合。例如，键合引线可为导电(例如，金属)引线，诸如铝、铜或金，或者它们的任何组合。焊料可为易熔导电合金(例如，金属合金)。在一个具体实施中，焊料可为多个焊球。环氧树脂可为任何类型的导电环氧树脂。另外，电容性隔离电路106可设置在相对于第一半导体管芯102和第二半导体管芯108的任何位置，如下文进一步说明。
一般来说，电容性隔离电路106可在隔离器内限定电容性耦合网络，其可准许穿过绝缘材料或基板在第一半导体管芯102与第二半导体管芯108之间传输数据。例如，第一半导体管芯102可经由电容性隔离电路106向第二半导体管芯108发送数据或从第二半导体管芯108接收数据。例如，电容性隔离电路106可为在隔离材料内经由电场提供传输路径的结构。在一些具体实施中，电容性隔离电路106可包括一个、两个或更多个传输路径或传输线，它们可形成在电容性隔离电路106上方、下方或嵌入在电容性隔离电路106的介电基板内。在一些具体实施中，电容性隔离电路106(或参考任何附图描述的任何电容性隔离电路)可支持差分通信。在一些具体实施中，电容性隔离电路106(或参考任何附图描述的任何电容性隔离电路)可支持双向差分通信。相对于双向差分通信，电容性隔离电路106可限定双向差分通信信道。为了实现双向差分通信，在一些具体实施中，电容性隔离电路106可包括两个不同的传输网络(例如，一个用于一个方向，并且另一个用于相反方向)，其中每个传输网络可包括一对导电传输线，这对导电传输线用于在第一半导体管芯102和/或第二半导体管芯108处进行差分感测。在一些具体实施中，电容性隔离电路106可任选地包括用于双向差分通信的单个传输网络。在一些具体实施中，双向差分通信信道可由两对导电传输线形成，例如，第一对导电传输线将用以在一个方向上传输数据，并且第二对导电传输线将用以在另一个方向上传输数据。此外，电容性隔离电路106可被配置为支持多个双向信道，诸如双重双向差分通信信道(例如，八对导电传输线)。然而，一般来说，本文描述的任何电容性隔离电路或隔离基板桥接器可支持任何类型的通信网络。电容性隔离电路106的这些和其他特征在下文中进一步描述。
在一些具体实施中，电容性隔离电路106可被配置为准许第一半导体管芯102和第二半导体管芯108在相对较高的电压电平下通信，诸如高达以及高于20KV的任何电压电平。如下文进一步描述，电容性隔离电路106可提供绝缘穿透距离(其在下文中更详细描述)，此绝缘穿透距离准许装置100在这些高电压电平下相对安全地工作，并且静电放电(ESD)或其他高电压事件对隔离屏障造成损坏的风险减小，同时满足装配在紧凑半导体封装内的间距要求。
在一般性具体实施中，电容性隔离电路106可包括介电材料或基板、第一导电层和第二导电层。在一些具体实施中，电容性隔离电路106可包括介电基板，其具有位于顶表面、底表面的至少一部分上和/或嵌入在介电基板内的导体。
在一些具体实施中，第一导电层(也可称为电极、顶部金属垫、线、板等)可形成在介电基板的顶表面的至少一部分上，并且第二导电层(也可称为电极、底部金属垫、线、板等)可形成在介电材料的底表面的至少一部分上。另外，在一些具体实施中，介电基板可为单个连续材料片，其中导体位于介电基板的每一侧的至少一部分上和/或嵌入在介电基板内(例如，隔离基板桥接器具体实施)。在其他例子中，介电材料可为两个独立部分的介电材料，其夹层有用一个或多个键合引线连接的导体(例如，如图3A所示)。
介电基板可为任何类型的绝缘或隔离材料。在一些具体实施中，介电基板可为介电常数大于空气的任何类型的材料。在一些具体实施中，介电基板可为任何类型的玻璃材料(诸如基于二氧化硅的玻璃材料)、共烧电介质和/或任何类型的陶瓷材料(诸如基于氧化铝的陶瓷材料)。在一些具体实施中，介电材料的厚度可提供等于或超过0.1毫米(mm)的绝缘穿透距离。下文进一步说明绝缘穿透距离。电容性隔离电路106的导体和介电材料可在电容性隔离电路106内形成电容性网络。在简化表征中，电容性网络可被描述为使用电容性隔离电路106的导电层和介电材料限定至少两个电容器。然后，第一半导体管芯102可通过调制信号以使其在电场内跨越电容性隔离电路106的电容器来将该信号发送到第二半导体管芯108-其可使用一个或多个导电传输线。
在一些具体实施中，电容性隔离电路106可限定具有至少两个电容器网络的耦合网络，所述电容器网络诸如设置在第一半导体管芯102顶部的第一电容器网络和设置在第二半导体管芯108顶部的第二电容器网络。第一电容器网络和第二电容器网络中的每者可由顶部导电板、底部导电板和设置在底部导电板与顶部导电板之间的介电材料限定。在该具体实施中，第一电容器网络的底板可经由第一导电部件104-1耦接到第一半导体管芯102的导电垫(例如，金属垫)，并且第二电容器网络的底板可经由第二导电部件104-2耦接到第二半导体管芯108的导电垫。此外，电容性隔离电路106可包括键合引线，其耦接到第一电容器网络的顶板和第二电容器网络的顶板。然而，电容性隔离电路106可包括其他构型，如参考其他附图进一步说明。
不管电容性隔离电路106的具体实施的类型如何，如图1所示，电容性隔离电路106设置在第一半导体管芯102和第二半导体管芯108外部。例如，第一半导体管芯102和第二半导体管芯108中的每者可包括顶部导电层(或顶部导电接触垫)和底部导电层。顶部导电接触垫可为半导体管芯的接触点或连接点。此外，这些半导体管芯102、108可在导电层之间包括其他中间层以及二氧化硅层。在一些具体实施中，电容性隔离电路106可设置在第一半导体管芯102和第二半导体管芯108的顶部导电接触垫(和底部导电层)外部。然而，第一半导体管芯102、第二半导体管芯108和电容性隔离电路106包括在半导体封装的模制物中。在一些具体实施中，半导体封装的模制物可为或可包括导体、塑料、玻璃或陶瓷壳体，其含有图1的部件，包括第一半导体管芯102、第二半导体管芯108和电容性隔离电路106。这样，与常规绝缘体相比，可增大绝缘穿透距离，如下文进一步描述。
在一些具体实施中，参考图1论述的电容性隔离电路106(或参考任何附图论述的任何隔离器)可提供大于或等于0.1mm的绝缘穿透距离，其大于现有数字隔离方案能够实现的绝缘穿透距离(例如，现有数字隔离方案可仅能够实现几十微米数量级的绝缘穿透距离)。在一些例子中，绝缘穿透距离可基于第一引线框部分110与第二引线框部分112之间的间距(D3)，以及电容性隔离电路106的介电材料的厚度(T)。D1、D2、D3可指各种距离或路径。更一般地说，绝缘穿透距离可被限定为第一半导体管芯侧上的导电元件与第二半导体管芯侧上的导电元件之间的最短路径。在一个例子中，第一引线框部分110与第二引线框部分112之间的距离(D3)可被视为一个路径。另外，电容性隔离电路106的介电材料的组合介电厚度(2T)可被视为另一个路径(D1+D2)。这两个路径中的较短者可限定绝缘穿透距离。
在非限制性实例中，介电材料的介电厚度(T)可为0.5mm。这样，在这个路径内，绝缘穿透距离可为1mm，因为信号将调制穿透介电材料在第一半导体管芯102一侧的厚度(经由D1)，并且将再次调制穿透介电材料在第二半导体管芯108一侧的厚度(T)(经由D2)。在图1中，仅出于清楚起见而在一个方向上示出路径(D1+D2)。例如，相对于一个方向示出路径(D1+D2)，但是该路径也可在相反方向上(D2+D1)。另外，值得注意的是，任何其他附图也可为这种情况。介电材料的组合厚度(2T)可指信号必须调制穿透以便在半导体管芯102、108中的一者处被接收的介电材料的厚度(例如，D1+D2)。继续这个例子，如果第一引线框部分110与第二引线框部分112之间的距离(D3)为0.5mm，则绝缘穿透距离将为0.5mm，因为绝缘穿透距离被限定为两个路径中的最短者。这样，根据一个实施例，电容性隔离电路106的介电材料的组合厚度(2T)可等于或大于第一引线框部分110与第二引线框部分112之间的距离(D3)。另外，电容性隔离电路106的介电材料的组合厚度(2T)可被限定为大于或等于0.1mm的任何值，并且该值可等于或大于第一引线框部分110与第二引线框部分112之间的距离(D3)。绝缘穿透距离的这些概念可适用于本文描述的各种其他附图的其他具体实施。
与将电容器集成在半导体管芯本身内以便提供电流隔离相反，将电容性隔离电路106构建在半导体管芯的构造外部(例如，在外表面外部，在体积外部)但在半导体封装内，使得可按所需方式增大绝缘穿透距离。因此，除了半导体封装的间距限制之外，与将其隔离器构造在半导体管芯本身的氧化物层内的常规非光学隔离相比，绝缘穿透距离不受限制。例如，常规隔离器的氧化物的厚度由于开裂和其他均匀度问题而受到限制，并且因此绝缘穿透距离限于小于0.1mm的值。另外，如果使用磁性变压器(与电容器形成对照)，则在变压器线圈之间提供额外间距(例如，以便增大绝缘穿透距离)可造成传输路径发生问题，因为将没有信号耦合。因此，电容性隔离器电路106可在装配在相对较小半导体封装内时提供等于或大于0.1mm的绝缘穿透距离(D1+D2)。
图2A示出了使用反转基板和倒装芯片构型的半导体封装200的横截面图。图2B示出了图2A的横截面图的一部分的更详细视图。在该构型中，隔离基板桥接器201的一个末端部分213耦接到第一引线框部分210的顶表面，并且隔离基板桥接器201的另一个末端部分215耦接到第二引线框部分212的顶表面。此外，与将半导体管芯202、208耦接到隔离基板桥接器201的顶表面(例如，其与引线框部分210、212相对)相反，半导体管芯202、208耦接到隔离基板桥接器201的用于附接引线框部分210、212的同一底表面(例如，在同一平面A4内)。在此语境中，图2A至图2B的隔离基板桥接器201的构型可被视为被反转。
参考图2A，隔离基板桥接器201可耦接到并且设置在引线框部分210、212的顶表面上。第一半导体管芯202可经由导电部件(例如，232、230和/或236)耦接到并且设置在隔离基板桥接器201邻近第一引线框部分210的一部分上。具体来讲，第一半导体管芯202可设置在隔离基板桥接器201连接到第一引线框部分210的同一底表面上。在一些具体实施中，第一半导体管芯202可设置在隔离基板桥接器201的底表面上的某个位置处，该位置具有离第一引线框部分210的特定距离(D4)。第二半导体管芯208可耦接到并且设置在隔离基板桥接器201邻近第二引线框部分212的一部分上。具体来讲，第二半导体管芯208可设置在隔离基板桥接器201连接到第二引线框部分212的同一底表面上。在一些具体实施中，第二半导体管芯208可设置在隔离基板桥接器201的底表面上的某个位置处，该位置具有离第二引线框部分212的特定距离(D5)。距离(D4)和距离(D5)可相同或不同，并且涵盖任何值。在一些具体实施中，第一半导体管芯202和第二半导体管芯208可按某种方式设置在并且耦接到隔离基板桥接器201的同一底表面上，使得第一半导体管芯202近似对准第一引线框部分210但位于离第一引线框部分210的距离(D4)处，并且第二半导体管芯208近似对准第二引线框部分212但位于离第二引线框部分212的距离(D5)处。
仍参考图2A，隔离基板桥接器201可包括介电基板，该介电基板具有集成电容器网络214，诸如构造在隔离基板桥接器201的一部分内的第一电容器网络214-1和构造在隔离基板桥接器201的另一部分内的第二电容器网络214-2。参考图7和图8进一步描述了电容器网络214的构造。隔离基板桥接器201可包括设置在隔离基板桥接器201的顶表面(例如，与具有半导体管芯202、208的表面相对的表面)上的一个或多个导电传输线203。在一些具体实施中，导电传输线203可设置在隔离基板桥接器201的表面上朝向隔离基板桥接器201的中间部分的位置处。在一些具体实施中，导电传输线203的一部分可设置在隔离基板桥接器201的顶表面上位于第一半导体管芯202与第二半导体管芯208之间的任何位置处。在一些具体实施中，导电传输线203可为铜。然而，一般来说，导电传输线203可由能够传输信号的任何类型的材料构成。导电传输线203可为从介电材料内的一个位置延伸到介电基板上的另一个位置的相对薄且长的导体条带。然而，导电传输线203可具有参考任何附图说明的结构。在其他具体实施中，隔离基板桥接器201可包括多个导电传输线，使得这些导电传输线被配置为多个通信信道，如下文进一步描述。
参考图2A，在一些具体实施中，第一半导体管芯202可被配置为与第二半导体管芯208传送数据(反之亦然)。具体来讲，信号可调制穿透介电材料(经由D1)，传输跨越所述一个或多个导电传输线203，随后调制穿透介电材料(经由D2)。在该例子中，可基于介电材料的厚度(T)来限定绝缘穿透距离(2T)。如上所述，如果介电材料的厚度(T)为0.5mm(例如，组合厚度(2T)将为1mm，这是由于信号经由D1调制穿过介电材料并且经由D2调制穿过介电材料的事实)，则绝缘穿透距离将为1mm。因此，根据所述实施例，第一半导体管芯202与第二半导体管芯208之间的距离(D3)可等于或大于最小组合厚度(2T)。另外，在一些具体实施中，绝缘穿透距离(T)可大于或等于0.1mm。
图2B示出了图2A的半导体封装200的部分217(例如，由具有虚线的矩形框描绘)的更详细视图。例如，图2B示出了隔离基板桥接器201的底表面的一部分、第二引线框部分212和第二半导体管芯208的一部分之间的连接。
一般来说，每个半导体管芯202、208可使用任何类型的导电材料(诸如焊料)附接到隔离基板桥接器201的表面。在一些实施例中，每个半导体管芯202、208可使用设置在相应半导体管芯202或208的末端部分上的两个导电部件附接到隔离基板桥接器201的底表面。在一些实施例中，每个半导体管芯202、208可使用以下各项附接到隔离基板桥接器201：(1)堆叠在半导体管芯202、208的邻近其相应引线框部分210、212的末端部分与隔离基板桥接器201的底表面之间的导电部件230(例如，凸块)、导电材料232(例如，焊料)和导电部件236；和(2)形成在半导体管芯202、202的邻近另一半导体管芯202、208的另一末端部分与隔离基板桥接器201的底表面之间的导电部件230(例如，凸块)和导电材料232(例如，焊料)。
图2B示出了第二半导体管芯208的一部分、第二引线框部分212和隔离基板桥接器201的末端部分之间的连接的更详细视图。参考图2B，导电部件236可设置在隔离基板桥接器201的底表面上朝向隔离基板桥接器201邻近第二引线框部分212的末端部分。在一些实施例中，导电部件236可被视为在方向A2上延伸的导电板。导电部件236可设置在隔离基板桥接器201上或覆盖(例如，包覆)隔离基板桥接器201的仅一部分。在一些具体实施中，导电部件236可经由任何类型的焊料或粘合剂连接材料耦接到第二引线框部分212，并且沿着隔离基板桥接器201的底表面的一部分延伸，其中导电部件236的另一个末端部分用以连接到第二半导体管芯208。
第二半导体管芯208可经由导电部件230从介电基板移位。在一些具体实施中，导电部件230可为金属凸块，诸如铜凸块。在一些具体实施中，导电部件230可为第二半导体管芯208的延伸部，并且可被视为提供第二半导体管芯208的外部接触点的导电垫。导电部件230可经由导电材料232(诸如导电焊料)耦接到导电部件236。在其他具体实施中，省略导电部件230，并且第二半导体管芯208的导体可经由导电材料(诸如导电环氧树脂、焊料或任何其他类型的导电材料)耦接到导电部件236。
图2C至图2E示出了具有在单信道基板上通信的多对半导体管芯的半导体封装200。图2C示出了半导体封装200的顶视图，图2D示出了半导体封装200的底视图，并且图2E示出了半导体封装200的另一个透视图。一般来讲，图2C至图2E示出半导体封装200具有用于多对半导体管芯202、208的反转基板和倒装芯片构型，并且每一对沿着形成单信道基板的传输线通信。在一些具体实施中，每个基板可包括两个传输线以用于单向差分通信。这两个基板可在相反方向上传送信号。
参考图2C至图2E，隔离基板桥接器201(例如，具有介电基板)可连接第一半导体管芯202和第二半导体管芯208。另外，半导体封装200可包括用隔离基板桥接器连接的另一对半导体管芯，其可与半导体管芯202、208和隔离基板桥接器201相同或不同。如图2C所示，隔离基板桥接器201可包括设置在隔离基板桥接器201的表面上的多个导电传输线203。在一些具体实施中，每个隔离基板桥接器201可包括两个导电传输线203。此外，除了图2所示的物理上分开的选项之外，额外信道或导电传输线203可集成到同一组半导体管芯202、208和同一隔离基板桥接器201中。
图3示出了根据实施例的用于构造图2A至图2E的半导体封装200的预处理流程300。虽然图3被示出为连续有序的操作列表，但应当理解，一些或所有操作可按不同次序或并行或反复发生，或者可在时间上重叠。
可在隔离基板桥接器上印刷焊料(302)，并且可将第一半导体管芯和第二半导体管芯附接到隔离基板桥接器(304)。可执行焊料回流(306)和助焊剂清除(308)。可通过将基板切割为具有第一半导体管芯和第二半导体管芯的部分来执行基板(例如，陶瓷基板)分离(310)。因此，预处理流程可产生多个部分，其中每个部分包括设置在隔离基板桥接器上的第一半导体管芯和第二半导体管芯。参考图3，在(311)中，在图中上部示出单个部分的顶面，并且在图中下部示出该部分的背面。
图4示出了用于构造图2A至图2E的半导体封装200的封装组装流程400。图4可为图3的延续。虽然图4被示出为连续有序的操作列表，但应当理解，一些或所有操作可按不同次序或并行或反复发生，或者可在时间上重叠。
可在引线框部分上印刷焊料或粘合剂(402)，并且可附接加载有半导体管芯的隔离基板桥接器(404)。例如，加载的隔离基板桥接器可为具有该对耦接半导体管芯的隔离基板桥接器，如图15的(411)所示。可执行焊料回流/粘合剂固化(406)、助焊剂清除(如果使用焊料的话)(408)和等离子体清洁(410)。然后，可模制半导体装置并且对其进行模制后烘烤(PMB)(412)。可执行修剪和成形(414)、电气测试(416)、修剪和成形(418)，以及包括打标和TNR的精修(420)。
图5示出了根据实施例的用于构造图2A至图2E的半导体封装200的处理流程500。例如，处理流程500可为图3和图4的处理流程的另选方案。虽然图5示出为连续有序的操作列表，但应当理解，一些或所有操作可按不同次序或并行或反复发生，或者可在时间上重叠。可执行焊料印刷(502)、陶瓷基板附接(504)、高熔点焊料回流(506)、助熔和输入倒装芯片附接(508)、助熔和输出倒装芯片附接(510)、无PB焊料回流和助熔剂清除(512)、等离子体清洁(514)、模制、PMB、镀后处理，和SRB(516)、修剪和成形(518)以及测试和精修(520)。
图6A至图6B示出了被配置成双信道通信设备的半导体封装600，其具有一对半导体管芯602、608以及隔离基板桥接器601。图6A示出了半导体封装600的顶视图，并且图6B示出了半导体封装600的底视图。半导体封装600可为图2A至2B的半导体封装，其具有反转基板和倒装芯片构型，但被配置为双通信信道。
参考图6A至图6B，隔离基板桥接器601(例如，具有介电基板)可连接第一半导体管芯602和第二半导体管芯608。如图6A所示，隔离基板桥接器601可包括设置在隔离基板桥接器601的表面上的多个导电传输线603。在一些具体实施中，隔离基板桥接器601可包括两组两个导电传输线603，其中每组导电传输线603可作为差分传输网络工作。
图7A至图7C示出了隔离基板桥接器701的各种透视图，该隔离基板桥接器可用于提供一对半导体管芯之间的隔离。隔离基板桥接器701可为图2C至图2E的隔离基板桥接器701的各种具体实施(例如，设置在单个隔离基板桥接器上的一对半导体管芯)，其可包括反转基板以及倒装芯片构型。图7A示出了隔离基板桥接器701的透视图。图7B示出了隔离基板桥接器701的顶视图。图7C示出了隔离基板桥接器701的底视图。值得注意的是，与图2C至图2E的视图相比，隔离基板桥接器701被反转(例如，在图7A至图7C中，导电传输线703出现在基板的底部上，这与图2C至图2E的在基板的顶表面上的情况相反)。
参考图7A至图7C，隔离基板桥接器701可包括设置在隔离基板桥接器701的上表面的两个末端部分上的多个框架导体722。在一些具体实施中，框架导体722可为用于连接到引线框部分的导电板(例如，铜)。另外，隔离基板桥接器701可包括设置在上表面上以用于连接到第一半导体管芯的两个管芯导体736，以及设置在上表面上以用于连接到第二半导体管芯的两个管芯导体736。在一些具体实施中，管芯导体736可被视为电容器垫、电容器板和/或电容器导体。在一些具体实施中，导体736可具有基于环行器的结构。此外，隔离基板桥接器701可包括底表面上的两个导电传输线703。导电传输线703可具有参考任何附图描述的结构。形成在隔离基板桥接器701上的两个导电传输线703可充当用以在半导体管芯702、708之间交换数据的通信信道。
在一些具体实施中，隔离基板桥接器701的电容器网络可由管芯导体736和导电传输线703，以及设置在管芯导体736与导电传输线703之间的介电材料形成。
图8A至图8C示出了隔离基板桥接器801的各种透视图，该隔离基板桥接器可用于提供一对半导体管芯之间的隔离。隔离基板桥接器801可为图6A至图6B的隔离基板桥接器601的各种具体实施，其可包括反转基板以及倒装芯片构型以使多个差分信道双向传送数据。图8A示出了隔离基板桥接器801的透视图。图8B示出了隔离基板桥接器801的顶视图。图8C示出了隔离基板桥接器801的底视图。值得注意的是，与图6A至6B的视图相比，隔离基板桥接器801被反转(例如，在图8A至图8C中，导电传输线803出现在基板的底部上，这与图6A至图6B的在基板的顶表面上的情况相反)。
参考图8A至图8C，隔离基板桥接器801可包括设置在隔离基板桥接器801的上表面的两个末端部分上的多个框架导体822。在一些具体实施中，框架导体822可为用于连接到引线框部分的导电板(例如，铜)。另外，隔离基板桥接器801可包括上表面上用于连接到第一半导体管芯的两组两个管芯导体836，以及上表面上用于连接到第二半导体管芯的两组两个管芯导体836。在一些具体实施中，管芯导体836可被视为电容器垫、电容器板和/或电容器导体。管芯导体836可包括基于圆形的结构。此外，隔离基板桥接器801可包括设置在底表面上的两组两个导电传输线803。导电传输线803可具有参考其他附图说明的结构。
在一些具体实施中，隔离基板桥接器801的电容器网络可由管芯导体836和导电传输线803，以及设置在管芯导体836与导电传输线803之间的介电材料形成。
在一些具体实施中，图2至图8的半导体封装可提供若干有益效果，诸如在基板的另一侧上隔离传输线并且使其与其他金属结构隔离(例如，提供相对良好的隔离保护)、结构重心围绕封装中部、基板布局简单(例如，可降低基板材料例如陶瓷的成本)、预镀引线框，和/或没有引线键合。
图9A至图9E示出了半导体封装900的各种视图，该半导体封装具有以倒装芯片构型耦接到无引线基板901的第一半导体管芯902和第二半导体管芯904。图9A示出了半导体封装900的平面图。图9B示出了半导体封装900的侧视图。图9C示出了半导体封装900的成品图。图9D示出了半导体封装900的内部图。图9E示出了半导体封装900的另一个内部图。在倒装芯片构型中，第一半导体管芯902和第二半导体管芯908被倒装，使得其导体(例如，导电垫)朝下定位(沿着竖直方向A1)。半导体封装900可为无引线封装构型。
如图9B至图9E所示，半导体封装900包括基板901。基板901可为参考前图论述的任何隔离基板桥接器。在一些例子中，基板901是厚度为T的介电基板。半导体封装900可包括设置在隔离基板901的顶表面上的第一模制化合物992-1和设置在隔离基板901的底表面上的第二模制化合物992-2。第一模制化合物991-1和第二模制化合物992-2可为环氧树脂模制化合物(EMC)。
半导体封装900可包括设置在半导体封装900的第一末端部分980和第二末端部分981上的多个堆叠990。堆叠990可为陶瓷铜重新分布(RDL)堆叠。每个堆叠990经由迹线991连接到第一半导体管芯902和第二半导体管芯908的不同端子。迹线991可为基于金属的导体，其提供堆叠990与第一半导体管芯902和第二半导体管芯908之间的连通性。迹线991可布置在基板901的顶表面上，其中堆叠990设置在迹线991的末端部分上，并且第一半导体管芯902和第二半导体管芯908设置在迹线991的其他末端部分上。在一些例子中，第一半导体管芯902和第二半导体管芯908经由附接部件910耦接到迹线991。附接部件910可为粘合剂、焊料，或导柱与焊料组合(例如，使得第一半导体管芯902和第二半导体管芯908从基板901的顶表面稍微升高)。每个堆叠990包括至少部分突出在第一模制化合物992-1的外表面上方的焊料端子994。
第一半导体管芯902可与第二半导体管芯908隔离以阻止或基本上阻止第一半导体管芯902与第二半导体管芯908之间的电流流动(例如，没有直接导电路径)，但允许经由第一电容器网络940-1和第二电容器网络940-2交换信息。第一电容器网络940-1可包括由电容器板936、传输线903，和设置在电容器板936与传输线903之间的基板901形成的电容器。因为第二电容器网络940-2包括相同部件，所以出于简明起见而省略第二电容器网络940-2的细节。
参考图9B，第一半导体管芯902和第二半导体管芯908可设置在基板901的顶表面上，其中第一半导体管芯902与第二半导体管芯908间隔距离D3。电容器板936设置在基板901上，使得电容器板936设置在第一半导体管芯902与基板901的顶表面之间。电容器板936可为基于导电金属的材料。电容器板936可朝向第二半导体管芯908延伸。在一些例子中，电容器板936在两个或更多个方向上延伸，并且具有两个或更多个宽度。第一半导体管芯902经由附接部件910耦接到电容器板936。
传输线903可耦接到基板901的底表面，使得传输线903和电容器板936间隔基板901的厚度T。传输线903可为基于导电金属的材料。传输线903可为具有一个或多个放大区段的细长构件。在一些例子中，传输线903可被视为电容器板。第二半导体管芯908可耦接到嵌入导体937和导体延伸部938。导体延伸部938经由附接部件910耦接到第二半导体管芯908。嵌入导体937可在第二半导体管芯908与传输线901之间在方向A2上延伸穿过基板901。在一些例子中，嵌入导体937是填充有金属(例如，填充有铜)的通孔。
通过第一电容器网络940-1，第一半导体管芯902可被配置为与第二半导体管芯908传送数据(反之亦然)。例如，信号可跨越电容器板936发送，调制穿透基板901的厚度T(在方向D1上)，传输跨越传输线903，传输跨越嵌入导体937(在方向D2上)，并且随后传输跨越导体延伸部938到达第二半导体管芯908。在该例子中，隔离厚度为基板901的厚度T。然而，根据另一个实施例，嵌入导体937和/或导体延伸部938可用电容器板936替换，如图34所示，从而使隔离厚度加倍(2T)。
图10示出了半导体封装1000，该半导体封装具有耦接到基板1001的第一半导体管芯1002和第二半导体管芯1008，其中基板1001将电容器板1036用于第二半导体管芯1008。半导体封装1000可类似于图9的半导体封装900，不同的是图9的嵌入导体937用电容器板1036替换。半导体封装1000包括设置在第一模制化合物1092-1与第二模制化合物1092-2之间的基板1001。第一半导体管芯1002和第二半导体管芯1008经由迹线1091连接到堆叠1090，并且堆叠1090具有焊料(堆)端子1094。第一半导体管芯1002被隔离，但经由两个电容器网络电容性地耦接到第二半导体管芯1008。相对于一个电容器网络，第一半导体管芯1002可跨越基板1001(例如，从第一半导体的电容器板1036到传输线1003)发送信号、使该信号跨越传输线1003然后跨越基板1001(例如，从传输线1003到第二半导体的电容器板1036)返回。
图11示出了根据实施例的用于构造图9的半导体封装900和图10的半导体封装1000的处理流程1100。虽然图11被示出为连续有序的操作列表，但应当理解，一些或所有操作可按不同次序或并行或反复发生，或者可在时间上重叠。可执行预组装，诸如焊料印刷、陶瓷面板附接和焊料回流(1102)。可除去第一倒装芯片的助熔剂(1104)，并且可除去第二倒装芯片的助熔剂(1108)。可执行FC焊料回流(1108)以及流和等离子体清洁(1110)。可执行框架辅助陶瓷面板模制和PMC(1115)、底部封装研磨(1114)、无PB焊料印刷(1116)、端子焊料回流(1118)、封装切割分离(1120)，以及测试、打标和TNR(1122)。
在一些一般方面，电容性隔离电路可经由第一导电部件耦接到第一半导体管芯，并且电容性隔离电路可经由第二导电部件耦接到第二半导体管芯。电容性隔离电路可包括电容器和传输线，它们形成至少一个电容性网络以在第一半导体管芯与第二半导体管芯之间传输数据。电容性隔离电路可包括第一导电层、第二导电层，以及设置在第一导电层与第二导电层之间的介电材料。介电材料可包括玻璃材料和陶瓷材料中的一者。电容性隔离电路可包括提供等于或大于0.1mm的绝缘穿透距离的介电厚度。电容性隔离电路可具有大于或等于第一引线框部分与第二引线框部分之间的最小距离的绝缘穿透距离。电容性隔离电路可包括用于在第一半导体管芯与第二半导体管芯之间通信的差分通信信道。该差分通信信道可包括第一导电传输线和第二导电传输线。第一半导体管芯和第二半导体管芯中的每者可包括顶部导电层和底部导电层。电容性隔离电路可形成在顶部导电层和底部导电层外部。
在一些一般方面，电容性隔离电路可包括：第一电容器网络，其具有第一导电层和第二导电层，其中在第一导电层与第二导电层之间设置有介电材料；第二电容器网络，其具有第一导电层和第二导电层，其中在第一导电层与第二导电层之间设置有介电材料；键合引线，其耦接到第一电容器的第一导电层和第二电容器网络的第一导电层。第一电容器的第二导电层可耦接到第一半导体管芯的导体，并且第二电容器网络的第二导电层可耦接到第二半导体管芯的导体。
在一些一般方面，电容性隔离电路可包括隔离基板桥接器，该隔离基板桥接器具有介电材料和至少一个导电传输线，所述导电传输线可通信地耦接第一半导体管芯与第二半导体管芯。所述至少一个导电传输线可包括多个导电传输线。隔离基板桥接器可至少部分地设置在第一半导体管芯顶部并且至少部分地设置在第一半导体管芯顶部，并且所述至少一个导电传输线可设置在介电材料的顶表面上。隔离基板桥接器可设置在第一半导体管芯和第二半导体管芯之间，以及第一引线框部分和第二引线框部分之间。所述至少一个导电传输线可设置在介电材料的底表面上。所述至少一个导电传输线可嵌入在介电材料内。隔离基板桥接器可设置在第一引线部分的至少一部分、第一半导体管芯、第二半导体管芯和第二引线部分的至少一部分的顶部。所述至少一个导电传输线可设置在介电材料的顶表面上。隔离基板桥接器可包括耦接到第一半导体管芯的第一部分、设置在第一半导体管芯与第二半导体管芯之间的区域中的第二部分，以及耦接到第二半导体管芯的第三部分。
在一些一般方面，第一半导体管芯设置为邻近第一引线框部分，第二半导体管芯设置为邻近第二引线框部分，并且电容性电路耦接到第一半导体管芯并耦接到第二半导体管芯。电容性电路可具有大于或等于第一导电部件与第二导电部件之间的最小距离的绝缘穿透距离。
在一些一般方面，电容性隔离电路可包括隔离基板桥接器，该隔离基板桥接器具有介电材料和至少一个导电传输线，所述导电传输线可通信地耦接第一半导体管芯与第二半导体管芯。所述至少一个导电传输线可包括被配置为双向差分信道的多个导电传输线。隔离基板桥接器可至少部分地设置在第一半导体管芯顶部并且至少部分地设置在第一半导体管芯顶部，并且所述至少一个导电传输线可设置在介电材料的顶表面上。隔离基板桥接器可设置在第一半导体管芯和第二半导体管芯之间，以及第一引线框部分和第二引线框部分之间。所述至少一个导电传输线可设置在介电材料的底表面上。所述至少一个导电传输线可嵌入在介电材料内。
在一些一般方面，一种装置可包括设置为邻近第一引线框部分的第一半导体管芯、设置为邻近第二引线框部分的第二半导体管芯，以及设置为邻近第一半导体管芯和第二半导体管芯的隔离基板桥接器。隔离基板桥接器可被配置为支持第一半导体管芯与第二半导体管芯之间的通信。
在一些一般方面，隔离基板桥接器可包括用于在第一半导体管芯与第二半导体管芯之间通信的差分通信信道。该装置可包括设置在第三引线框部分上的第三半导体管芯。第一半导体管芯和第二半导体管芯中的每者可包括顶部导电层和底部导电层。隔离基板桥接器可形成在顶部导电层和底部导电层外部。
本文所述的各种技术的具体实施可在数字电子电路中或在计算机硬件、固件、软件中或在它们的组合中实现。方法的部分也可以通过专用逻辑电路(例如，FPGA(现场可编程门阵列)或ASIC(专用集成电路))执行，并且装置可实现为专用逻辑电路(例如，FPGA(现场可编程门阵列)或ASIC(专用集成电路))。
具体实施可在计算系统中实现，该计算系统包括后端组件(例如，数据服务器)，或者包括中间件组件(例如，应用服务器)，或者包括前端组件(例如，具有图形用户界面或网页浏览器的客户端计算机(用户可通过该客户端计算机与具体实施互动))，或者这样的后端组件、中间件组件或前端组件的任意组合。组件可通过数字数据通信的任何形式或介质(例如，通信网络)进行互连。通信网络的例子包括局域网(LAN)和广域网(WAN)，如互联网。
还可理解的是，当某一层被称为位于另一层或基板上时，其可直接位于另一层或基板上，或者也可存在居间层。还将理解，在元件(例如层、区域或基板)被称为位于另一个元件上或连接至、电连接至、耦接至或电耦接至另一个元件时，元件可直接位于另一个元件上或连接或耦接至另一个元件，或者可存在一个或多个居间元件。相比之下，在元件被称为直接位于另一个元件或层上或直接连接至或直接耦接至另一个元件或层时，不存在居间元件或居间层。尽管在整个具体实施方式中可能未使用术语“直接位于……上”、“直接连接至”或“直接耦接至”，但图中示出为直接位于其上、直接连接或直接耦接的元件可被称为这样的情况。可修正本专利申请的权利要求，以列举说明书中所述或图中所示的示例性关系。
一些具体实施可使用各种半导体加工和/或封装技术来实现。一些实施例可使用与半导体基板相关的各种类型的半导体加工技术来实现，所述半导体基板包括但不限于(例如)硅(Si)、砷化镓(GaAs)、碳化硅(SiC)，等等。
虽然所述具体实施的某些特征已被示出为如本文所述，但本领域的技术人员现将可以想到许多修改、替代、变更和等效方案。因此，应当理解，所附权利要求旨在覆盖落入所述实施例的范围内的所有此类修改和变更。应当理解，所述实施例仅以举例的方式而不是以限制的方式呈现，并且可在形式和细节方面进行各种变更。本文所述的装置和/或方法的任一部分可以以任何组合加以组合，但相互排斥的组合除外。本文所述的实施例可包括所描述的不同实施例的功能、组件和/或特征的各种组合和/或子组合。

Claims (14)

1.一种装置，包括：
第一半导体管芯，其设置为邻近第一引线框部分；
第二半导体管芯，其设置为邻近第二引线框部分；以及
电容性隔离电路，其耦接到所述第一半导体管芯和所述第二半导体管芯，所述电容性隔离电路设置在所述第一半导体管芯和所述第二半导体管芯外部，所述第一半导体管芯、所述第二半导体管芯和所述电容性电路包括在半导体封装的模制物中。
2.根据权利要求1所述的装置，其中所述电容性隔离电路经由第一导电部件耦接到所述第一半导体管芯，并且所述电容性隔离电路经由第二导电部件耦接到所述第二半导体管芯。
3.根据权利要求1所述的装置，其中所述电容性隔离电路包括电容器和传输线，所述电容器和传输线形成至少一个电容性网络以在所述第一半导体管芯与所述第二半导体管芯之间传输数据。
4.根据权利要求1所述的装置，其中所述电容性隔离电路包括第一导电层、第二导电层，以及设置在所述第一导电层与所述第二导电层之间的介电材料。
5.根据权利要求4所述的装置，其中所述介电材料包括玻璃材料和陶瓷材料中的一者。
6.根据权利要求1所述的装置，其中所述电容性隔离电路包括提供等于或大于0.1mm的绝缘穿透距离的介电厚度。
7.根据权利要求1所述的装置，其中所述电容性隔离电路具有大于或等于所述第一引线框部分与所述第二引线框部分之间的最小距离的绝缘穿透距离。
8.根据权利要求1所述的装置，其中所述电容性隔离电路包括用于在所述第一半导体管芯与所述第二半导体管芯之间通信的差分通信信道。
9.根据权利要求1所述的装置，其中所述第一半导体管芯和所述第二半导体管芯中的至少一者包括顶部导电层和底部导电层，其中所述电容性隔离电路形成在所述顶部导电层和所述底部导电层外部。
10.根据权利要求1所述的装置，其中所述电容性隔离电路包括隔离基板桥接器，所述隔离基板桥接器具有介电材料和至少一个导电传输线，所述至少一个导电传输线耦接所述第一半导体管芯与所述第二半导体管芯。
11.一种装置，包括：
第一半导体管芯，其设置为邻近第一引线框部分；
第二半导体管芯，其设置为邻近第二引线框部分；以及
电容性电路，其耦接到所述第一半导体管芯并且耦接到所述第二半导体管芯，所述电容性电路具有大于或等于第一导电部件与第二导电部件之间的最小距离的绝缘穿透距离。
12.根据权利要求11所述的装置，其中所述电容性隔离电路包括隔离基板桥接器，所述隔离基板桥接器具有介电材料和至少一个导电传输线，所述至少一个导电传输线可通信地耦接所述第一半导体管芯与所述第二半导体管芯。
13.根据权利要求12所述的装置，其中所述隔离基板桥接器至少部分地设置在所述第一半导体管芯顶部并且至少部分地设置在所述第二半导体管芯顶部，并且所述至少一个导电传输线设置在所述介电材料的顶表面上。
14.根据权利要求12所述的装置，其中所述第一半导体管芯和所述第二半导体管芯设置在所述隔离基板桥接器顶部，并且所述至少一个导电传输线设置在所述介电材料的底表面上。
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US20170373008A1 (en) 2017-12-28

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