CN115004364A - 具有加强隔离的多芯片封装 - Google Patents

具有加强隔离的多芯片封装 Download PDF

Info

Publication number
CN115004364A
CN115004364A CN202180011225.5A CN202180011225A CN115004364A CN 115004364 A CN115004364 A CN 115004364A CN 202180011225 A CN202180011225 A CN 202180011225A CN 115004364 A CN115004364 A CN 115004364A
Authority
CN
China
Prior art keywords
die
pad
layer
device package
iso
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180011225.5A
Other languages
English (en)
Inventor
V·阿罗拉
金宇灿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN115004364A publication Critical patent/CN115004364A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/06—Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/40—Structural association with built-in electric component, e.g. fuse
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/06—Mounting, supporting or suspending transformers, reactors or choke coils not being of the signal type
    • H01F2027/065—Mounting on printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种多芯片隔离(ISO)装置封装(100)包含：引线框架，其包含引线(114、124)；中介层衬底(122)，其包含顶部铜层(122a)及底部金属层(122c)，其中介电层(122b)在其间。第一IC裸片(110)及第二IC裸片(120)包含：电路(180a、180b)，其包含发射器或接收器；以及第一接合垫(181a)及第二接合垫(181b)，其顶侧朝上附接在所述封装中。叠层变压器(130)附接到定位成横向于所述IC裸片的所述顶部铜层。接合线(141到145)将所述第一接合垫线接合到所述叠层变压器上的第一垫及所述引线或引线端子，且接合线将所述第二接合垫线接合到所述叠层变压器上的第二垫及引线或所述引线端子，且模塑化合物(160)提供囊封。

Description

具有加强隔离的多芯片封装
技术领域
本公开涉及经封装半导体隔离(ISO)装置，且更具体来说，涉及经封装多芯片ISO装置。
背景技术
在用于存在高电压(HV)的应用(例如用于电动机控制)的电路设计中，通常有必要采取措施来降低对电气系统的用户的潜在风险。这些措施传统上包含绝缘、接地及通过建立与HV的电介质分离来隔离危险的HV电平。已知用于在集成电路(IC)裸片之间的通信通道中跨越电介质分离传递信号信息及功率的技术。经封装ISO装置防止直流电(DC)及非所要AC电流在一个裸片上的其输入与另一裸片上的其输出之间传播，同时允许所要AC信号在裸片之间发射。
ISO装置使用第一与第二IC裸片之间的具有高击穿电压及低电流泄漏的隔离势垒来实现此功能。跨隔离势垒存在高电阻路径，但ISO装置仍然可通过电容耦合、电感耦合(变压器隔离)或光学耦合将编码在所要AC信号中的信息跨过隔离势垒从一个IC裸片传递到另一IC裸片。在变压器隔离的情况下，已知磁增强叠层变压器，其包括具有磁场增强磁芯的线圈1(具有N1匝)及线圈2(具有N2匝)，所述磁场增强磁芯包括通常包括铁氧体的顶部磁芯及底部磁芯。
一些市售ISO装置包括具有5kV均方根(RMS)加强隔离额定值的DC/DC转换器，其经设计以将高效的隔离功率提供到需要具有经良好调节的输出电压的偏压电源的隔离电路。此ISO装置包含变压器及DC/DC控制器，其可以高功率转换效率及低电磁干扰(EMI)提供500mW(典型)的隔离功率。
在隔离用于使系统能够正常运作但不一定用作防止电击的势垒的情况下，其常规地被称为功能隔离。在只要绝缘势垒完好无损隔离就能提供足够的防电击保护的情况下，其常规地被称为基本隔离。安全法规要求基本隔离辅以用于冗余的次级隔离势垒，使得即使第一ISO势垒失效，额外势垒也提供电击保护。这常规地被称为双重隔离。为了使包括ISO装置的系统紧凑并节省成本，希望仅具有一个级别的隔离，其具有所需电强度、可靠性及常规地由两个级别的基本隔离提供的冲击保护。这种隔离布置常规地被称为加强隔离。
发明内容
提供本发明内容以依简化形式介绍所公开的概念的简要选择，这些概念在下文包含所提供的附图的具体实施方式中进一步描述。本发明内容不意在限制所主张的标的物的范围。
所公开的方面认识到遵守由例如保险商实验室(UL)1577、国际电工委员会(IEC)60747及UL60950的各种工业标准定义的漏电规则，归因于缺乏经暴露裸片垫而限制常规加强ISO装置封装(例如，包含支持具有IC裸片-IC裸片隔离的DC/DC转换器的两个IC裸片)的热耗散能力，且因此阻碍此类ISO装置封装支持高输出功率(例如，>1W)应用。ISO装置封装的大小也被常规地扩大以满足漏电要求。
所公开的方面包含通过添加经隔离中介层衬底来解决具有加强隔离封装的常规ISO装置封装的上述问题的解决方案，这种及中介层衬底包含作为都可为铜的顶部与底部金属层之间的导热介电层。所公开的ISO装置封装包含含有发射器或接收器的第一IC裸片及含有发射器或接收器的第二IC裸片，其中叠层变压器提供耦合在相应IC裸片上的发射器及接收器之间的加强隔离。
所公开的方面包含一种多芯片ISO装置封装，所述多芯片ISO装置封装包含：引线框架，其包含引线；中介层衬底，其包含顶部铜层及底部金属层，介电层在中间。第一IC裸片及第二IC裸片都包含含有发射器或接收器的电路，且所述第一IC裸片上的第一接合垫及所述第二IC裸片上的第二接合垫顶侧朝上附接在所述封装中。叠层变压器附接到定位成横向于所述IC裸片的所述顶部铜层。接合线将所述第一接合垫线接合到所述叠层变压器上的第一垫及所述引线或引线端子的第一群组，且接合线将所述第二接合垫线接合到所述叠层变压器上的第二垫及所述引线或所述引线端子的第二群组，且模塑化合物为所述ISO装置封装提供囊封。
附图说明
现在将参考附图，这些附图不一定按比例绘制，其中：
图1是展示实例多芯片ISO装置封装的顶部透视图，其包含：第一IC裸片，其包含包括发射器或接收器的电路；及第二IC裸片，其包含包括发射器或接收器的电路，使得封装提供至少一个通信通道；及叠层变压器，其安装到中介层衬底，所述中介层衬底上具有耦合在相应IC裸片的发射器及接收器之间的叠层变压器，这提供加强隔离。
图2A是描绘多芯片ISO装置封装的俯视视图，其包含安装到中介层衬底的叠层变压器。提供在此图的右侧的此ISO装置封装的仰视图展示中介层衬底的介电层上的底部金属层。
图2B是沿图2A中展示的切割线A-A截取的图2A中展示的ISO装置封装的侧横截面视图，其中顶部铜层是图案化层，其展示顶部铜层上的第一IC裸片，所述第一IC裸片具有线接合到位于中介层衬底上的叠层变压器的叠层电介质上的接合垫的接合垫。
图2C是沿图2A中展示的切割线B-B截取的图2A中展示的ISO装置封装的侧横截面视图，其展示裸片垫上的第二IC裸片，所述第二IC裸片具有线接合到位于中介层衬底的顶部铜层上的叠层变压器的叠层电介质上的接合垫的接合垫。
图2D是描绘实例多芯片ISO装置封装的俯视图，其包含安装到中介层衬底上的叠层变压器。在这种布置中，顶部铜层是图案化层，且中介层衬底本质上占据封装的整个区域，使得叠层变压器以及第一IC裸片及第二IC裸片都在中介层衬底的顶部铜层的区域上。
图2E是描绘实例多芯片ISO装置封装的俯视图，其包含安装到中介层衬底上的叠层变压器。在这种布置中，中介层衬底仅占据封装的足够区域，使得叠层变压器位于其上，且存在用于第一IC裸片及第二IC裸片的引线框架的分开的裸片垫。
图3是展示根据实例方面的用于形成多芯片ISO装置封装的实例方法中的步骤的流程图，所述多芯片ISO装置封装包含安装到中介层衬底上的叠层变压器。
具体实施方式
参考附图描述实例方面，其中类似参考数字用于表示类似或等效元件。所说明的动作或事件的顺序不应被认为是限制性的，因为一些动作或事件可以不同顺序发生及/或与其它动作或事件同时发生。此外，可不需要一些所说明的动作或事件来实施根据本公开的方法。
此外，如本文使用的术语“耦合到”或“与…耦合”(及类似者)在不进一步限定的情况下意在描述间接或直接电连接。因此，如果第一装置“耦合”到第二装置，那么连接可通过直接电连接(其中只有路径中存在寄生)或通过经由包含其它装置及连接的中介项的间接电连接。对于间接耦合，中介项通常不修改信号的信息，但可调整其电流电平、电压电平及/或功率电平。
所公开的方面认识到中介层衬底(例如具有拥有相当好的热导率的陶瓷芯介电层(例如氧化铝或氮化铝)的直接接合铜(DBC)衬底)的使用以至少2种方式促进多芯片ISO装置封装的性能。陶瓷芯材料在封装内部及外部提供ISO装置封装的HV及低电压节点之间的电隔离。中介层衬底的通常较厚的顶部铜层与中介层衬底的介电层通常包括的陶瓷材料的相对较高热导率组合帮助增强热耗散，这实现更高功率多芯片ISO装置封装解决方案。已知的多芯片ISO装置封装解决方案(例如经暴露裸片附接垫(DAP)小外形集成电路(SOIC)封装)是非隔离的，且通常也违反漏电要求。
所公开的ISO装置大体上提供具有经暴露热垫的最小面积封装，其满足加强隔离要求。中介层衬底的底部厚铜层提供增强的热传递能力。底部铜层还使得能够附接散热器，所述散热器将归因于芯陶瓷材料的介电特性而与封装内部的第一IC裸片及第二IC裸片组件隔离。
图1是展示实例多芯片ISO装置封装100的顶部透视图，其包含：第一IC裸片110，其包含包括发射器或接收器的电路；及第二IC裸片120，其包含包括发射器或接收器的电路，使得封装提供至少一个通信通道。ISO装置封装100还包括安装到中介层衬底122(例如，DBC衬底，例如针对其介电层122b，包含陶瓷，例如氧化铝(Al2O3)、氮化铝(AlN)或氮化硅)的叠层变压器130，所述中介层衬底包含顶部铜层122a及底部金属层122c，其中介电层122b位于这些金属层之间。
叠层变压器130位于顶部铜层122a上，其中变压器130耦合在相应IC裸片110、120的发射器与接收器之间，这提供加强隔离。叠层变压器130通常支持在一分钟测试时间内的至少1kV的均方根(RMS)击穿电压，从而通常提供至少2.5kV到5kV的击穿电压。UCC12050根据UL1577进行一分钟的击穿测试，UL1577是隔离装置的最流行的标准之一。
中介层衬底可包括除DBC衬底之外的衬底，例如也可用作中介层的绝缘金属衬底(IMS)。此项技术中已知的IMS由金属底板(通常使用铝，因为其低成本及密度)组成，所述金属底板由薄介电层(通常是环氧基层，通常是FR-4)及顶部铜层(通常约35μm到超过200μm厚)覆盖。基于FR-4的电介质通常提供为薄的(约100μm厚)，因为与DBC衬底中使用的陶瓷相比，其具有更低热导率。作为另一替代方案，中介层衬底还可包含活性金属钎焊衬底(AMB)，其中使用锡膏将金属箔焊接到陶瓷。与DBC相比，AMB通常是更高成本的布置，但从技术上来说，AMB与DBC具有本质上相同的配置。
在ISO装置封装操作期间通常是ISO装置封装中的最热组件的叠层变压器130附接到中介层衬底122的顶部铜层122a使得由叠层变压器130产生的热能够垂直地传导出去。ISO装置封装100的热传递路径首先通过顶部铜层122a，接着通过介电层122b，且接着最后从底部金属层122c离开到用作ISO装置封装100的散热器的环境。
如上文提及，介电层122b可包括陶瓷层，其可在20℃下提供至少20W/m·K的热导率。例如，氧化铝在20℃下具有28到35W/m·K的热导率，氮化铝在20℃下具有约70到180W/m·K的热导率，氮化硅在20℃下具有约30W/m·K的热导率。
例如，针对图1中的ISO装置封装100展示中介层衬底122，所述中介层衬底122为L形以容纳叠层变压器130及第二IC裸片120。在此实例中，第一IC裸片110横向于中介层衬底122的区域，且代替地位于横向于中介层衬底122的区域的引线框架的裸片垫112上。
在一些所公开的布置中，中介层衬底122还可本质上占据ISO装置封装的整个区域，使得叠层变压器130以及第一及第二IC裸片110、120都在中介层衬底122的图案化顶部铜层122a部分上。在下文描述的图2D中展示此布置。在另一布置中，中介层衬底122仅占据封装的足够区域，使得叠层变压器130位于其上，且存在用于第一IC裸片110及第二IC裸片120的引线框架的分开裸片垫。在下文描述的图2E中展示此另一布置。
底部金属层122c可包括铜或铝。在裸片垫112上展示包含电路180a及接合垫181a的第一IC裸片110，而在中介层衬底122的顶部铜层122a上展示包含电路180b及接合垫181b的第二IC裸片120。此项技术中已知的IC裸片110、120上的电路180a、180b包括形成于半导体衬底中(例如在块状衬底上的外延层中)的电路元件(包含晶体管，且通常包含二极管、电阻器、电容器等)，所述电路元件经配置在一起以通常各自实现至少一个发射器或接收器，其中IC裸片中的至少一者提供至少一个额外电路功能。实例额外电路功能包含模拟(例如，放大器或功率转换器)、射频(RF)、数字或非易失性存储器功能。
顶部铜层122a经蚀刻或以其它方式图案化以允许将第二IC裸片120与叠层变压器130电隔离。在图1中未展示的第一及第二IC裸片110、120都在叠层变压器130上的情况下，顶部铜层122a经图案化以将第一及第二IC裸片110、120彼此隔离，并提供与叠层变压器130的隔离。
在ISO装置封装100的一个侧上的引线被展示为124，且在ISO装置封装100的与引线124相对的另一侧上展示引线114。在一些引线124与第一IC裸片110上的一些接合垫181a之间存在展示为141的接合线，且在第一IC裸片110上的一些接合垫181a与叠层变压器130的叠层电介质130b上的一些接合垫130g之间存在接合线142。如此项技术中已知，展示为叠层电介质130b的物体通常包括叠层衬底，所述叠层衬底具有多个金属层(层级)，其在相应金属层之间具有穿过电介质材料的通孔连接以将所有信号带到叠层衬底的最上表面。因此，IC裸片110、120与叠层变压器130之间的接合线142、143通常将形成与叠层衬底的最上铜层的连接件，其连接到叠层变压器130的顶部芯(展示为线圈2)或底部芯(展示为线圈1)。
因此，在叠层变压器130上的一些接合垫130g与第二IC裸片120上的一些接合垫181b之间存在接合线143，且在第二IC裸片120上的一些接合垫181b与一些引线114之间存在一些接合线144。在叠层变压器130上的一些接合垫130g与一些引线114之间也存在接合线145。还展示模塑化合物160。
尽管中介层衬底122在图1中展示为跨越ISO装置封装100的足以容纳叠层变压器130及展示为第二IC裸片120的IC裸片中的一者的区域，但情况不必如此，例如在引线框架包含用于安装第一IC裸片110及第二IC裸片120的第一裸片垫及第二裸片垫的情况下。因此，中介层衬底122的顶部铜层122a可在其上具有两个IC裸片及叠层变压器130中的任一者，IC裸片110、120及叠层变压器130中的两者，或仅具有叠层变压器130。在这种情况下，顶部铜层122a经图案化，IC裸片110、120都可安装在中介层衬底122的介电层122b上，或一个或两个IC裸片110、120可具有介电层122b上的顶部铜层122a的分开区域以提供装置隔离。
应注意，在中介层衬底122包括DBC衬底的情况下，因为DBC衬底通常比引线框架布置更昂贵，所以通常最好保持DBC衬底的面积尽可能小。其上具有所有组件(叠层变压器130、第一IC裸片110及第二IC裸片120)的更大面积DBC衬底的优点是热效益。具有大面积的顶部铜层122a通过利用更大的面积来帮助热扩散。因此，针对ISO装置封装100，存在成本与热性能之间的折衷。
尽管图1中展示的多芯片ISO装置封装100仅包含2个IC裸片110、120，但当需要时，所公开的多芯片ISO装置封装可具有多于2个IC裸片。例如，在一个所公开的多芯片ISO装置封装中，可包含3个IC裸片而不是仅包含2个IC裸片。因此，所公开的多芯片ISO装置封装提供取决于终端应用的可伸缩性。
所公开的多芯片IC装置封装通常可用于任何电力电子电路拓扑，而不仅用于DC-DC转换器。除DC-DC转换器之外的实例还可包含数字隔离器、隔离式反激控制器、隔离式模/数转换器(ADC)、隔离式栅极驱动器及隔离式放大器。
图2A是描绘实例多芯片ISO装置封装200的俯视图，其包含安装到中介层衬底122的叠层变压器130以及第一及第二IC裸片110、120。叠层变压器130通常包括各自具有磁场增强磁芯的线圈1(具有N1匝)及线圈2(具有N2匝)，所述磁场增强磁芯包括通过展示为130b的叠层电介质彼此隔开的顶部磁芯130a及底部磁芯130c(通常都包括铁氧体)。提供在此图的右侧的此ISO装置封装200的仰视图展示中介层衬底122b的介电层122b上的底部金属层122c。在此布置中，类似于其中仅展示为第二IC裸片120的IC裸片中的一者及叠层变压器130位于中介层衬底122上的图1，中介层衬底122再次具有足够大的面积以容纳叠层变压器130以及现在展示为第一IC裸片110的IC裸片中的一者，而第二IC裸片120展示为横向于中介层衬底122的区域，而不是在引线框架的裸片垫112上。
图2B是沿图2A中展示的切割线A-A截取的图2A中展示的ISO装置封装200的侧横截面视图，其中顶部铜层122a是图案化层。图2B展示中介层衬底的顶部铜层122a的一部分上的第一IC裸片110，所述第一IC裸片110具有通过接合线142线接合到叠层变压器130的叠层电介质130b的接合垫130g的接合垫181a，所述叠层变压器130也在顶部铜层122a的另一部分上。展示模塑化合物160，其中中介层衬底122的底部金属层122c展示为从ISO装置封装200暴露以为叠层变压器130提供增强冷却。
图2C是沿图2A中展示的切割线B-B截取的图2A中展示的ISO装置封装200的侧横截面视图，其展示裸片垫112上的第二IC裸片120。第二IC裸片120具有线接合到叠层变压器130的叠层电介质130b上的接合垫130g的接合垫181b，其中叠层变压器130位于中介层衬底122的顶部铜层122a上。可看到第二IC裸片120横向于中介层衬底122，而不是在引线框架的裸片垫112上。
可如图2B中那样再次看到中介层衬底122的底部金属层122c从ISO装置封装200的底侧暴露。所公开的布置可自由地选择ISO装置封装的冷却侧。例如，如果终端应用需要顶侧冷却封装，那么通过翻转图2C中展示的ISO装置封装200的视图，也可在ISO装置封装的顶侧上暴露中介层衬底的背侧(例如用于DBC衬底的铜)以用于顶侧散热器附接。
图2D是描绘实例多芯片ISO装置封装240的俯视图，其包含安装到展示为122l的中介层衬底的叠层变压器130。在此布置中，中介层衬底122l本质上占据ISO装置封装240的整个区域，使得叠层变压器130以及第一IC裸片110及第二IC 120都位于中介层衬底122l的顶部铜层122A的分开(图案化)区域上。
图2E是描绘实例多芯片ISO装置封装260的俯视图，其包含安装到展示为122s的中介层衬底上的叠层变压器130。在此布置中，中介层衬底122s仅占据ISO装置封装260的足够区域，使得叠层变压器130位于其上，且引线框架为相应IC裸片提供分开的裸片垫，其中为第一IC裸片110提供裸片垫112a且为第二IC裸片120提供另一裸片垫112b。
图3是展示根据实例方面的用于形成多芯片ISO装置封装的实例方法300中的步骤的流程图，所述多芯片ISO装置封装包含安装到隔离中介层衬底上的叠层变压器。展示为“原材料准备”的步骤301包括提供第一IC裸片110、第二IC裸片120、叠层变压器130、中介层衬底122及包含引线或引线端子(图1中展示的引线114、124)的引线框架，所述引线框架任选地包含一或多个裸片垫。取决于封装设计，如上文描述，引线框架可包含0、1或2个裸片垫，其中IC裸片可位于裸片垫上，或直接位于中介层衬底的顶部铜层上，其中顶部铜层任选地是图案化层。在引线框架不提供裸片垫(仅引线或引线端子)的情况下，中介层衬底可具有足以容纳ISO装置封装的所有组件的面积，例如上文描述的图2D中展示。
步骤302包括将引线框架(通常为引线框架面板/阵列)安装到夹具上，且接着拾取引线框架的引线或引线端子内部的中介层衬底并将其放置到夹具上。夹具可提供引线框架与中介层衬底之间的精确对准以使得能够将中介层衬底放置在引线框架中的开口内，且引线框架上的拉杆可用于将中介层衬底物理连接到引线框架面板/阵列。这种物理连接可通过使用粘合材料连同回流步骤或使用机械夹紧来实现。步骤303包括在中介层衬底的顶部铜层上及任选地在一或多个裸片垫上施配粘合剂。如上文提及，粘合剂通常具有至少2W/m·K@20℃，例如至少20W/m·K@20℃的热导率。
步骤304包括拾取叠层变压器并将其放置在中介层衬底的顶部铜层上的粘合剂上，且当顶部铜层是图案化层时将第一IC裸片及第二IC裸片放置在中介层衬底的顶部铜层上的粘合剂上，或当引线框架包含裸片垫时将第一IC裸片及第二IC裸片放置在裸片垫上。步骤305包括固化或回流工艺以使粘合剂固化，例如在约200℃的温度下固化约一分钟。步骤306包括线接合。步骤307包括模制工艺以形成模塑化合物，且步骤308包括封装修整及成形，包含切割引线框架的拉杆。
所公开的方面可集成到各种组装流程中以形成各种不同多芯片ISO封装及相关产品。组合件可包括包含多个堆叠半导体裸片的配置。可使用各种封装衬底。半导体裸片可包含在其中的各种元件及/或在其上的层，包含势垒层、介电层、装置结构、有源元件及无源元件，包含源极区、漏极区、位线、基极、发射极、集电极、导电线、导电通孔等。此外，半导体裸片可由包含双极、绝缘栅双极晶体管(IGBT)、CMOS、BiCMOS及MEMS的各种工艺形成。
本公开涉及的领域所属的技术人员将理解，在所主张发明的范围内，所公开的方面的许多变化是可能的，且在不脱离本公开的范围的情况下，可对上述方面进行进一步添加、删除、替换及修改。

Claims (20)

1.一种多芯片隔离(ISO)装置封装，其包括：
引线框架，其包含引线或引线端子，
中介层衬底，其包括顶部铜层及底部金属层，其中介电层位于所述顶部铜层与所述底部金属层之间；
第一IC裸片，其包括包含发射器或接收器的电路及顶侧朝上附接在所述ISO装置封装中的第一接合垫；
第二IC裸片，其包括包含发射器或接收器的电路及顶侧朝上附接在所述ISO装置封装中的第二接合垫；
叠层变压器，其附接到定位成横向于所述第一IC裸片及所述第二IC裸片的所述顶部铜层；
接合线，其将所述第一IC裸片的所述第一接合垫中的相应者线接合到所述叠层变压器上的第一垫及所述引线或所述引线端子的第一群组；
接合线，其将所述第二IC裸片的所述第二接合垫中的相应者线接合到所述叠层变压器上的第二垫及所述引线或所述引线端子的第二群组；
模塑化合物，其为所述ISO装置封装提供囊封，其中所述底部金属层至少在所述叠层变压器下方从所述ISO装置封装暴露。
2.根据权利要求1所述的ISO装置封装，其中所述中介层衬底包括直接接合铜(DBC)衬底，使得所述底部金属层包括铜。
3.根据权利要求1所述的多芯片封装，其中用于所述第一IC裸片或用于所述第二IC裸片的所述电路进一步包括DC/DC转换器。
4.根据权利要求1所述的多芯片封装，其中所述叠层变压器支持至少1kV的均方根(RMS)击穿电压。
5.根据权利要求1所述的多芯片封装，其中所述顶部铜层包括图案化层。
6.根据权利要求1所述的多芯片封装，其中所述介电层包括在20℃下提供至少20W/m·K的热导率的陶瓷层。
7.根据权利要求1所述的多芯片封装，其中所述底部金属层从所述ISO装置封装的底侧或顶侧暴露。
8.根据权利要求1所述的多芯片封装，其中所述引线框架包含至少一个裸片垫，且其中所述第一IC裸片或所述第二IC裸片顶侧朝上附接到所述裸片垫上。
9.根据权利要求1所述的多芯片封装，其中所述引线框架包含第一裸片垫及第二裸片垫，且其中所述第一IC裸片位于所述第一裸片垫上，且所述第二IC裸片位于所述第二裸片垫上。
10.一种用于形成多芯片隔离(ISO)装置封装的方法，其包括：
提供包含含有发射器或接收器的电路及第一接合垫的第一IC裸片、包含含有发射器或接收器的电路及第二接合垫的第二IC裸片、叠层变压器、包括顶部铜层及底部金属层以及定位于所述顶部铜层与所述底部金属层之间的介电层的中介层衬底以及包含多个引线或引线端子的引线框架；
将所述引线框架安装到夹具上，且接着拾取所述引线框架的所述引线或引线端子内部的所述中介层并将其放置到所述夹具上；
将粘合剂施配到至少所述顶部铜层上；
拾取所述叠层变压器、所述第一IC裸片及所述第二IC裸片并将其放置到所述粘合剂上；
使所述粘合剂固化；
将所述第一IC裸片的所述第一接合垫中的相应者线接合到所述叠层变压器上的第一垫及所述引线或所述引线端子的第一群组，且将所述第二IC裸片的所述第二接合垫中的相应者线接合到所述叠层变压器上的第二垫及所述引线或所述引线端子的第二群组，及
进行模制处理以形成囊封所述ISO装置封装的模塑化合物，其中所述底部金属层至少在所述叠层变压器下方从所述ISO装置封装暴露。
11.根据权利要求10所述的方法，其中所述施配包括当所述顶部铜层是图案化层时将粘合剂定位于所述顶部铜层上，或当所述引线框架包含所述裸片垫时将粘合剂定位于至少一个裸片垫上。
12.根据权利要求10所述的方法，其中所述粘合剂在20℃下具有至少20W/m·K的热导率。
13.根据权利要求10所述的方法，其中所述中介层衬底包括直接接合铜(DBC)衬底，使得所述底部金属层包括铜。
14.根据权利要求10所述的方法，其中所述顶部铜层是图案化层。
15.根据权利要求10所述的方法，其中所述叠层变压器支持至少1kV的均方根(RMS)击穿电压。
16.根据权利要求10所述的方法，其中所述介电层包括在20℃下提供至少20W/m·K的热导率的陶瓷层。
17.根据权利要求10所述的方法，其中所述引线框架包括至少一个裸片垫，且其中所述拾取及放置包括将所述第一IC裸片或所述第二IC裸片顶侧朝上放置到所述裸片垫上。
18.根据权利要求10所述的方法，其中所述引线框架包含第一裸片垫及第二裸片垫，且其中所述拾取及放置包括将所述第一IC裸片放置于所述第一裸片垫上，且将所述第二IC裸片放置于所述第二裸片垫上。
19.根据权利要求10所述的方法，其中所述引线框架包括引线框架面板。
20.根据权利要求10所述的方法，其中用于所述第一IC裸片或用于所述第二IC裸片的所述电路进一步包括DC/DC转换器。
CN202180011225.5A 2020-03-24 2021-03-23 具有加强隔离的多芯片封装 Pending CN115004364A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/828,298 US11329025B2 (en) 2020-03-24 2020-03-24 Multi-chip package with reinforced isolation
US16/828,298 2020-03-24
PCT/US2021/023563 WO2021195013A1 (en) 2020-03-24 2021-03-23 Multi-chip package with reinforced isolation

Publications (1)

Publication Number Publication Date
CN115004364A true CN115004364A (zh) 2022-09-02

Family

ID=77857524

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180011225.5A Pending CN115004364A (zh) 2020-03-24 2021-03-23 具有加强隔离的多芯片封装

Country Status (4)

Country Link
US (2) US11329025B2 (zh)
EP (1) EP4128341A4 (zh)
CN (1) CN115004364A (zh)
WO (1) WO2021195013A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3127841A1 (fr) * 2021-10-01 2023-04-07 Stmicroelectronics (Tours) Sas Transformateur dans un substrat de boitier
US11929311B2 (en) * 2021-10-15 2024-03-12 Texas Instruments Incorporated Isolated semiconductor package with HV isolator on block
WO2024069401A1 (en) * 2022-09-28 2024-04-04 Delphi Technologies Ip Limited Systems and methods for three channel galvanic isolator for inverter for electric vehicle

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100993579B1 (ko) * 2002-04-30 2010-11-10 르네사스 일렉트로닉스 가부시키가이샤 반도체장치 및 전자 장치
US7064442B1 (en) * 2003-07-02 2006-06-20 Analog Devices, Inc. Integrated circuit package device
DE102007012154B4 (de) * 2007-03-12 2014-05-08 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US7468547B2 (en) * 2007-05-11 2008-12-23 Intersil Americas Inc. RF-coupled digital isolator
JP5332374B2 (ja) * 2008-07-25 2013-11-06 サンケン電気株式会社 半導体装置
JP2010244977A (ja) * 2009-04-09 2010-10-28 Renesas Electronics Corp 半導体装置
KR101101490B1 (ko) * 2009-11-24 2012-01-03 삼성전기주식회사 차폐 기능을 갖는 무선 장치
US20120199960A1 (en) 2011-02-07 2012-08-09 Texas Instruments Incorporated Wire bonding for interconnection between interposer and flip chip die
JP6114184B2 (ja) * 2011-04-04 2017-04-12 ローム株式会社 半導体装置および半導体装置の製造方法
DE102011100487A1 (de) * 2011-05-04 2012-11-08 Micronas Gmbh Integriertes passives Bauelement
US9035435B2 (en) * 2012-11-14 2015-05-19 Power Integrations, Inc. Magnetically coupled galvanically isolated communication using lead frame
US8963622B2 (en) * 2013-03-10 2015-02-24 Microchip Technology Incorporated Method and apparatus for generating regulated isolation supply voltage
US9250403B2 (en) * 2013-04-26 2016-02-02 Oracle International Corporation Hybrid-integrated photonic chip package with an interposer
US20150004902A1 (en) * 2013-06-28 2015-01-01 John M. Pigott Die-to-die inductive communication devices and methods
US10297572B2 (en) * 2014-10-06 2019-05-21 Mc10, Inc. Discrete flexible interconnects for modules of integrated circuits
JP6522402B2 (ja) * 2015-04-16 2019-05-29 ローム株式会社 半導体装置
US9899282B2 (en) * 2015-07-24 2018-02-20 Infineon Technologies Americas Corp. Robust high performance semiconductor package
US10497506B2 (en) * 2015-12-18 2019-12-03 Texas Instruments Incorporated Methods and apparatus for isolation barrier with integrated magnetics for high power modules
US9837923B2 (en) 2016-04-27 2017-12-05 General Electric Company Integrated power converter and transformer
US10056319B2 (en) * 2016-04-29 2018-08-21 Delta Electronics, Inc. Power module package having patterned insulation metal substrate
US9905439B2 (en) * 2016-04-29 2018-02-27 Delta Electronics, Inc. Power module package having patterned insulation metal substrate
US10439065B2 (en) 2017-10-11 2019-10-08 Texas Instruments Incorporated Inverted leads for packaged isolation devices
US20190109061A1 (en) * 2017-10-11 2019-04-11 Texas Instruments Incorporated Edge Bend for Isolation Packages
US11315891B2 (en) 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant
US10714418B2 (en) * 2018-03-26 2020-07-14 Texas Instruments Incorporated Electronic device having inverted lead pins
US10559524B1 (en) * 2018-09-17 2020-02-11 Texas Instruments Incorporated 2-step die attach for reduced pedestal size of laminate component packages
US11482477B2 (en) * 2018-12-31 2022-10-25 Texas Instruments Incorporated Packaged electronic device with suspended magnetic subassembly
US20200248914A1 (en) * 2019-01-31 2020-08-06 Johnson Controls Technology Company Printed circuit board of an hvac controller
US10854538B2 (en) * 2019-02-12 2020-12-01 Texas Instruments Incorporated Microelectronic device with floating pads
US11616006B2 (en) * 2019-02-27 2023-03-28 Semiconductor Components Industries, Llc Semiconductor package with heatsink
US11258270B2 (en) * 2019-06-28 2022-02-22 Alpha And Omega Semiconductor (Cayman) Ltd. Super-fast transient response (STR) AC/DC converter for high power density charging application
US20210193586A1 (en) * 2019-12-18 2021-06-24 Bae Systems Information And Electronic Systems Integration Inc. Cryptographic system-in-package (csip)
JP2022046251A (ja) * 2020-09-10 2022-03-23 ローム株式会社 半導体装置
JP2022055599A (ja) * 2020-09-29 2022-04-08 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
US20220271008A1 (en) 2022-08-25
US20210305207A1 (en) 2021-09-30
WO2021195013A1 (en) 2021-09-30
EP4128341A4 (en) 2023-09-13
EP4128341A1 (en) 2023-02-08
US11908834B2 (en) 2024-02-20
US11329025B2 (en) 2022-05-10

Similar Documents

Publication Publication Date Title
JP6300978B2 (ja) 電力用半導体モジュール
US11908834B2 (en) Multi-chip package with reinforced isolation
US9001524B1 (en) Switch-mode power conversion IC package with wrap-around magnetic structure
WO2011145219A1 (ja) パワー半導体モジュール
US10784213B2 (en) Power device package
CN108735689B (zh) 具有空间限制的导热安装体的芯片模块
EP3157053A1 (en) Power module
US12015019B2 (en) Stacked die multichip module package
KR20220162165A (ko) 수동 디바이스들을 포함하는 멀티 레벨 rf(radio frequency) 집적 회로 컴포넌트들
KR102490612B1 (ko) 전력용 반도체 모듈
US10888036B1 (en) Thermal management assemblies for electronic assemblies circumferentially mounted on a motor
US11153996B2 (en) Thermal management assemblies for electronic assemblies mounted on a motor end
US20230129232A1 (en) Multi-chip module leadless package
JP2023530301A (ja) リードフレームコンデンサ
CN108323211B (zh) 功率器件封装
CN111244061A (zh) 氮化镓设备的封装结构
EP4258337A1 (en) Insulated board and power converter
KR102464477B1 (ko) 양면 냉각 파워 모듈 및 이의 제조방법
US11929311B2 (en) Isolated semiconductor package with HV isolator on block
US11870341B2 (en) Isolated power converter package with molded transformer
US11791249B2 (en) Thermally enhanced isolated power converter package
US11716117B2 (en) Circuit support structure with integrated isolation circuitry
US20230335509A1 (en) Power module package with magnetic mold compound
US20240222237A1 (en) Isolated semiconductor package with hv isolator on block
KR20180005389A (ko) 후막인쇄기법을 이용한 절연기판

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination