CN110783315A - 具有电磁屏蔽结构的半导体封装及其制造方法 - Google Patents

具有电磁屏蔽结构的半导体封装及其制造方法 Download PDF

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Publication number
CN110783315A
CN110783315A CN201910674961.3A CN201910674961A CN110783315A CN 110783315 A CN110783315 A CN 110783315A CN 201910674961 A CN201910674961 A CN 201910674961A CN 110783315 A CN110783315 A CN 110783315A
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semiconductor package
conductive layer
shielding structure
carrier substrate
upper conductive
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CN201910674961.3A
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J·赫格尔
O·哈泽
T·基斯特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种具有双侧冷却结构的半导体封装，其包括：上导电元件，该上导电元件具有向外露出的金属表面；下承载衬底，其具有上导电层、带有向外露出的表面的下导电层和电绝缘层，其中，该电绝缘层布置在上导电层与下导电层之间；第一导电间距保持件，其布置在上导电元件与上导电层之间；至少一个功率半导体芯片，其布置在上导电元件与上导电层之间；第二导电间距保持件，其布置在上导电元件与功率半导体芯片之间；屏蔽结构，其构造用于电磁屏蔽半导体封装的线路。

Description

具有电磁屏蔽结构的半导体封装及其制造方法
技术领域
本发明涉及一种具有双侧冷却结构的半导体封装，该半导体封装具有电磁屏蔽结构。本发明还涉及一种用于具有双侧冷却结构和电磁屏蔽结构的半导体封装的制造方法。
背景技术
(例如在机动车的电驱动中)对高电流电路性能的要求越来越高，因此需要进一步开发和改善在这些电路中使用的半导体封装。这些电路例如可以具有逆变器，该逆变器将电池电压转换为用于驱动电机的交流电压。这种逆变器可以通过半导体封装中的合适的电路来实现，其中，对于逆变器的性能来说决定性的是，在半导体封装中实现充分的冷却、尽可能低的阻抗、尽可能低的漏感等。此外，可能需要将半导体封装中的线路与其周围环境进行电磁屏蔽，以便例如确保半导体封装中实现的电路功能良好。通过改善半导体封装或通过改善用于制造这种半导体封装的方法，可以进一步提高这种逆变器的性能。
发明内容
通过独立权利要求的特征解决本发明所基于的任务。本发明的有利的构型和扩展在从属权利要求中说明。
具体示例涉及一种具有双侧冷却结构的半导体封装，该半导体封装包括：上导电元件，其具有向外露出的金属表面；下承载衬底，其具有上导电层、下导电层以及布置在上导电层与下导电层之间的电绝缘层，其中，该下导电层具有向外露出的表面；第一导电间距保持件，其布置在上导电元件与上导电层之间；至少一个功率半导体芯片，其布置在上导电元件与上导电层之间；第二导电间距保持件，其布置在上导电元件与功率半导体芯片之间；屏蔽结构，其构造用于电磁屏蔽半导体封装的线路。
具体示例涉及一种用于制造具有双侧冷却结构的半导体封装的方法，该方法包括：提供下承载衬底，该下承载衬底具有上导电层、下导电层以及布置在上导电层与下导电层之间的电绝缘层；将第一导电间距保持件安置在下承载衬底的上导电层上；将至少一个功率半导体芯片安置在下承载衬底的上导电层上；将第二导电间距保持件安置在功率半导体芯片上；将上导电元件与下承载衬底相对置地安置在所述间距保持件上；如此构造屏蔽结构，使得半导体封装的线路由屏蔽结构电磁屏蔽。
附图说明
所附的附图示出示例并且用于结合说明书来阐释本发明的基本特征。附图的元素不一定必须按比例缩放。相同的附图标记可以表示相应的、相似的或相同的部分。
图1由子图1A和1B组成，在子图1A中示出具有双侧冷却结构的半导体封装的侧视图，子图1B示出具有双侧冷却结构的另一半导体封装的侧视图；
图2示出具有双侧冷却结构的半导体封装的立体视图，该半导体封装还包括封装体；
图3由子图3A至3D组成，在子图3A中示出另一半导体封装的下承载衬底的立体视图，在子图3B中，上冷却结构以立体视图示出，在子图3C中，组装的半导体封装以立体视图示出，在子图3D中示出半导体封装的侧视图；
图4示出用于制造半导体封装的方法的流程图；
图5示出具有屏蔽结构的半导体封装的示例，该屏蔽结构布置在两个信号线路之间。
具体实施方式
在本说明书中，术语“耦合”、“电耦合”和/或“电连接”并不表示元件必须直接耦合；在“耦合的”或“电耦合的”元件之间可以设有中间件(例如焊料层)。
图1A示出根据本发明的具有双侧冷却结构的半导体封装100。在此，“双侧冷却结构”表示半导体封装100具有上导电元件110和下承载衬底120，所述上导电元件和下承载衬底可以分别用作半导体封装100的冷却结构。半导体封装100还具有第一导电间距保持件130、至少一个功率半导体芯片140和第二导电间距保持件150。第二导电间距保持件150布置在上导电元件110与功率半导体芯片140之间。
下承载衬底120具有上导电层121、下导电层123以及布置在上导电层121与下导电层123之间的电绝缘层122。下承载衬底120例如可以是DCB(直接键合铜)，DAB(直接键合铝)或AMB(活性金属钎焊)型的衬底。
根据一种示例，半导体封装100还可以具有封装体(未示出)，该封装体将间距保持件130和150、至少一个功率半导体芯片140、上导电元件110以及下承载衬底120封装在内。上导电元件110与下承载衬底120之间的间隙尤其可以通过封装体完全或部分地填充。但是，上导电元件110的金属表面111和下导电层123的表面124在任何情况下都构型成完全或至少部分向外露出的(即表面111、124是半导体封装件100的外表面)。
根据一种示例，封装体可以具有灌注料或模压料或由它们组成。封装体例如可以借助模压制造。为了制造封装体，例如可以将尚未封装的半导体封装100放置到模具中(英语“molding tool”)，可以注入介电物料，并且可以将介电物料固化成封装体。
导电间距保持件130、150可以由金属或金属合金构成，并且例如可以具有铝或铜或由其构成。第一导电间距保持件130与上导电元件110并且与下承载衬底120例如通过焊接或导电粘合剂物理地和电气地连接。
根据一种示例，至少一个功率半导体芯片140包括碳化硅或由其组成。根据一种示例，至少一个功率半导体芯片140是IGBT(绝缘栅双极型晶体管)型芯片。根据一种示例，在半导体封装100中实现有半桥电路。该半桥电路可以具有用于正供电电压(VDD)的功率连接端、用于负供电电压(VSS)的功率连接端以及构型成相(Phase)的功率连接端。
第二导电间距保持件150可以与功率半导体芯片140的电极(未示出)并且与上导电元件110(例如通过焊接或导电粘合剂)电连接。所述电极可以是功率半导体芯片140的功率电极或控制电极。第二导电间距保持件150可以完全或部分地覆盖功率半导体芯片140。
根据一种示例，半导体封装可以具有连接引脚(Anschlussfinger)形式的外连接端。这些外连接端的至少一部分可以设计用于将至少一个功率半导体芯片140的电极与外界电连接。外连接端可以与上导电元件110和/或与上导电层121电连接。连接引脚可以是引线框架的一部分。外连接端中的一个可以是功率连接端，这些功率连接端例如可以与至少一个功率半导体芯片140的相应功率电极电连接。外连接端中的一个或多个可以是控制连接端，所述控制连接端与至少一个功率半导体芯片140的控制电极(例如栅极)电连接。外连接端中的一个可以是测量连接端，该测量连接端例如设计用于测量半导体封装100中的VDD、VSS、相电压、电流或温度。
在半导体封装100中布置有屏蔽结构，该屏蔽结构构造用于电磁屏蔽半导体封装100的一个或多个线路。电磁屏蔽可以用于防止：构造在半导体封装100中的电路在其电开关特性方面受到外部电磁路径的干扰。电磁屏蔽还可以用于防止：构造在半导体封装100中的电路又通过电磁影响而引起另一构件中的干扰。这些待屏蔽的线路可以例如包括一个或多个控制连接端和/或一个或多个测量连接端。屏蔽结构可以构造在上导电层121中和/或上导电元件110和/或引线框架中。
屏蔽结构可以设计成处于VSS或VDD上。处于VSS或VDD上的屏蔽结构可以设计成相的低电阻屏蔽。由此，可以至少部分地防止所述相向外电磁辐射并且充当其他构件的干扰源。
在待屏蔽的线路是控制线路的情况下，尤其如果至少一个功率半导体芯片140是基于碳化硅的，则具有显著大于10kHz的控制信号可以施加在控制线路上。因此，这种控制线路可以用作天线并且会在没有电磁屏蔽的情况下将功率耦合到周围环境中，或者从周围环境接收功率。从周围环境接收功率可能导致控制信号受到干扰并且电路的开关特性受到不利影响。相应的屏蔽则可以有助于确保至少一个功率半导体芯片140的无故障开关。这也类似地适用于半导体封装100中的其他类型的线路。
半导体封装100可以包括构造在上导电层121中的控制线路，该控制线路与至少一个功率半导体芯片的控制电极并且与控制连接端电连接。屏蔽结构可以在至少两侧上包围控制线路以及与该控制线路连接的控制连接端。
图1B示出半导体封装100_1，除了在下文中描述的不同之处以外，该半导体封装与图1A的半导体封装100一致。在半导体封装100_1中，上导电元件110具有上承载衬底160，该上承载衬底具有上导电层161、下导电层163和布置在上导电层161与下导电层163之间的电绝缘层162。在此，上导电层161相应于向外露出的金属表面111。
半导体封装100_1还可以具有外连接端170，如图1B所示，该外连接端布置在上承载衬底160与下承载衬底120之间。根据一种示例，外连接端170中的每个可以与上承载衬底160的下导电层163或者与下承载衬底120的上导电层121电连接。
上承载衬底160的下导电层163以及下承载衬底120的上导电层121是结构化的，并且它们例如可以具有用于导电间距保持件130、150的芯片平台、线路导轨和/或安装位置。
图2示出半导体封装200的立体视图，该半导体封装可以与半导体封装100和100_1相同。半导体封装200具有封装体210，该封装体将间距保持件130、150、上导电元件110、下承载衬底120和至少一个功率半导体芯片140封装在内。表面111和表面124(在图2中不可见)在封装体210上处于半导体封装200的相对置的侧上并且是向外露出的。
封装体210由合适的电绝缘材料构成或者具有如下材料：例如塑料、聚合物或树脂。封装体210例如可以是模制成型体(molded body)。
表面111和/或表面124可以具有电绝缘涂层，并且所述表面可以分别构造用于冷却体的安装。
半导体封装200具有外连接端220、230，所述外连接端布置在半导体封装200的以下侧面上：该侧面将具有金属表面111和表面124的相对置的侧连接。外连接端220可以设计成功率连接端，并且外连接端230可以设计成控制连接端或测量连接端。根据一种示例，功率连接端仅布置在半导体封装的一侧上，并且控制连接端或测量连接端仅布置在相对置的侧上。根据另一示例，构造成相的功率连接端布置在具有控制连接端或测量连接端的侧面上。外连接端220和230可以是共同的引线框架的一部分。
图3A示出半导体封装300的下承载衬底120的立体视图。半导体封装300可以与半导体封装100、100_1和200相同。
半导体封装300的上导电层121可以包括第一结构化区域310、第二结构化区域320、第三结构化区域330、第四结构化区域340和第五结构化区域350。
第一功率半导体芯片311可以布置在第一区域310上并且与该第一区域电连接。例如，布置在第一功率半导体芯片311的下侧上的功率电极(例如漏极)可以通过焊料层与第一区域310连接。第一区域310可以设计用于施加VDD。第一区域310可以与第一功率连接端312电连接。第一功率半导体芯片311可以构型成设置在半导体封装300中的半桥电路的高侧功率半导体芯片。
第二功率半导体芯片331可以布置在第三区域330上并且与第三区域330连接。例如，布置在第二功率半导体芯片331的下侧上的功率电极(例如漏极)可以通过焊料层与第三区域330连接。第三区域330可以设计成半桥电路的相。第三区域330可以与第三功率连接端332电连接。第二功率半导体芯片331可以构型成所述半桥电路的低侧功率半导体芯片。第三区域330可以(例如通过导电间距保持件130)与上承载衬底160电连接。
第二区域320可以布置在下承载衬底120上的第一区域310与第三区域330之间。第二区域320可以与第二功率连接端322电连接，并且该第二区域可以设计用于施加VSS。第二区域320可以(例如通过导电间距保持件130)与上承载衬底160电连接。
第四区域340可以(例如通过导电间距保持件130)与上承载衬底160电连接，并且第四区域可以设计用于施加相。第五区域350可以(例如通过导电间距保持件130)与上承载衬底160电连接，并且第五区域可以设计用于施加VSS。
半导体封装300的上导电层121还可以包括第一控制线路361和第二控制线路362。第一控制线路361可以在两侧由第一区域310至少部分地包围，并且第二控制线路可以在两侧由第三区域330至少部分地包围。第一功率半导体芯片311的控制电极(例如栅极)可以(例如借助接合线)与第一控制线路361电连接。第二功率半导体芯片331的控制电极(例如栅极)可以(例如通过接合线)与第二控制线路362电连接。第一控制线路361和第二控制线路362可以分别具有细长的形状，即控制线路361、362的长度可以明显大于它们的宽度(例如超过10倍或超过15倍或超过20倍)。
控制线路361、362可以延伸到下承载衬底120的第一侧301直至边缘或者几乎直到下承载衬底120的边缘。第一控制线路361可以在第一侧301上与第一控制连接端363电连接，第二控制线路362可以在第一侧301上与第二控制连接端364电连接。第一控制连接端363和第二控制连接端364可以分别包括连接引脚。
根据一种示例，第一控制连接端363或第二控制连接端364在左侧和右侧由屏蔽结构的第一部分包围。屏蔽结构的第一部分例如可以具有连接引脚341、351的形状。连接引脚341与第四区域340电连接，并且连接引脚351与第五区域电连接。
根据一种示例，屏蔽结构的第一部分在第一控制连接端363和第二控制连接端364的左侧和右侧具有多于一个的连接引脚341或351——例如在左侧和右侧分别具有两个连接引脚341和351。另外的连接引脚341和351也分别与第四区域340或第五区域350电连接。在左侧和右侧使用多于一个连接引脚可以有助于通过屏蔽结构进一步改善电磁屏蔽。
关于第一控制线路361而言，第一区域310可以是屏蔽结构的构造在上导电层121中的第三部分。第四区域340也可以是第一控制线路361的屏蔽结构的第三部分的一部分。关于第二控制线路362而言，第三区域330可以是屏蔽结构的构造在上导电层121中的第三部分。第五区域350也可以是第二控制线路362的屏蔽结构的第三部分的一部分。
根据一种示例，半导体封装300还具有测量连接端313，该测量连接端与第一区域310电连接并且设计用于测量VDD。控制连接端363和364、连接引脚341和351以及测量连接端313可以全部布置在下承载衬底120的第一侧301上，并且功率连接端312、322和332可以全部布置在相对置的第二侧302上。控制连接端363和364、连接引脚341和351、测量连接端313以及功率连接端312、322和332都可以是引线框架的一部分。
图3B示出半导体封装300的上承载衬底160的立体视图，其中，在图3B中示出上承载衬底160的下侧的立体视角(参见图3C中用于视向的箭头)。
上承载衬底160的下导电层163是结构化的并且具有第六区域370和第七区域380。第六区域370在组装的半导体衬底300(参见图3C)中与下承载衬底120的第一区域310重叠。第七区域380在组装的半导体衬底300中与第二区域320并且与下承载衬底120的第三区域330重叠。
在第六区域370中布置有第一表面371，该第一表面完全填充有下导电层163。在第七区域380中布置第二表面381，该第二表面完全填充有下导电层163。在组装的半导体封装300中，第一控制线路361覆盖第一表面371并且第二控制线路381覆盖第二表面381。在组装的半导体封装300中，第一表面371是第一控制线路361的屏蔽结构的第二部分，并且该第一表面与第四区域340和连接引脚341电连接。在组装的半导体封装300中，第二表面381是第二控制线路362的屏蔽结构的第二部分，并且该第二表面与第五区域350以及连接引脚351电连接。以这种方式，第一控制线路361或第二控制线路362可以由相应屏蔽结构的至少三侧包围。
根据一种示例，连接引脚341作为屏蔽结构的第一部分构造用于电磁屏蔽控制连接端363，并且表面371和区域310、340作为屏蔽结构的第二和第三部分构造用于电磁屏蔽控制连接端361。类似地，连接引脚351作为屏蔽结构的第一部分构造用于电磁屏蔽控制连接端364，并且表面381和区域330、350分别作为屏蔽结构的第二和第三部分构造用于电磁屏蔽控制线路362。
在第六区域370和第七区域380中，凹部372、382设置用于包围如下接点：在该连接点处，将下承载衬底160的下导电层163安置到导电间距保持件130、150上(参见图1A)。第一表面371和第二表面381不具有这些凹部372、382。
图3C示出在将上承载衬底160布置在图3A的下承载衬底120上之后的半导体封装300。为清楚起见，在图3C中仅示出上承载衬底160的下导电层163，省略了上导电层161和绝缘层162。第六区域370可以完全或部分地覆盖第一区域310和第四区域340，并且第七区域380可以完全或部分地覆盖第二区域320、第三区域330和第五区域350。第六区域370可以借助导电间距保持件与第三区域330并且与第四区域340电连接，并且第七区域380可以借助导电间距保持件与第二区域320并且与第五区域350电连接。
图3D示出沿着图3C中的箭头方向的半导体封装300的侧视图。
图4示出用于制造具有双侧冷却结构的半导体封装的方法400的流程图。根据方法400，例如可以制造半导体封装100、100_1、200和300。
方法400包括在401中提供下承载衬底，该下承载衬底具有上导电层、下导电层以及布置在上导电层与下导电层之间的电绝缘层。方法400包括在402中将第一导电间距保持件安置在下承载衬底的上导电层上。方法400包括在403中将至少一个功率半导体芯片安置在下承载衬底的上导电层上。方法400包括在404中将第二导电间距保持件安置在功率半导体芯片上。方法400包括在405中将上导电元件与下承载衬底相对置地安置在所述间距保持件上。方法400包括在406中如此构造屏蔽结构，使得半导体封装的控制连接端或测量连接端由屏蔽结构电磁屏蔽。
方法400还可以包括：为了构造屏蔽结构的第一部分，将第二连接引脚和第三连接引脚在两侧上布置在所述半导体封装的控制连接端的第一连接引脚旁边。
方法400还可以包括在下承载衬底的上导电层中构造控制线路，其中，该控制线路将至少一个功率半导体芯片的控制电极与该控制连接端电连接，其中，该控制线路由屏蔽结构的至少三侧包围。方法400还可以包括蚀刻上导电元件来产生屏蔽结构的第二部分，其中，屏蔽结构的第二部分与控制线路重叠。方法400还可以包括蚀刻下承载衬底的上导电层来产生屏蔽结构的第三部分，其中，该第三部分在两侧上包围控制线路。
图5示出半导体封装500的另一示例，其中，半导体封装500可以与半导体封装100、100_1、200和300类似，并且该半导体封装可以仅具有在下文中示出的相对于它们的区别。为清楚起见，在图5中未示出半导体封装500的上承载衬底和可能的封装体。
半导体封装500的下承载衬底501具有第一承载区域510和第二承载区域520，该第一承载区域具有第一功率半导体芯片511，该第二承载区域具有第二功率半导体芯片521。第一承载区域510例如可以设计用于施加VDD，并且第二承载区域520可以例如设计用于施加相。
第一承载区域510可以与第一功率连接端512并且与第二功率连接端513连接。第三功率连接端530可以布置在第一功率连接端512与第二功率连接端513之间。第三功率连接端530可以与半导体封装500的上承载衬底连接，并且该第三功率连接端可以是VSS连接端。第二承载区域520可以与第四功率连接端522连接。
第一功率半导体芯片511的控制电极(例如栅极)可以与第一控制线路541连接，并且第二功率半导体芯片521的控制电极(例如栅极)可以与第二控制线路542连接。
在第一控制线路541与第二控制线路542之间构造有屏蔽结构550，该屏蔽结构(尤其相互)电磁屏蔽控制线路541、542。控制线路541、542和屏蔽结构550可以构造成下承载衬底501的上导电层中的结构化区域。
根据一种示例，屏蔽结构550(例如通过一个或多个导电间距保持件)与半导体封装500的上承载衬底电连接。屏蔽结构550尤其可以构造用于施加VSS。
尽管在此已经示出和描述了特定的实施方式，但是对于本领域技术人员显而易见的是，在不脱离本发明的保护范围的情况下，多种替代的和/或等效的实施方式可以替代所示的和所描述的特定实施方式。本申请旨在涵盖在此讨论的特定实施方式的所有改型或变型。因此期望的是，本发明旨在仅通过权利要求及其等同内容进行限制。

Claims (20)

1.一种能够双侧冷却的半导体封装(100，200，300)，所述半导体封装(100，200，300)包括：
上导电元件(110)，所述上导电元件具有向外露出的金属表面(111)，
下承载衬底(120)，所述下承载衬底包括上导电层(121)、下导电层(123)和电绝缘层(122)，其中，所述下导电层具有向外露出的表面(124)，所述电绝缘层布置在所述上导电层与所述下导电层(121，123)之间，
第一导电间距保持件(130)，所述第一导电间距保持件布置在所述上导电元件(110)与所述上导电层(121)之间，
至少一个功率半导体芯片(140)，所述至少一个功率半导体芯片布置在所述上导电元件(110)与所述上导电层(121)之间，
第二导电间距保持件(150)，所述第二导电间距保持件布置在所述上导电元件(110)与所述功率半导体芯片(140)之间，
屏蔽结构，所述屏蔽结构构造用于电磁屏蔽所述半导体封装(100，200，300)的线路(361，362)，
其中，所述线路(361，362)包括所述半导体封装(100，200，300)的控制连接端(363，364)或测量连接端，
其中，所述控制连接端(363，364)和/或所述测量连接端以及所述屏蔽结构的至少一个第一部分构造在引线框架中。
2.根据权利要求1所述的半导体封装(100，200，300)，其中，所述上导电元件(110)具有上承载衬底(160)，所述上承载衬底具有上导电层(161)、下导电层(163)和电绝缘层(162)，其中，所述电绝缘层布置在所述上导电层与所述下导电层(161，163)之间，其中，所述上导电层(161)相应于所述向外露出的金属表面(111)。
3.一种能够双侧冷却的半导体封装(100，200，300)，所述半导体封装(100，200，300)包括：
上承载衬底(160)，所述上承载衬底具有向外露出的上导电层(161)、下导电层(163)和电绝缘层(162)，其中，所述电绝缘层布置在所述上导电层与所述下导电层(161，163)之间，
下承载衬底(120)，所述下承载衬底具有上导电层(121)、下导电层(123)和电绝缘层(122)，其中，所述下导电层具有向外露出的表面(124)，所述电绝缘层布置在所述上导电层与所述下导电层(121，123)之间，
第一导电间距保持件(130)，所述第一导电间距保持件布置在所述上承载衬底(160)与所述下承载衬底(120)的上导电层(121)之间，
至少一个功率半导体芯片(140)，所述至少一个功率半导体芯片布置在所述上承载衬底(160)与所述下承载衬底(120)的上导电层(121)之间，
第二导电间距保持件(150)，所述第二导电间距保持件布置在所述上承载衬底(160)与所述功率半导体芯片(140)之间，
屏蔽结构，所述屏蔽结构构造用于电磁屏蔽所述半导体封装(100，200，300)的线路(361，362)，
其中，所述屏蔽结构的第二部分构造在所述上承载衬底(160)的下导电层(163)中。
4.根据以上权利要求中任一项所述的半导体封装(100，200，300)，所述半导体封装还包括：
控制线路(361，362)，所述控制线路构造在所述下承载衬底(120)的上导电层(121)中，并且所述控制线路与所述控制连接端(363，364)以及与所述至少一个功率半导体芯片(311，331)的控制电极电连接，
其中，所述屏蔽结构的第三部分构造在所述下承载衬底(120)的上导电层(121)中并且在两侧上包围所述控制线路(361，362)。
5.根据权利要求3所述的半导体封装(100，200，300)，其中，所述屏蔽结构的第二部分与所述控制线路(361，362)重叠，
其中，所述屏蔽结构的第二部分构造用于施加负供电电压。
6.根据权利要求4所述的半导体封装(100，200，300)，其中，所述至少一个功率半导体芯片(311，331)是半桥电路的高侧功率半导体，并且所述屏蔽结构的第三部分构造用于施加正供电电压。
7.根据权利要求3和6所述的半导体封装(100，200，300)，其中，所述屏蔽结构的第二部分与所述控制线路(361，362)重叠，
其中，所述屏蔽结构的第二部分构造用于施加相。
8.根据权利要求1所述的半导体封装(100，200，300)，其中，所述控制连接端(363，364)或所述测量连接端包括第一连接引脚，所述屏蔽结构的第一部分包括第二连接引脚和第三连接引脚(341，351)，并且所述第一连接引脚(363，364)布置在所述第二连接引脚与所述第三连接引脚(341，351)之间。
9.根据权利要求3和4所述的半导体封装(100，200，300)，其中，所述第一导电间距保持件(130)将所述屏蔽结构的第二部分与第三部分彼此电连接。
10.根据以上权利要求中任一项所述的半导体封装(100，200，300)，其中，所述测量连接端构造用于测量所述半导体封装中的电流或温度。
11.根据以上权利要求中任一项所述的半导体封装(100，200，300)，所述半导体封装还包括：
第一功率连接端、第二功率连接端和第三功率连接端(312，322，332)，
其中，这些功率连接端(312，322，332)布置在所述半导体封装(100，200，300)的第一侧(302)上，并且所述控制连接端(363，364)布置在所述半导体封装(100，200，300)的与所述第一侧(302)相对置的第二侧(301)上。
12.根据以上权利要求中任一项所述的半导体封装(100，200，300)，所述半导体封装还包括：
封装体(210)，所述封装体布置在所述下承载衬底(120)与所述上导电元件(110)之间，并且所述封装体将所述间距保持件(130，150)、所述至少一个功率半导体芯片(140)、所述上导电元件(110)和所述下承载衬底(120)封装在内。
13.根据权利要求12所述的半导体封装(100，200，300)，其中，所述封装体(210)包括模压料。
14.根据以上权利要求中任一项所述的半导体封装(100，200，300)，其中，所述至少一个功率半导体芯片(140)包括碳化硅。
15.一种用于制造能够双侧冷却的半导体封装的方法(400)，所述方法(400)包括：
提供(401)下承载衬底，所述下承载衬底具有上导电层、下导电层以及布置在所述上导电层与所述下导电层之间的电绝缘层，
将第一导电间距保持件安置(402)在所述下承载衬底的上导电层上，
将至少一个功率半导体芯片安置(403)在所述下承载衬底的上导电层上，
将第二导电间距保持件安置(404)在所述功率半导体芯片上，
将上导电元件与所述下承载衬底相对置地安置(405)在所述间距保持件上，
如此构造(406)屏蔽结构，使得所述半导体封装的线路由所述屏蔽结构电磁屏蔽，
其中，所述线路包括所述半导体封装的控制连接端或测量连接端，
其中，将所述控制连接端和/或所述测量连接端以及所述屏蔽结构的至少一个第一部分构造在引线框架中。
16.根据权利要求15所述的方法(400)，其中，构造(406)所述屏蔽结构包括：为了构造所述屏蔽结构的第一部分，将第二连接引脚和第三连接引脚在两侧上布置在所述半导体封装的控制连接端的第一连接引脚旁边。
17.根据权利要求16所述的方法(400)，其中，构造(406)所述屏蔽结构包括：在所述下承载衬底的上导电层中构造控制线路，其中，所述控制线路将所述至少一个功率半导体芯片的控制电极与所述控制连接端电连接，
其中，所述控制线路在至少三侧上由所述屏蔽结构包围。
18.根据权利要求17所述的方法(400)，其中，构造(406)所述屏蔽结构包括：蚀刻所述上导电元件来产生所述屏蔽结构的第二部分，所述屏蔽结构的第二部分与所述控制线路重叠。
19.根据权利要求17或18所述的方法(400)，所述方法还包括：蚀刻所述下承载衬底的上导电层来产生所述屏蔽结构的第三部分，所述屏蔽结构的第三部分在两侧上包围所述控制线路。
20.根据权利要求15至19中任一项所述的方法(400)，所述方法还包括：借助封装体至少部分地封装所述下承载衬底和所述上导电元件，所述封装体包括模压料。
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