CN105448665A - 半导体结构的制造方法以及相关半导体结构 - Google Patents

半导体结构的制造方法以及相关半导体结构 Download PDF

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CN105448665A
CN105448665A CN201510765107.XA CN201510765107A CN105448665A CN 105448665 A CN105448665 A CN 105448665A CN 201510765107 A CN201510765107 A CN 201510765107A CN 105448665 A CN105448665 A CN 105448665A
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semiconductor layer
area
main semiconductor
multilayer substrate
basic unit
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比什-因·阮
玛丽亚姆·萨达卡
C·马勒维尔
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Soitec SA
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Soitec SA
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Abstract

半导体结构的制造方法以及相关半导体结构。形成半导体结构的方法包括提供多层衬底，该多层衬底具有覆在位于埋置氧化物层之上的应变主半导体层上的外延基层。使用外延基层内的元素来改变多层衬底的第一区域内的主半导体层中的应变状态，而不改变多层衬底的第二区域内的主半导体层的应变状态。形成各包括多层衬底第一区域内的主半导体层的一部分的第一多个晶体管沟道结构，并且形成各包括多层衬底的第二区域内的主半导体层的一部分的第二多个晶体管沟道结构。通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

Description

半导体结构的制造方法以及相关半导体结构
技术领域
本公开的实施方式涉及可用于制造在半导体衬底上的共用层中具有不同应力(stress)状态的n型金属氧化物半导体(NMOS)场效应晶体管和p型金属氧化物半导体(PMOS)场效应晶体管的方法，并且涉及使用这种方法制造的半导体结构和器件。
背景技术
诸如微处理器和存储装置等的半导体器件采用固态晶体管作为其集成电路的基本、主要的操作结构。在半导体结构和器件中常用的晶体管中的一种是场效应晶体管(FET)，通常包括源接触件、漏接触件和一个或更多个栅接触件。半导电的沟道区在源接触件与漏接触件之间延伸。一个或更多个pn结被限定在源接触件与栅接触件之间。栅接触件定位成与沟道区的至少一部分相邻，并且沟道区的导电性由于电场的存在而变化。因此，通过向栅接触件施加电压而在沟道区内提供电场。由此，例如，在对栅接触件施加电压时，电流可以通过沟道区从源接触件到漏接触件流过晶体管，但在不对栅接触件施加电压时，可能不能从源接触件到漏接触件流过晶体管。
近来，已经开发了采用称为“鳍(fin)”的分离的细长沟道结构的场效应晶体管(FET)。这样的晶体管在本领域中通常称为“finFET”。本领域提出了许多不同的finFET的构造。
finFET的该细长沟道结构或鳍包括n型或p型的可以被掺杂的半导体材料。还已表明当n型半导体材料处于拉应力状态时，可以提高n型掺杂半导体材料的导电性，并且当p型半导体材料处于压应力状态时，可以提高p型半导体材料的导电性。
目前使用的finFET具有小于22nm的截面尺寸。这样的finFET可以采用全耗尽(未掺杂)沟道，该全耗尽沟道提高了晶体管的静电性能并且避免了与随机掺杂波动关联的问题。已表明在晶体管的沟道区中引入拉伸应变(strain)可以提高n型FET的电子迁移率，并且在晶体管的沟道区中引入压缩应变可以提高p型FET的空穴迁移率。
发明内容
提供该发明内容，以以简化形式介绍一些概念。这些概念在下文本公开的示例性实施方式的详细描述中进一步详细地描述。该发明内容不旨在识别所要求保护的主题的关键特征或基本特征，也不旨在用于限制所要求保护的主题的范围。
在一些实施方式中，本公开涉及一种制造半导体结构的方法。提供多层衬底，该多层衬底包括基底衬底；埋置氧化物层，该埋置氧化物层在基底衬底的表面上方；应变主半导体层，该应变主半导体层在埋置氧化物层上方、该埋置氧化物层的与基底衬底相反的一侧上；以及外延基层，该外延基层在应变半导体层上方、该应变半导体层的与埋置氧化物层相反的一侧上。在不将元素从外延基层扩散到多层衬底的第二区域内的应变主半导体层中的情况下，将元素从外延基层扩散到多层衬底的第一区域内的应变主半导体层中，，并且增大在第一区域内的主半导体层中所扩散元素的浓度，使得第一区域内的主半导体层中的应变状态不同于第二区域内的主半导体层中的应变状态。形成第一多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于多层衬底的第一区域内的主半导体层的一部分，并且形成第二多个晶体管沟道结构，第二多个晶体管沟道结构分别包括位于多层衬底的第二区域内的主半导体层的一部分。
在另一实施方式中，本公开包括一种制造半导体结构的方法，在该方法中，提供多层衬底，该多层衬底包括基底衬底；埋置氧化物层，该埋置氧化物层在基底衬底的表面上方；应变主半导体层，该应变主半导体层在埋置氧化物层上方、该埋置氧化物层的与基底衬底相反的一侧上；以及外延基层，该外延基层在应变半导体层上方、该应变半导体层的与埋置氧化物层相反的一侧上。用第一掩模层遮蔽多层衬底的第一区域，并且从多层衬底的第二区域去除外延基层的一部分。从多层衬底的第一区域去除第一掩模层，并且用第二掩模层遮蔽多层衬底的第二区域。在将元素不扩散到位于多层衬底的所述第二区域内的应变主半导体层中的情况下，将元素从外延基层扩散到位于多层衬底的第一区域内的应变主半导体层中，并且改变多层衬底的第一区域内的主半导体层的应变状态。形成第一多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于多层衬底的第一区域内的主半导体层的一部分，并且形成第二多个晶体管沟道结构，第二多个晶体管沟道结构分别包括位于多层衬底的第二区域内的主半导体层的一部分。
在进一步的实施方式中，本公开包括一种包括多层衬底的半导体结构，该半导体结构包括：基底衬底；埋置氧化物层，该埋置氧化物层在基底衬底的表面上方；以及主半导体层，该主半导体层在埋置氧化物层之上、该埋置氧化物层的与基底衬底相反的一侧上。位于多层衬底的第一区域内的主半导体层的一部分包括SiyGe1-y，其中，y在大约0.20到大约0.99之间，并且位于多层衬底的第二区域内的主半导体层的一部分包括拉伸应变硅。位于多层衬底的第一区域内的主半导体层的部分具有与位于多层衬底的第二区域内的主半导体层的部分的晶体应变不同的晶体应变。
附图说明
虽然本说明书以具体指出并清楚要求保护什么被认为是本发明的实施方式的权利要求结束，但在结合附图阅读公开的实施方式的特定示例的描述时，更加容易地确定公开的实施方式的优点，在附图中：
图1至图4是例示了根据本公开的实施方式的可以采用的多层衬底的制造的简化、示意性例示的截面图；
图1例示了将离子注入到包括体材料、外延基层和应变主半导体层的施主衬底中，所注入的离子在外延基层内形成弱化区；
图2例示了将图1的施主衬底结合到受主衬底；
图3例示了沿着弱化区分离施主衬底；
图4例示了在如图3例示沿着弱化区分离施主衬底时形成多层衬底；
图5例示了第一掩模层覆盖图4的多层衬底的第一区域，而多层衬底的另一个第二区域不被覆盖并借助第一掩模层露出；
图6例示了在从多层衬底的第二区域中的主半导体层上去除外延基层的一部分之后图5的半导体结构，而外延基层的另一部分仍保持在多层衬底的第一区域中的、图5的第一掩模层下的主半导体层上方；
图7例示了通过从多层衬底的第一区域去除第一掩模层并在多层衬底的第二区域的主半导体层上方设置第二掩模层所形成的结构；
图8A-图8C是多层衬底的第一区域的一部分的放大图，该图例示了用于将一种或更多种元素从外延基层扩散到位于多层衬底的第一区域内的主半导体层中以改变多层衬底的第一区域中的主半导体层内的应变状态的凝聚(condensation)工艺；
图9例示了通过蚀刻穿透图7的结构的主半导体层而形成的多个鳍结构；以及
图10例示了finFET晶体管的示例结构。
具体实施方式
本文提出的例示并非是任何特定半导体结构、器件、系统或方法的实际视图，而仅仅是用于描述公开的实施方式的理想化图示。
本文所使用的任何标题不应被认为是限制如下面权利要求及其合法等同物所限定的本发明的实施方式的范围。任何特定标题中描述的概念在通篇整个说明书普遍适用于其它部分。
本说明书和权利要求中的术语第一和第二用于区分类似元件。
如本文所用，术语“鳍”和“鳍结构”指的是具有长度、宽度和高度的、细长、三维的体积有限且有约束的半导体材料，其中，长度大于宽度。鳍的宽度和高度在某些实施方式中可以沿着鳍的长度变化。
下面参照附图描述可用于制造半导体器件的方法。如下文进一步详细讨论的，方法总体涉及提供多层衬底，该多层衬底包括基底衬底、位于基底衬底的表面上方的埋置氧化物(BOX)层、位于BOX层的基底衬底相反的一侧在BOX层上方的应变主半导体层、以及位于应变半导体层的与BOX层相反的一侧在应变半导体层上方的外延基层。如本文下面所讨论的，外延基层可以包括以下的层，即在该层上预先外延生长了主半导体层。在提供了多层衬底之后，可以以这样的方式处理多层衬底：改变主半导体层的一个区域中的应变状态，而不改变主半导体层的另一个区域中的应变状态，使得不同应变状态的区域存在于主半导体层中。然后，可以在主半导体层的一个或多个区域中制造表现出对提高电子迁移率较优选的应变状态的N型晶体管结构，并且可以在主半导体层的一个或多个区域中制造表现出对提高空穴迁移率较优选的应变状态的p型晶体管结构。
下面参照图1至图4公开可以用于提供多层衬底的方法的示例实施方式。图1例示了施主衬底(donorsubstrate)100，其包括体材料102、体材料102上的外延基层104以及位于外延基层104的与体材料102相反的一侧上的应变半导体层106。
体材料102可以包括例如，半导体材料(例如，硅、碳化硅、锗、III-V族半导体材料等)、陶瓷材料(例如，氧化硅、氧化铝、碳化硅等)、或金属材料(例如，钼等)的晶圆或晶片。体材料102在一些实施方式中可以具有单晶或多晶微结构。在其他实施方式中，体材料102可以是非晶的。体材料102可以具有范围是从例如大约400μm至大约900μm(例如，大约750μm)的厚度。
覆在体材料102上的层(诸如外延基层104和主半导体层106等)可以通过使用一些不同工艺(诸如例如，化学气相淀积(CVD)、原子层淀积(ALD)、物理气相淀积(PLD)、气相外延(VPE)、分子束外延(MBE)等)中的任一种在衬底上沉淀或外延“生长”。
在一些实施方式中，如下面进一步详细讨论的，外延基层104可以包括可用于在后续处理中辅助保留上覆的主半导体层106的晶格中的应变的材料。因此，如下文进一步详细讨论的，外延基层104可以具有允许外延基层104在后续处理中保留上覆的主半导体层106的晶格中的应变而选择的组成和/或层厚度。
主半导体层106可以包括例如，应变硅(Si)层、应变锗(Ge)层、应变硅锗(SiGe)层或应变III-V族半导体材料层。因此，应变主半导体层106可以具有呈现以下晶格参数的晶体结构，即这些晶格参数高于(拉伸应变)或低于(压缩应变)各应变半导体层106在平衡状态下以独立、体形式存在的情况下其晶体结构所正常呈现的弛豫晶格参数。虽然本公开的实施方式也可以采用更厚层的应变半导体材料，但主半导体层106可以具有大约50nm或更小、或甚至大约35nm或更小的平均层厚。
可选地，可以在体材料102与外延基层104之间设置一个或更多个缓冲层108，以促进外延基层104和主半导体层106在体材料102上的外延生长。
作为一个非限制性具体示例，施主衬底100的体材料102可以包括单晶硅衬底，外延基层104可以包括SixGe1-x(其中，x从大约0.01至大约0.99，或，更具体地，从大约0.20至大约0.80)，并且主半导体层106可以包括应变硅(sSi)或应变SiyGe1-y(其中，y从大约0.20至大约0.99)。在一些实施方式中，外延基层104的SixGe1-x可以包括至少大致上弛豫的SixGe1-x。换句话说，在一些实施方式中，外延基层104的SixGe1-x可以至少大致上无晶体应变。
可以在体材料102的硅与SixGe1-x外延基层104之间设置包括SizGe1-z(其中，z值随着远离体材料102而以阶梯式或连续方式逐步增大)的一个或更多个缓冲层108。
可以选择SixGe1-x外延基层104中的x值，以在主半导体层106的上覆的Si或SiyGe1-y中给予期望的应变水平。如本领域已知的，硅与锗之间存在大约4.2％的晶格错配度。因此，SixGe1-x外延基层104中的锗的量将至少部分决定SixGe1-x外延基层104中的晶格参数的值，并且因此，部分决定上覆的外延主半导体层106的Si或SiyGe1-y的晶格中的晶体应变量。
外延基层104和主半导体层106可以具有低于它们各自的临界厚度的厚度，以避免其晶体结构中的开始弛豫和局部缺陷的形成。
在形成或以其他提供提供图1的施主衬底100之后，主半导体层106和外延基层104的至少一部分可以通过使用例如本领域被称为工艺的工艺转移到受主衬底(receiversubstrate)110(图2)。工艺在例如，授权给Bruel的美国专利No.RE39484(2007年2月6日授权)、授权给Aspar等人的美国专利No.6303468(2001年10月16日授权)、授权给Aspar等人的美国专利No.6335258(2002年1月1日授权)、授权给Moriceau等人的美国专利No.6756286(2004年6月29日授权)、授权给Aspar等人的美国专利No.6809044(2004年10月26日授权)和授权给Aspar等人的美国专利No.6946365(2005年9月20日授权)中均有描述，此处以引证的方式将这些专利的全部公开整体并入本文。
多个离子(例如，氢、氦或惰性气体离子)可以被注入到施主衬底100中。例如，离子可以从定位在施主衬底100一侧的离子源注入到施主衬底100中，如图1中方向箭头109所示。离子可以沿着大致垂直于施主衬底100的主表面的方向注入到施主衬底100中。如本领域已知的，离子注入到施主衬底100中的深度至少部分是离子注入到施主衬底100中所用能量的函数。通常，以较低能量注入的离子将注入在相反较浅的深度，而以较高能量注入的离子将注入在相对较深的深度。
离子可以以预定能量注入到施主衬底100中，选择该预定能量是为了在施主衬底100中以期望深度注入离子。作为一个特定的非限制性示例，离子可以以所选深度布置在施主衬底100中，使得在施主衬底100中形成弱化区。如本领域已知的，至少一些离子不可避免地以除了期望注入深度之外的深度注入，并且离子的浓度曲线图(作为从施主衬底100的表面到施主衬底100中的深度的函数)可以呈现大致钟形(对称或不对称)曲线，该曲线在期望注入深度处具有最大值。
在离子被注入到施主衬底100中时，离子就可以在施主衬底100中限定弱化区112(如图1中的虚线所示)。该弱化区112可以包括位于施主衬底100内的对准施主衬底100最大离子浓度的平面(例如，以该平面为中心)的层或区域。弱化区112可以在施主衬底100内限定用于在后续过程中可以沿着其分开或裂开施主衬底100的平面。如图1所示，弱化区112可以布置在包括外延基层104在内的施主衬底的大致均同质区域内。
在施主衬底100内形成弱化区112之后，如图2所示，可以使用直接分子结合工艺将施主衬底100结合到受主衬底110。
直接分子结合工艺可以在施主衬底100与受主衬底110之间形成直接原子键。施主衬底100与受主衬底110之间的原子键的性质将依赖于施主衬底100和受主衬底110的各自表面处的材料组成。
在一些实施方式中，施主衬底100的结合面与受主衬底110的结合面之间的直接结合可以通过将施主衬底100的结合面和受主衬底110的结合面形成为具有相对平滑的表面并且随后将两个结合面邻接在一起并在两个结合面之间开始传播结合波而建立。例如，可以将施主衬底100的结合面和受主衬底110的结合面形成为具有大约两纳米(2.0nm)或更小、大约1纳米(1.0nm)或更小、或甚至大约四分之一纳米(0.25nm)或更小的均方根表面粗糙度(RMS)。可以使用机械抛光操作和化学蚀刻操作中的至少一种使施主衬底100的结合面和受主衬底110的结合面平滑。例如，化学机械平坦化(CMP)操作可用于使施主衬底100的结合面和受主衬底110的结合面平坦化、和/或减小施主衬底100的结合面和受主衬底110的结合面的表面粗糙度。
在使两个结合面平滑之后，可以使用本领域中已知的工艺来选择性地清洁和/或激活结合面。这种激活工艺可以用于以促进结合工艺和/或导致形成更强的键的方式改变结合面处的表面化学性质。
可以使结合面彼此直接物理接触，并且可以在局部区域中跨结合界面施加压力。可以在局部压力区附近开始原子间结合，并且结合波可以跨结合面之间的界面传播。
可选地，退火工艺可以被使用来加强结合。这种退火工艺可以包括在大约一百摄氏度(100℃)至大约四百摄氏度(400℃)的温度下，在熔炉中将已结合的施主衬底100和受主衬底110加热大约两分钟(2分钟)至大约十五小时(15小时)的时间。
可以在结合工艺之前在施主衬底100和受主衬底110两者之一或两者全部上设置绝缘层114(诸如，氧化物(例如，SiO2、Al2O3等)、氮化物、或氮氧化物等)，使得施主衬底100和受主衬底110两者之一或两者全部的结合面包括绝缘层114的表面。因此，在这些实施方式中，直接分子结合工艺可以包括氧化物对氧化物或氧化物对硅、或氧化物对硅锗的直接分子结合工艺。
该绝缘层114可以包括本领域通常所称的“埋置氧化物层”或“BOX”。该绝缘层114可以是晶体的或非晶的。虽然本公开的实施方式中也可以采用更厚或更薄的绝缘层114，但绝缘层114可以具有大约10nm到大约50nm之间的已结合结构中的平均层厚(如果在结合之前淀积在施主衬底100和受主基板110两者上，则可以包括两个绝缘层114的厚度)。
参照图3，在将施主衬底100和受主衬底110结合之后，可以沿着弱化区112(图1和图2)分开施主衬底100。通过加热施主衬底100和/或向施主衬底100施加机械力，可以沿着弱化区112分开或裂开施主衬底100。
如图3所示裂开施主衬底100时，提供了多层衬底120，该多层衬底120包括对多层衬底120的基底衬底进行限定的受主衬底110、对多层衬底120的埋置氧化物层进行限定的绝缘层114、位于埋置氧化物层114上方、该埋置氧化物层114与基底衬底110相反的一侧上的主半导体层106、以及位于主半导体层106上方、该主半导体层106的与埋置氧化物层114相反的一侧上的外延基层104的至少一部分。
图4所示的多层衬底120从图4所示的方位反转，用于后续处理。
多层衬底120的外延基层104的厚度可以通过如参照图3之前描述的，控制施主衬底100(图1)内的弱化区112的位置(即，深度)，和/或通过在沿着弱化区112裂开施主衬底100之后选择性地使多层衬底120的外延基层104的一部分变薄，而选择性地受控。例如，在一些实施方式中，在沿着弱化区112裂开施主衬底100之后，使用例如机械抛光操作和化学蚀刻操作中的至少一种来选择性地减小外延基层104的厚度。例如，化学机械平坦化(CMP)工艺可以用于在沿着弱化区112裂开施主衬底100之后将外延基层104的厚度减小到预定且选定的厚度。这样的处理也可以减小外延基层104的露出的主表面的表面粗糙度，并得到外延基层104的更均匀的厚度，这也可能是人们所期望的。
参照图5，第一掩模层122可以淀积或以其他方式设置在位于多层衬底120的第一区域124A内在外延基层104和主半导体层106的上方。该掩模层122可以不覆盖位于多层衬底120的第二区域124B内的外延基层104和主半导体层106。第一掩模层122可以至少大致连续地淀积在多层衬底120上，随后进行构图，以去除位于多层衬底120的第二区域124B内的掩模层122，使得外延基层104和主半导体层106在多层衬底120的第二区域124B内借助第一掩模层122而露出。
第一掩模层122可以包括单层掩模材料，或多层掩模材料。如下面所讨论的，第一掩模层122的组成被选择成抵抗由用于随后蚀刻和去除位于多层衬底120的第二区域124B内的掩模层122的蚀刻剂进行的蚀刻。例如，第一掩模层122可以包括氧化物(例如，SiO2、Al2O3等)、氮化物(例如Si3N4)、或氧氮化物(例如，氧氮化硅)。作为非限制性示例，在外延基层104包括SixGe1-x并且主半导体层106包括拉伸应变硅(sSi)的实施方式中，第一掩模层122可以包括多层掩模结构，该多层掩模结构包括第一层氧化物(例如，SiO2)、在第一层氧化物的与外延基层104相反的一侧上的氮化物层(例如，Si3N4)、以及在氮化物层的与第一层氧化物相反的一侧上的第二层氧化物(例如，SiO2)，使得氮化物层夹在第一层氧化物与第二层氧化物之间。
参照图6，在用第一掩模层122遮蔽多层衬底120的第一区域124A内的外延基层104和主半导体层106之后，可以从多层衬底120的第二区域124B去除外延基层104的露出部分。蚀刻工艺可以被使用来从第二区域124B中的主半导体层106上方去除外延基层104。
用于从第二区域124B中的主半导体层106去除外延基层104的蚀刻工艺可以包括湿法蚀刻工艺或者干法蚀刻工艺(例如，反应离子蚀刻(RIE)工艺)。蚀刻工艺可以包括各向同性或各向异性蚀刻工艺。可以选择蚀刻剂，以相对于主半导体层106选择性地蚀刻外延基层104，使得外延基层104优先被蚀刻工艺去除并且主半导体层106充当蚀刻阻挡层。在其他实施方式中，如果选择性地去除外延基层104而基本上不去除主半导体层106的蚀刻剂无法找到，则在去除了外延基层104时，则可简单地终止蚀刻工艺。
作为非限制性示例，在外延基层104包括SixGe1-x并且主半导体层106包括拉伸应变硅(sSi)的实施方式中，干法反应离子蚀刻(RIE)工艺可以被使用来去除外延基层104。包括氯(例如，Cl2)、氟(例如，CF4或SF6)、和/或溴(例如，HBr)反应性气体的卤素基化学物质可以在这种干法RIE工艺中用作蚀刻剂。RIE蚀刻工艺的蚀刻速率可以通过调节RIE蚀刻室内的气体比、压力和偏置功率而选择性地控制。例如，参见JournalofIntegratedCircuitsandSystems，2013年，第8卷，第2期，第104-109页)，MarceloS.B.Castro等人的SelectiveandAnisotropicDryEtchingofGeoverSi，其公开了这种RIE蚀刻工艺并且此处以引证的方式并入其全部内容。
在从多层衬底120的第二区域124B内的上覆主半导体层106去除外延基层104之后，然后可以从多层衬底120去除掩模层134。
参照图7，第二掩模层126可以淀积或以其它方式形成在多层衬底120的第二区域124B内所露出的主半导体层106上。该第二掩模层126不可以覆盖多层衬底120的第一区域124A内的外延基层104和主半导体层106。第二掩模层126可以至少大致连续地淀积在多层衬底120上，并随后进行构图以去除位于多层衬底120的第一区域124A中的掩模层122，使得外延基层104和主半导体层106通过多层衬底120的第一区域124A内的第一掩模层122而露出。
第二掩模层126可以包括单层掩模材料，或多层掩模材料。如下面参照图8A-图8C描述的，第二掩模层126的组成被选择成抵抗对位于多层衬底120的第一区域124A内的外延基层104和主半导体层106后续执行的原子扩散过程期间可以暴露于的环境条件。例如，第二掩模层126可以包括氧化物(例如，SiO2、Al2O3等)、氮化物(例如Si3N4)、或氧氮化物(例如，氧氮化硅)。作为非限制性示例，在外延基层104包括SixGe1-x并且主半导体层106包括拉伸应变硅(sSi)的实施方式中，第二掩模层126可以包括多层掩模结构，该多层掩模结构包括氧化物(例如，SiO2)层和在该氧化物层的与外延基层104相反的一侧上的氮化物(例如，Si3N4)层。
在用第二掩模层126遮蔽多层衬底120的第二区域124B内的主半导体层106之后，凝聚工艺(经常称为“热混合”工艺)或另一种工艺可以被使用来将元素从第一区域124A内的外延基层104扩散到下覆主半导体层106中，以相对于多层衬底120的第二区域124B内的主半导体层106中的应变水平，选择性地降低第一区域124A内的主半导体层106中的拉伸应变和/或增加其中的压缩应变。第二区域124B中存在第二掩模层126而不存在外延基层104可以防止元素扩散到第二区域124B内的主半导体层106中，使得在对多层衬底120的第一区域124A执行凝聚工艺期间主半导体层106中的应变保持不变。换句话说，仅可以对多层衬底120的第一区域124A，而不对多层衬底120的第二区域124B执行凝聚工艺。下面参照图8A-图8C对这种凝聚工艺进行描述。
图8A是图6所示的多层衬底120在第一区域124A内的一部分的放大图。凝聚工艺可以涉及在氧化气氛(例如，干燥的O2)中在高温下(例如，大约900℃至大约1150℃)在熔炉中使多层衬底120(在多层衬底120的第二区域124B内主半导体层106被掩蔽)经受氧化工艺。参照图8B，该氧化工艺可能导致在多层衬底120的表面处形成氧化物层136，并且可能导致元素从外延基层104扩散到多层衬底120的第一区域124A内的主半导体层106中。随着时间的推移，因为外延基层104的元素合并到所生长的氧化物层136中和/或扩散到并且合并到下覆主半导体层106中，所以外延基层104与主半导体层106之间的边界或界面可以变得不分开。
在主半导体层106包括拉伸应变硅(sSi)并且外延基层104包括SixGe1-x的实施方式中，氧化物层136可以包括二氧化硅(SiO2)，并且SixGe1-x外延基层104的锗可以扩散到主半导体层106的应变硅(sSi)中，这将sSi应变半导体层106转变成应变SiyGe1-y主半导体层106。氧化物层136可以在外延基层104的表面处形成，在厚度上生长到多层衬底120中，通过溶解的外延基层104并且到主半导体层106中。随着氧化物层136的厚度在锗凝聚工艺期间生长，如图8C所示，主半导体层106的厚度减小，并且主半导体层106中锗的浓度增加，直到获得在应变SiyGe1-y主半导体层106中具有期望浓度的锗的主半导体层106为止。锗扩散到主半导体层106中会得到引起主半导体层106内的任何的拉伸应变降低，并且可能会引起主半导体层106内的压缩应变增加。在凝聚工艺之后，第一区域124A内的主半导体层106会处于低于第二区域124B内的主半导体层106中的拉伸应变的拉伸应变状态，第一区域124A内的主半导体层106会处于无拉伸或压缩应变的至少大致处于弛豫状态，或位于第一区域124A内的主半导体层106可能处于压缩应变状态。
在执行凝聚工艺之后，氧化物层136可以选择性地被从位于多层衬底120的第一区域124A内的主半导体层106上方去除。氧化物层136可以使用例如，湿法或干法蚀刻工艺去除。
如通过比较图8A和图8C可以看出的，凝聚工艺会引起多层衬底120的第一区域124A内的主半导体层106的厚度减小。在一些实施方式中，在执行凝聚工艺并去除氧化物层136之后，在位于多层衬底120的第一区域124A内的主半导体层106上可以选择性地外延生长附加半导体材料，而不在位于多层衬底120的第二区域124B内的主半导体层106上外延生长该附加半导体材料。该附加半导体材料可以具有与位于多层衬底120的第一区域124A内的主半导体层106的下覆半导体材料相同的组成和应变状态。该附加半导体材料的选择性外延生长可以用于增加多层衬底120的第一区域124A内的主半导体层106的厚度，使得第一区域124A内的主半导体层106的厚度至少大致等于没有经受凝聚工艺的第二区域124B内的主半导体层106的厚度。
凝聚工艺会引起位于多层衬底120的第一区域124A内的主半导体层106内的空穴迁移率提高，这对于形成PMOS晶体管(诸如平面FET晶体管或具有包括多层衬底120的第一区域124A内的主半导体层106的区域的晶体管沟道结构的finFET晶体管等)可以是期望的。位于多层衬底120的第二区域124B内的主半导体层106可以保持处于拉伸应变的状态，这对于形成NMOS晶体管(诸如平面FET晶体管或具有包括多层衬底120的第二区域124B内的主半导体层106的区域的晶体管沟道结构的finFET晶体管等)可以是期望的。
因此，参照图9，在提供了多层衬底120之后，可以蚀刻多层衬底120，以限定各可以包括主半导体层106的一部分的鳍结构132。各个鳍结构132可以具有一定尺寸并被构造为在FinFET中使用。
蚀刻工艺可以通过下列步骤执行：例如，在多层衬底120上淀积掩模层；对该掩模层构图，以在期望蚀刻进入并蚀刻穿透外延基层104和主半导体层106的位置处包括开口；然后借助构图后的掩模层蚀刻主半导体层106。可以使用用于形成这种鳍结构132的本领域中已知的其他工艺，诸如间隔区限定的双构图(SDDP)工艺(本领域中还称为侧壁图像转印工艺)。
蚀刻工艺可以包括湿法蚀刻工艺或干法蚀刻工艺(例如，反应离子蚀刻(RIE)工艺)。蚀刻工艺可以包括各向异性蚀刻工艺，以提供具有大致垂直的侧壁的鳍结构132。可以选择蚀刻剂，以相对于上覆的BOX层114选择性地蚀刻外延基层104和主半导体层106，使得该BOX层114可以用作蚀刻停止层。
作为非限制性示例，在主半导体层106在第二区域124B内包括拉伸应变硅(sSi)，而在第一区域124A内包括压缩应变SiyGe1-y的实施方式中，可以采用使用包括氯(例如，Cl2)、氟(例如，CF4或SF6)和/或溴(例如，HBr)反应性气体的卤素基化学物质作为蚀刻剂的干法反应离子蚀刻(RIE)工艺。
鳍结构132可以包括旨在作为p型finFET晶体管的鳍的第一多个鳍132A和旨在作为n型finFET晶体管的鳍的第二多个鳍132B。第一多个鳍132A中的每一个可以包括位于多层衬底120的第一区域124A内的主半导体层106的一部分，并且第二多个鳍132B中的每一个可以包括位于多层衬底120的第二区域124B内的主半导体层106的一部分。结果，第一多个鳍结构132A相对于第二多个鳍结构132B可以处于不同的应变状态。特别是，第二多个鳍结构132B可以处于拉伸应变的状态，而第一多个鳍结构132A可以处于降低的拉伸应变状态(相对于第二多个鳍结构132B)、处于至少大致无拉伸或压缩应变的弛豫状态或处于压缩应变的状态。
在一些实施方式中，鳍结构132可以具有比鳍结构132的材料将自发弛豫或在后续处理期间在高温下弛豫的临界大小小的一个或更多个大小(例如，长度、宽度、或高度)。在一些实施方式中，鳍结构132可以被形成为具有大约30nm或更小、大约20nm或更小、或甚至大约15nm或更小的平均鳍宽W(如图10)。
在上文描述的方法中，如参照图1描述的，外延基层104可以用作基层，在该基层上最初外延生长主半导体层106，使得主半导体层106处于应变状态，并且如参照图8A至图8C描述的，外延基层104可以随后用于在凝聚工艺中改变主半导体层106的一部分的应变状态。
如上文所述，如参照图9描述的，第一多个鳍结构132A和第二多个鳍结构132B可以在共同的掩模和蚀刻工艺中一起形成。
由本文描述的方法形成的所得结构包括第一多个鳍结构132A和第二多个鳍结构132B，这些鳍结构132A和132B布置在埋置氧化物层114上方在埋置氧化物层114的与基底衬底110相反的一侧上的共用面。第一多个鳍结构132A中的每一个包括凝聚后的主半导体层106，该凝聚后的半导体层106包括两种或更多种元素(例如，硅和锗)。第二多个鳍结构132B中的每一个包括非凝聚主半导体层106。此外，第二多个鳍结构132B的鳍结构132具有不同于第一多个鳍结构132A的鳍结构132的晶体应变的晶体应变。例如，第二多个鳍结构132B的鳍结构132可以处于拉伸应变的状态，而第一多个鳍结构132A的鳍结构132可以处于降低的拉伸应变状态、弛豫应变状态(即，无应变)或压缩应变状态。
如上文所述形成第一多个鳍结构132A和第二多个鳍结构132B之后，可以形成包括第一多个鳍结构132A的第一多个PMOSfinFET晶体管，并且可以形成包括第二多个鳍结构132B的第二多个NMOSfinFET晶体管。
图10例示了可以使用根据本公开的实施方式的第一多个鳍结构132A和/或第二多个鳍结构132B来制造的finFET晶体管构造的非限制性简化示例实施方式。应当注意的是，finFET的许多不同构造是本领域中已知的并且可以根据本公开的实施方式采用，并且图10所示的finFET结构仅作为这种finFET结构的示例而阐述。
如图10所示，finFET晶体管140包括源区142、漏区144以及源区142与漏区144之间延伸的沟道。沟道被鳍132限定并且包括诸如第一鳍结构132A或第二鳍结构132B这样的鳍132。在一些实施方式中，源区142和漏区144可以包括鳍结构132的纵向端部，或由鳍结构132的纵向端部限定。导电栅极146在源区142与漏区144之间的鳍结构132的至少一部分上方延伸并邻近该至少一部分。栅极146可以经由介电材料148与鳍结构132分离。栅极146可以包括多层结构，并且可以包括半导电层和/或导电层。包括金属、金属化合物或这两者(诸如导电硅化物等)的低电阻层可以淀积在源区142和/或漏区144的上方，以形成与源区142和/或漏区144的电接触件。
有利的是，沟道中的拉应力可以提高NMOSfinFET晶体管的性能并降低阈值电压，同时沟道中降低的拉应力(例如，较小的拉应力、无拉伸或压应力、或压应力)可以提高PMOSfinFET晶体管的性能并降低阈值电压。对于一些功能，因为需要高性能，所以应变器件是有益的；而对于一些其他功能，性能并不同样重要，但高阈值电压是有益的。凭借本公开的实施方式，制造商可以选择性地将不同水平的应力和应变合并到共用finFET晶体管平面中的同一器件中的不同finFET晶体管的晶格中。
虽然上文公开的方法和结构与finFET结构有关地进行描述，但应当注意的是，本公开的附加实施方式可以涉及除了finFET结构之外的传统FET结构的形成，并且多个传统p型CMOSFET晶体管可以使用位于多层衬底120的第一区域124A内的主半导体层106来制造，并且多个传统n型CMOSFET晶体管可以使用位于多层衬底120的第二区域124B内的主半导体层106来制造。
另外，下面阐述本公开的非限制性示例实施方式。
实施方式1：一种制造半导体结构的方法，该方法包括以下步骤：提供多层衬底，该多层衬底包括基底衬底；埋置氧化物层，该埋置氧化物层在该基底衬底的表面之上；应变主半导体层，该应变主半导体层在该埋置氧化物层上方、该埋置氧化物层的与该基底衬底相反的一侧上；以及外延基层，该外延基层在该应变半导体层上方、该应变半导体层的与该埋置氧化物层相反的一侧上；在将元素不从外延基层扩散到位于多层衬底的第二区域内的应变主半导体层中的情况下，将元素从该外延基层扩散到该多层衬底的该第一区域内的该应变主半导体层中，并且增大在该第一区域内的该主半导体层中所扩散的元素的浓度，使得该第一区域内的该主半导体层中的应变状态不同于第二区域内的主半导体层中的应变状态；以及形成第一多个晶体管沟道结构和第二多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于多层衬底的第一区域内的主半导体层的一部分，并且第二多个晶体管沟道结构分别包括位于多层衬底的第二区域内的主半导体层的一部分。
实施方式2：根据实施方式1的方法，该方法还包括选择该应变半导体层，以包括应变硅。
实施方式3：根据实施方式2的方法，该方法还包括选择该应变半导体层，以包括拉伸应变硅。
实施方式4：根据实施方式1至3中任一实施方式的方法，该方法还包括选择该外延基层，以包括SixGe1-x，其中，x从大约0.01到大约0.99，并且其中，从该外延基层将元素扩散到应变主半导体层中包括将锗扩散到位于该多层衬底的该第一区域内的该应变主半导体层中。
实施方式5：根据实施方式1至4中任一实施方式的方法，其中，形成第一多个晶体管沟道结构和形成该第二多个晶体管沟道结构包括蚀刻穿透该主半导体层并且限定鳍结构，各个该鳍结构包括该主半导体层的一部分，并且各个该鳍结构具有一定尺寸并被构造为在FinFET中使用。
实施方式6：根据实施方式1至5中任一实施方式的方法，其中，提供该多层衬底包括：在施主衬底上方的该外延基层上外延生长该应变半导体层，以形成施主结构；将离子注入到该施主结构中并在该施主结构内形成弱化区；将该施主结构结合到包括该基底衬底的受主衬底；以及沿着该弱化区分开该施主结构，以将该应变半导体层和外延基层转移到该基底衬底。
实施方式7：根据实施方式6的方法，其中，将该施主结构结合到该受主衬底包括在该施主结构和该受主衬底两者之一或这两者上设置氧化物层，以及使用直接结合工艺将该施主结构结合到该受主衬底。
实施方式8：根据实施方式6或7的方法，该方法还包括在包括该外延基层的该施主衬底的大致同质区域内布置该弱化区。
实施方式9：根据实施方式1至8中任一实施方式的方法，其中，将元素从该外延基层扩散到位于该多层衬底的该第一区域内的该应变主半导体层中包括使该多层衬底的该第一区域内的该主半导体层中的应变弛豫。
实施方式10：根据实施方式1至9中任一实施方式的方法，其中，将元素从该外延基层扩散到位于该多层衬底的该第一区域内的该应变主半导体层中包括在该多层衬底的该第一区域内的该主半导体层中引起压缩应变。
实施方式11：根据实施方式1至10中任一实施方式的方法，其中，将元素从该外延基层扩散到位于该多层衬底的该第一区域内的该应变主半导体层中包括提高该第一区域内的主半导体层内的空穴迁移率。
实施方式12：根据实施方式1至11中任一实施方式的方法，其中，将元素从该外延基层扩散到该多层衬底的该第一区域内的该应变主半导体层中包括在该多层衬底的该第一区域内的主半导体层上执行凝聚工艺。
实施方式13：根据实施方式12的方法，其中，在该多层衬底的该第一区域内的该主半导体层上执行凝聚工艺包括使该多层衬底的该第一区域内的该主半导体层的一部分氧化。
实施方式14：根据实施方式1至13中任一实施方式的方法，该方法还包括形成包括该第一多个晶体管沟道结构的多个p型FET晶体管，以及形成包括该第二多个晶体管沟道结构的多个n型FET晶体管。
实施方式15：一种制造半导体结构的方法，该方法包括以下步骤：提供多层衬底，该多层衬底包括基底衬底；埋置氧化物层，该埋置氧化物层在基底衬底的表面之上；应变主半导体层，该应变主半导体层在埋置氧化物层上方、与基底衬底相反的一侧上；以及外延基层，该外延基层在应变半导体层上方、与埋置氧化物层相反的一侧上；用第一掩模层遮蔽多层衬底的第一区域，并且从多层衬底的第二区域去除外延基层的一部分；从多层衬底的第一区域去除第一掩模层，并且用第二掩模层遮蔽多层衬底的第二区域；在将元素不扩散到位于所述多层衬底的所述第二区域内的所述应变主半导体层中的情况下，将元素从外延基层扩散到位于多层衬底的第一区域内的应变主半导体层中，并且改变多层衬底的第一区域内的主半导体层的应变状态；以及形成第一多个晶体管沟道结构和第二多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于多层衬底的第一区域内的主半导体层的一部分，并且第二多个晶体管沟道结构分别包括位于多层衬底的第二区域内的主半导体层的一部分。
实施方式16：根据实施方式15的方法，该方法还包括选择该应变半导体层，以包括拉伸应变硅。
实施方式17：实施方式15或实施方式16的方法，还包括选择该外延基层，以包括至少大致弛豫的SixGe1-x，其中，x从大约0.01到大约0.99，并且其中，将元素从该外延基层扩散到该多层衬底的该第一区域内的该应变主半导体层中包括将锗扩散到该多层衬底的该第一区域内的该应变主半导体层中。
实施方式18：实施方式15至17中任一实施方式的方法，该方法还包括形成包括该第一多个晶体管沟道结构的多个p型FET晶体管，以及形成包括该第二多个晶体管沟道结构的多个n型FET晶体管。
实施方式19：一种包括多层衬底的半导体结构，该半导体结构包括基底衬底；埋置氧化物层，该埋置氧化物层在基底衬底的表面之上；以及主半导体层，该主半导体层在埋置氧化物层之上、该埋置氧化物层的与基底衬底相反的一侧上，该多层衬底的第一区域内的该主半导体层的一部分包括SiyGe1-y，其中，y在大约0.20到大约0.99之间，并且位于多层衬底的第二区域内的主半导体层的一部分包括拉伸应变硅；其中，位于该多层衬底的该第一区域内的该主半导体层的该部分具有与位于该多层衬底的该第二区域内的该主半导体层的该部分的晶体应变不同的晶体应变。
实施方式20：根据实施方式19的半导体结构，该半导体结构还包括第一多个p型FET晶体管和第二多个n型FET晶体管，第一多个p型FET晶体管分别包括位于该多层衬底的该第一区域内的该主半导体层的一部分，并且第二多个n型FET晶体管分别包括位于该多层衬底的该第二区域内的该主半导体层的一部分。
上文描述的本公开的示例实施方式不限制由所附权利要求及其合法等同物的范围所限定的本发明的范围(因为这些实施方式仅是本发明的实施方式的示例)。任意等同的实施方式旨在在本发明的范围之内。事实上，公开的除了本文所示和描述的修改之外的各种修改(诸如所描述的元件的替换有用组合等)将根据描述对于本领域技术人员是显而易见的。换言之，本文描述的一个示例实施方式的一个或更多个特征可以与本文描述的另一个示例实施方式的一个或更多个特征组合，以提供公开的附加实施方式。这种修改和实施方式也旨在落入所附权利要求的范围之内。

Claims (20)

1.一种制造半导体结构的方法，该方法包括以下步骤：
提供多层衬底，该多层衬底包括：
基底衬底；
埋置氧化物层，该埋置氧化物层在所述基底衬底的表面上方；
应变主半导体层，该应变主半导体层在所述埋置氧化物层上方、所述埋置氧化物层的与所述基底衬底相反的一侧上；以及
外延基层，该外延基层在所述应变半导体层上方、所述应变半导体层的与所述埋置氧化物层相反的一侧上；
在不将元素从所述外延基层扩散到位于所述多层衬底的第二区域内的所述应变主半导体层中的情况下，将元素从所述外延基层扩散到位于所述多层衬底的第一区域内的所述应变主半导体层中，并且增大在所述第一区域内的所述主半导体层中的所扩散的元素的浓度，使得所述第一区域内的所述主半导体层中的应变状态不同于所述第二区域内的所述主半导体层中的应变状态；以及
形成第一多个晶体管沟道结构和第二多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于所述多层衬底的所述第一区域内的所述主半导体层的一部分，并且第二多个晶体管沟道结构分别包括位于所述多层衬底的所述第二区域内的所述主半导体层的一部分。
2.根据权利要求1所述的方法，所述方法还包括选择所述应变半导体层以包括应变硅。
3.根据权利要求2所述的方法，所述方法还包括选择所述应变半导体层以包括拉伸应变硅。
4.根据权利要求2所述的方法，所述方法还包括选择所述外延基层以包括SixGe1-x，其中，x从大约0.01到大约0.99，并且其中，将元素从所述外延基层扩散到所述应变主半导体层中的步骤包括将锗扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中。
5.根据权利要求1所述的方法，其中，形成所述第一多个晶体管沟道结构以及形成所述第二多个晶体管沟道结构的步骤包括蚀刻穿透所述主半导体层并且限定鳍结构，各个所述鳍结构包括所述主半导体层的一部分，并且各个所述鳍结构具有一定尺寸并被构造为在FinFET中使用。
6.根据权利要求1所述的方法，其中，提供所述多层衬底的步骤包括：
在施主衬底上方的所述外延基层上外延生长所述应变半导体层，以形成施主结构；
将离子注入到所述施主结构中并在所述施主结构内形成弱化区；
将所述施主结构结合到包括所述基底衬底的受主衬底；以及
沿着所述弱化区分开所述施主结构，以将所述应变半导体层和所述外延基层转移到所述基底衬底。
7.根据权利要求6所述的方法，其中，将所述施主结构结合到所述受主衬底的步骤包括在所述施主结构和所述受主衬底之一或这两者上设置氧化物层，以及使用直接结合工艺将所述施主结构结合到所述受主衬底。
8.根据权利要求6所述的方法，所述方法还包括：在包括所述外延基层的所述施主衬底的大致同质区域内布置所述弱化区。
9.根据权利要求1所述的方法，其中，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中的步骤包括使所述多层衬底的所述第一区域内的所述主半导体层中的应变弛豫。
10.根据权利要求1所述的方法，其中，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中的步骤包括在所述多层衬底的所述第一区域内的所述主半导体层中引起压缩应变。
11.根据权利要求1所述的方法，其中，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中的步骤包括提高所述第一区域内的所述主半导体层内的空穴迁移率。
12.根据权利要求1所述的方法，其中，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中的步骤包括在所述多层衬底的所述第一区域内的所述主半导体层上执行凝聚工艺。
13.根据权利要求12所述的方法，其中，在所述多层衬底的所述第一区域内的所述主半导体层上执行凝聚工艺的步骤包括使所述多层衬底的所述第一区域内的所述主半导体层的一部分氧化。
14.根据权利要求1所述的方法，所述方法还包括：形成包括所述第一多个晶体管沟道结构的多个p型FET晶体管；以及形成包括所述第二多个晶体管沟道结构的多个n型FET晶体管。
15.一种制造半导体结构的方法，该方法包括以下步骤：
提供多层衬底，该多层衬底包括：
基底衬底；
埋置氧化物层，该埋置氧化物层在所述基底衬底的表面上方；
应变主半导体层，该应变主半导体层在所述埋置氧化物层上方、所述埋置氧化物层的与所述基底衬底相反的一侧上；以及
外延基层，该外延基层在所述应变半导体层上方、所述应变半导体层的与所述埋置氧化物层相反的一侧上；
用第一掩模层遮蔽所述多层衬底的第一区域，并且从所述多层衬底的第二区域去除所述外延基层的一部分；
从所述多层衬底的所述第一区域去除所述第一掩模层，并且用第二掩模层遮蔽所述多层衬底的所述第二区域；
在不将元素扩散到位于所述多层衬底的所述第二区域内的所述应变主半导体层中的情况下，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中，并且改变所述多层衬底的所述第一区域内的所述主半导体层的应变状态；以及
形成第一多个晶体管沟道结构和第二多个晶体管沟道结构，第一多个晶体管沟道结构分别包括位于所述多层衬底的所述第一区域内的所述主半导体层的一部分，并且第二多个晶体管沟道结构分别包括位于所述多层衬底的所述第二区域内的所述主半导体层的一部分。
16.根据权利要求15所述的方法，所述方法还包括选择所述应变半导体层以包括拉伸应变硅。
17.根据权利要求16所述的方法，所述方法还包括选择所述外延基层以包括至少大致弛豫的SixGe1-x，其中，x从大约0.01到大约0.99，并且其中，将元素从所述外延基层扩散到位于所述多层衬底的所述第一区域内的所述应变主半导体层中的步骤包括将锗扩散到所述多层衬底的所述第一区域内的所述应变主半导体层中。
18.根据权利要求17所述的方法，所述方法还包括：形成包括所述第一多个晶体管沟道结构的多个p型FET晶体管；以及形成包括所述第二多个晶体管沟道结构的多个n型FET晶体管。
19.一种包括多层衬底的半导体结构，该半导体结构包括：
基底衬底；
埋置氧化物层，该埋置氧化物层在所述基底衬底的表面上方；以及
主半导体层，该主半导体层在所述埋置氧化物层上方、所述埋置氧化物层的与所述基底衬底相反的一侧上，位于所述多层衬底的第一区域内的所述主半导体层的一部分包括SiyGe1-y，其中，y在大约0.20到大约0.99之间，并且位于所述多层衬底的第二区域内的所述主半导体层的一部分包括拉伸应变硅；
其中，位于所述多层衬底的所述第一区域内的所述主半导体层的所述部分具有与位于所述多层衬底的所述第二区域内的所述主半导体层的所述部分的晶体应变不同的晶体应变。
20.根据权利要求19所述的半导体结构，所述半导体结构还包括第一多个p型FET晶体管和第二多个n型FET晶体管，第一多个p型FET晶体管分别包括位于所述多层衬底的所述第一区域内的所述主半导体层的一部分，并且第二多个n型FET晶体管分别包括位于所述多层衬底的所述第二区域内的所述主半导体层的一部分。
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