JP2016063224A - 異なる歪み状態を有するフィン構造を含む半導体構造を作製するための方法及び関連する半導体構造 - Google Patents
異なる歪み状態を有するフィン構造を含む半導体構造を作製するための方法及び関連する半導体構造 Download PDFInfo
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Abstract
Description
図1〜図4は、本開示の実施形態により用いられてもよい多層基板の作製を示す簡略化された概略断面図である。
実施形態1
ベース基板、ベース基板の表面上の埋め込み酸化物層、ベース基板とは反対側の埋め込み酸化物層上の歪み主半導体層、及び埋め込み酸化物層とは反対側の歪み半導体層上のエピタキシャルベース層を含む、多層基板を用意するステップと、第1の領域内の主半導体層の歪み状態が第2の領域内の主半導体層の歪み状態と異なるように、元素をエピタキシャルベース層から多層基板の第2の領域内の歪み主半導体層へは拡散させずに、元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させ、第1の領域内の主半導体層の拡散させた元素の濃度を高くするステップと、多層基板の第1の領域内の主半導体層の一部をそれぞれが備える第1の複数のトランジスタチャネル構造、及び多層基板の第2の領域内の主半導体層の一部をそれぞれが備える第2の複数のトランジスタチャネル構造を形成するステップとを含む、半導体構造を作製する方法。
実施形態2
歪みシリコンを含むように歪み半導体層を選択するステップをさらに含む、実施形態1に記載の方法。
実施形態3
引張り歪みシリコンを含むように歪み半導体層を選択するステップをさらに含む、実施形態2に記載の方法。
実施形態4
SixGe1−xを含むようにエピタキシャルベース層を選択するステップであって、xが約0.01〜約0.99であるステップをさらに含み、元素をエピタキシャルベース層から歪み主半導体層へ拡散させるステップが、多層基板の第1の領域内の歪み主半導体層へゲルマニウムを拡散させるステップを含む、ステップをさらに含む、実施形態1〜3のいずれか一項に記載の方法。
実施形態5
第1の複数のトランジスタチャネル構造を形成するステップ及び第2の複数のトランジスタチャネル構造を形成するステップが、主半導体層を貫いてエッチングするステップ、及びそれぞれが主半導体層の一部を備え、それぞれがフィンFETで使用するためにサイズが調整され、構成されているフィン構造を規定するステップを含む、実施形態1〜4のいずれか一項に記載の方法。
実施形態6
多層基板を用意するステップが、歪み半導体層をドナー基板上のエピタキシャルベース層にエピタキシャル成長させてドナー構造を形成するステップと、ドナー構造にイオンを注入し、ドナー構造内に脆弱ゾーンを形成するステップと、ドナー構造を、ベース基板を備えるレシーバ基板に接合するステップと、脆弱ゾーンに沿ってドナー構造を劈開して、歪み半導体層及びエピタキシャルベース層をベース基板に移しかえるステップと、を含む、実施形態1〜5のいずれか一項に記載の方法。
実施形態7
ドナー構造をレシーバ基板に接合するステップが、ドナー構造及びレシーバ基板の1つ又は両方に酸化物層を設けるステップ、及び直接接合プロセスを使用してドナー構造をレシーバ基板に接合するステップを含む、実施形態6に記載の方法。
実施形態8
エピタキシャルベース層を備えるドナー基板の実質的に均質の領域内に脆弱ゾーンを配置するステップをさらに含む、実施形態6又は実施形態7に記載の方法。
実施形態9
元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させるステップが、多層基板の第1の領域内の主半導体層の歪みを緩和するステップを含む、実施形態1〜8のいずれか一項に記載の方法。
実施形態10
元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させるステップが、多層基板の第1の領域内の主半導体層の圧縮歪みを引き起こすステップを含む、実施形態1〜9のいずれか一項に記載の方法。
実施形態11
元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させるステップが、第1の領域内の主半導体層内の正孔移動度を増加させるステップを含む、実施形態1〜10のいずれか一項に記載の方法。
実施形態12
元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させるステップが、多層基板の第1の領域内の主半導体層に対する凝縮プロセスを実行するステップを含む、実施形態1〜11のいずれか一項に記載の方法。
実施形態13
多層基板の第1の領域内の主半導体層に対する凝縮プロセスを実行するステップが、多層基板の第1の領域内の主半導体層の一部を酸化させるステップを含む、実施形態12に記載の方法。
実施形態14
第1の複数のトランジスタチャネル構造を備える複数のp型FETトランジスタを形成するステップ、及び第2の複数のトランジスタチャネル構造を備える複数のn型FETトランジスタを形成するステップをさらに含む、実施形態1〜13のいずれか一項に記載の方法。
実施形態15
ベース基板、ベース基板の表面上の埋め込み酸化物層、ベース基板とは反対側の埋め込み酸化物層上の歪み主半導体層、及び埋め込み酸化物層とは反対側の歪み半導体層上のエピタキシャルベース層を含む、多層基板を用意するステップと、第1のマスク層によって多層基板の第1の領域をマスクし多層基板の第2の領域からエピタキシャルベース層の一部を除去するステップと、多層基板の第1の領域から第1のマスク層を除去し第2のマスク層によって多層基板の第2の領域をマスクするステップと、元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させ、元素を多層基板の第2の領域内の歪み主半導体層へは拡散させずに多層基板の第1の領域内の主半導体層の歪み状態を変えるステップと、多層基板の第1の領域内の主半導体層の一部をそれぞれが備える第1の複数のトランジスタチャネル構造、及び多層基板の第2の領域内の主半導体層の一部をそれぞれが備える第2の複数のトランジスタチャネル構造を形成するステップと、を含む、半導体構造を作製する方法。
実施形態16
引張り歪みシリコンを含むように歪み半導体層を選択するステップをさらに含む、実施形態15に記載の方法。
実施形態17
少なくとも実質的に緩和したSixGe1−xを含むようにエピタキシャルベース層を選択するステップであって、xが約0.01〜約0.99であるステップをさらに含み、元素をエピタキシャルベース層から多層基板の第1の領域内の歪み主半導体層へ拡散させるステップが、多層基板の第1の領域内の歪み主半導体層へゲルマニウムを拡散させるステップを含む、実施形態15又は実施形態16に記載の方法。
実施形態18
第1の複数のトランジスタチャネル構造を備える複数のp型FETトランジスタを形成するステップ、及び第2の複数のトランジスタチャネル構造を備える複数のn型FETトランジスタを形成するステップをさらに含む、実施形態15〜17のいずれか一項に記載の方法。
実施形態19
ベース基板、ベース基板の表面上の埋め込み酸化物層、及びベース基板とは反対側の埋め込み酸化物層上の主半導体層であって、多層基板の第1の領域内の主半導体層の一部が、yが約0.20〜約0.99であるSiyGe1−yを含み、多層基板の第2の領域内の主半導体層の一部が引張り歪みSiを含む、主半導体層と、を備え、多層基板の第1の領域内の主半導体層の一部が、多層基板の第2の領域内の主半導体層の一部の結晶学的な歪みと異なる結晶学的な歪みを有する、多層基板を含む半導体構造。
実施形態20
多層基板の第1の領域内の主半導体層の一部をそれぞれが備える第1の複数のp型FETトランジスタ、及び多層基板の第2の領域内の主半導体層の一部をそれぞれが備える第2の複数のn型FETトランジスタをさらに備える、実施形態19に記載の半導体構造。
102 バルク材料
104 エピタキシャルベース層
106 歪み半導体層
108 バッファ層
109 矢印
110 レシーバ基板
112 脆弱ゾーン
114 埋め込み酸化物層
120 多層基板
122 マスク層
124A 第1の領域
124B 第2の領域
126 マスク層
136 酸化物層
Claims (20)
- ベース基板、
前記ベース基板の表面上の埋め込み酸化物層、
前記ベース基板とは反対側の前記埋め込み酸化物層上の歪み主半導体層、及び
前記埋め込み酸化物層とは反対側の前記歪み半導体層上のエピタキシャルベース層
を含む、多層基板を用意するステップと、
第1の領域内の前記主半導体層の歪み状態が第2の領域内の前記主半導体層の歪み状態と異なるように、元素を前記エピタキシャルベース層から前記多層基板の前記第2の領域内の前記歪み主半導体層へは拡散させずに、元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させ、前記第1の領域内の前記主半導体層の前記拡散させた元素の濃度を高くするステップと、
前記多層基板の前記第1の領域内の前記主半導体層の一部をそれぞれが備える第1の複数のトランジスタチャネル構造、及び前記多層基板の前記第2の領域内の前記主半導体層の一部をそれぞれが備える第2の複数のトランジスタチャネル構造を形成するステップと、
を含む、半導体構造を作製する方法。 - 歪みシリコンを含むように前記歪み半導体層を選択するステップをさらに含む、請求項1に記載の方法。
- 引張り歪みシリコンを含むように前記歪み半導体層を選択するステップをさらに含む、請求項2記載の方法。
- SixGe1−xを含むように前記エピタキシャルベース層を選択するステップであって、xが約0.01〜約0.99であるステップをさらに含み、元素を前記エピタキシャルベース層から前記歪み主半導体層へ拡散させるステップが、前記多層基板の前記第1の領域内の前記歪み主半導体層へゲルマニウムを拡散させるステップを含む、請求項2に記載の方法。
- 第1の複数のトランジスタチャネル構造を形成するステップ及び前記第2の複数のトランジスタチャネル構造を形成するステップが、前記主半導体層を貫いてエッチングするステップ及びそれぞれが前記主半導体層の一部を備え、それぞれがフィンFETで使用するためにサイズが調整され、構成されているフィン構造を規定するステップを含む、請求項1に記載の方法。
- 前記多層基板を用意するステップが、
前記歪み半導体層をドナー基板上の前記エピタキシャルベース層にエピタキシャル成長させてドナー構造を形成するステップと、
前記ドナー構造にイオンを注入し、前記ドナー構造内に脆弱ゾーンを形成するステップと、
前記ドナー構造を、前記ベース基板を備えるレシーバ基板に接合するステップと、
前記脆弱ゾーンに沿って前記ドナー構造を劈開して、前記歪み半導体層及び前記エピタキシャルベース層を前記ベース基板に移しかえるステップと、
を含む、請求項1に記載の方法。 - 前記ドナー構造を前記レシーバ基板に接合するステップが、前記ドナー構造及び前記レシーバ基板の1つ又は両方に酸化物層を設けるステップ、及び直接接合プロセスを使用して前記ドナー構造を前記レシーバ基板に接合するステップを含む、請求項6に記載の方法。
- 前記エピタキシャルベース層を備える前記ドナー基板の実質的に均質の領域内に前記脆弱ゾーンを配置するステップをさらに含む、請求項6に記載の方法。
- 元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させるステップが、前記多層基板の前記第1の領域内の前記主半導体層の歪みを緩和するステップを含む、請求項1に記載の方法。
- 元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させるステップが、前記多層基板の前記第1の領域内の前記主半導体層の圧縮歪みを引き起こすステップを含む、請求項1項に記載の方法。
- 元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させるステップが、前記第1の領域内の前記主半導体層内の正孔移動度を増加させるステップを含む、請求項1に記載の方法。
- 元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させるステップが、前記多層基板の前記第1の領域内の前記主半導体層に対する凝縮プロセスを実行するステップを含む、請求項1に記載の方法。
- 前記多層基板の前記第1の領域内の前記主半導体層に対する凝縮プロセスを実行するステップが、前記多層基板の前記第1の領域内の前記主半導体層の一部を酸化させるステップを含む、請求項12に記載の方法。
- 前記第1の複数のトランジスタチャネル構造を備える複数のp型FETトランジスタを形成するステップ、及び前記第2の複数のトランジスタチャネル構造を備える複数のn型FETトランジスタを形成するステップをさらに含む、請求項1に記載の方法。
- ベース基板、
前記ベース基板の表面上の埋め込み酸化物層、
前記ベース基板とは反対側の前記埋め込み酸化物層上の歪み主半導体層、及び
前記埋め込み酸化物層とは反対側の前記歪み半導体層上のエピタキシャルベース層
を含む、多層基板を用意するステップと、
第1のマスク層によって前記多層基板の第1の領域をマスクし前記多層基板の第2の領域から前記エピタキシャルベース層の一部を除去するステップと、
前記多層基板の前記第1の領域から前記第1のマスク層を除去し、第2のマスク層によって前記多層基板の前記第2の領域をマスクするステップと、
元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させ、元素を前記多層基板の前記第2の領域内の前記歪み主半導体層へは拡散させずに前記多層基板の前記第1の領域内の前記主半導体層の歪み状態を変えるステップと、
前記多層基板の前記第1の領域内の前記主半導体層の一部をそれぞれが備える第1の複数のトランジスタチャネル構造、及び前記多層基板の前記第2の領域内の前記主半導体層の一部をそれぞれが備える第2の複数のトランジスタチャネル構造を形成するステップと、
を含む、半導体構造を作製する方法。 - 引張り歪みシリコンを含むように前記歪み半導体層を選択するステップをさらに含む、請求項15に記載の方法。
- 少なくとも実質的に緩和したSixGe1−xを含むように前記エピタキシャルベース層を選択するステップであって、xが約0.01〜約0.99であるステップをさらに含み、元素を前記エピタキシャルベース層から前記多層基板の前記第1の領域内の前記歪み主半導体層へ拡散させるステップが、前記多層基板の前記第1の領域内の前記歪み主半導体層へゲルマニウムを拡散させるステップを含む、請求項16に記載の方法。
- 前記第1の複数のトランジスタチャネル構造を備える複数のp型FETトランジスタを形成するステップ、及び前記第2の複数のトランジスタチャネル構造を備える複数のn型FETトランジスタを形成するステップをさらに含む、請求項17に記載の方法。
- ベース基板、
前記ベース基板の表面上の埋め込み酸化物層、及び
前記ベース基板とは反対側の前記埋め込み酸化物層上の主半導体層であって、前記多層基板の第1の領域内の前記主半導体層の一部が、yが約0.20〜約0.99であるSiyGe1−yを含み、前記多層基板の第2の領域内の前記主半導体層の一部が引張り歪みSiを含む、主半導体層、
を備え、
前記多層基板の前記第1の領域内の前記主半導体層の前記一部が、前記多層基板の前記第2の領域内の前記主半導体層の前記一部の結晶学的な歪みと異なる結晶学的な歪みを有する、
多層基板を含む半導体構造。 - 前記多層基板の前記第1の領域内の前記主半導体層の一部をそれぞれが備える第1の複数のp型FETトランジスタ、及び前記多層基板の前記第2の領域内の前記主半導体層の一部をそれぞれが備える第2の複数のn型FETトランジスタをさらに備える、請求項19に記載の半導体構造。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020511777A (ja) * | 2017-03-21 | 2020-04-16 | ソイテックSoitec | 特に、正面側型撮像装置のための、セミコンダクタオンインシュレータ型構造、及びこのような構造を製作する方法 |
KR20210021488A (ko) * | 2018-06-21 | 2021-02-26 | 소이텍 | 전면 이미지 센서 및 이러한 이미지 센서를 제조하기 위한 프로세스 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9219150B1 (en) | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
CN105845546B (zh) * | 2015-01-15 | 2019-11-05 | 联华电子股份有限公司 | 照光的外延制作工艺 |
US10141229B2 (en) * | 2016-09-29 | 2018-11-27 | Globalfoundries Inc. | Process for forming semiconductor layers of different thickness in FDSOI technologies |
US10679901B2 (en) | 2018-08-14 | 2020-06-09 | International Business Machines Corporation | Differing device characteristics on a single wafer by selective etch |
CN109297778B (zh) * | 2018-10-08 | 2021-10-19 | 山东一诺威新材料有限公司 | 一种用于组合聚醚的高通量配样装置 |
US11164867B2 (en) * | 2019-08-07 | 2021-11-02 | Globalfoundries U.S. Inc. | Fin-type field-effect transistors over one or more buried polycrystalline layers |
CN113764347B (zh) * | 2021-09-07 | 2023-06-16 | 上海集成电路装备材料产业创新中心有限公司 | 鳍式半导体器件的制备方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005013375A1 (ja) * | 2003-08-05 | 2005-02-10 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP2006049673A (ja) * | 2004-08-06 | 2006-02-16 | Seiko Epson Corp | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 |
JP2007180285A (ja) * | 2005-12-28 | 2007-07-12 | Siltronic Ag | Sgoi基板の製造方法 |
JP2008004910A (ja) * | 2006-06-23 | 2008-01-10 | Interuniv Micro Electronica Centrum Vzw | 歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス |
JP2009094229A (ja) * | 2007-10-05 | 2009-04-30 | Toshiba Corp | 電界効果トランジスタおよびその製造方法 |
US20090227078A1 (en) * | 2008-03-06 | 2009-09-10 | Ding-Yuan Chen | CMOS Devices having Dual High-Mobility Channels |
JP2012191170A (ja) * | 2011-03-09 | 2012-10-04 | Soytec | Ge・オン・III/V族・オン・インシュレータ構造を形成するための方法 |
Family Cites Families (59)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US39484A (en) | 1863-08-11 | Improved smoothing-iron | ||
JPS5856409A (ja) | 1981-09-30 | 1983-04-04 | Toshiba Corp | 半導体装置の製造方法 |
US4899202A (en) | 1988-07-08 | 1990-02-06 | Texas Instruments Incorporated | High performance silicon-on-insulator transistor with body node to source node connection |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US6399970B2 (en) * | 1996-09-17 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | FET having a Si/SiGeC heterojunction channel |
KR100218538B1 (ko) | 1996-10-17 | 1999-09-01 | 김덕중 | 반도체 기판 및 그 제조 방법 |
FR2755537B1 (fr) | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2795865B1 (fr) | 1999-06-30 | 2001-08-17 | Commissariat Energie Atomique | Procede de realisation d'un film mince utilisant une mise sous pression |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
FR2818010B1 (fr) | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
WO2004038778A1 (en) | 2002-10-22 | 2004-05-06 | Amberwave Systems Corporation | Gate material for semiconductor device fabrication |
US7018909B2 (en) | 2003-02-28 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Forming structures that include a relaxed or pseudo-relaxed layer on a substrate |
US6963078B2 (en) | 2003-03-15 | 2005-11-08 | International Business Machines Corporation | Dual strain-state SiGe layers for microelectronics |
JP2004320000A (ja) | 2003-04-02 | 2004-11-11 | Sumitomo Mitsubishi Silicon Corp | 歪Si−SOI基板の製造方法 |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US7247534B2 (en) * | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
WO2005112129A1 (ja) * | 2004-05-13 | 2005-11-24 | Fujitsu Limited | 半導体装置およびその製造方法、半導体基板の製造方法 |
JP4157496B2 (ja) | 2004-06-08 | 2008-10-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
US20060113603A1 (en) | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
US7229901B2 (en) | 2004-12-16 | 2007-06-12 | Wisconsin Alumni Research Foundation | Fabrication of strained heterojunction structures |
JP4481181B2 (ja) | 2005-01-27 | 2010-06-16 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7282402B2 (en) | 2005-03-30 | 2007-10-16 | Freescale Semiconductor, Inc. | Method of making a dual strained channel semiconductor device |
DE102005052357A1 (de) * | 2005-09-01 | 2007-03-15 | Osram Opto Semiconductors Gmbh | Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement |
JP2007180402A (ja) | 2005-12-28 | 2007-07-12 | Toshiba Corp | 半導体装置及びその製造方法 |
US7468313B2 (en) | 2006-05-30 | 2008-12-23 | Freescale Semiconductor, Inc. | Engineering strain in thick strained-SOI substrates |
US8962447B2 (en) | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
US7888197B2 (en) * | 2007-01-11 | 2011-02-15 | International Business Machines Corporation | Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer |
US7528056B2 (en) | 2007-01-12 | 2009-05-05 | International Business Machines Corporation | Low-cost strained SOI substrate for high-performance CMOS technology |
US20080179636A1 (en) | 2007-01-27 | 2008-07-31 | International Business Machines Corporation | N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers |
FR2913527B1 (fr) * | 2007-03-05 | 2009-05-22 | Commissariat Energie Atomique | Procede de fabrication d'un substrat mixte et utilisation du substrat pour la realisation de circuits cmos |
DE102007030054B4 (de) | 2007-06-29 | 2009-04-16 | Advanced Micro Devices, Inc., Sunnyvale | Transistor mit reduziertem Gatewiderstand und verbesserter Verspannungsübertragungseffizienz und Verfahren zur Herstellung desselben |
US7524740B1 (en) | 2008-04-24 | 2009-04-28 | International Business Machines Corporation | Localized strain relaxation for strained Si directly on insulator |
US8003454B2 (en) | 2008-05-22 | 2011-08-23 | Freescale Semiconductor, Inc. | CMOS process with optimized PMOS and NMOS transistor devices |
EP2151852B1 (en) | 2008-08-06 | 2020-01-15 | Soitec | Relaxation and transfer of strained layers |
EP2324488B1 (en) * | 2008-08-27 | 2013-02-13 | Soitec | Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters |
CN102117750B (zh) * | 2009-12-30 | 2012-08-29 | 中国科学院微电子研究所 | Mosfet结构及其制作方法 |
US8169025B2 (en) | 2010-01-19 | 2012-05-01 | International Business Machines Corporation | Strained CMOS device, circuit and method of fabrication |
US8395213B2 (en) | 2010-08-27 | 2013-03-12 | Acorn Technologies, Inc. | Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer |
US8124470B1 (en) | 2010-09-29 | 2012-02-28 | International Business Machines Corporation | Strained thin body semiconductor-on-insulator substrate and device |
US20120276695A1 (en) | 2011-04-29 | 2012-11-01 | International Business Machines Corporation | Strained thin body CMOS with Si:C and SiGe stressor |
US9761666B2 (en) * | 2011-06-16 | 2017-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel field effect transistor |
CN102881694A (zh) | 2011-07-14 | 2013-01-16 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
US8791502B2 (en) * | 2011-10-09 | 2014-07-29 | The Institute of Microelectronics Chinese Academy of Science | Semiconductor device and method of manufacturing the same |
US20130175579A1 (en) * | 2012-01-10 | 2013-07-11 | International Business Machines Corporation | Transistor with recessed channel and raised source/drain |
US20130277747A1 (en) | 2012-04-24 | 2013-10-24 | Stmicroelectronics, Inc. | Transistor having a stressed body |
US8847315B2 (en) * | 2012-05-07 | 2014-09-30 | Qualcomm Incorporated | Complementary metal-oxide-semiconductor (CMOS) device and method |
KR101909204B1 (ko) * | 2012-06-25 | 2018-10-17 | 삼성전자 주식회사 | 내장된 스트레인-유도 패턴을 갖는 반도체 소자 및 그 형성 방법 |
EP2682983B1 (en) | 2012-07-03 | 2016-08-31 | Imec | CMOS device comprising silicon and germanium and method for manufacturing thereof |
US8653599B1 (en) | 2012-11-16 | 2014-02-18 | International Business Machines Corporation | Strained SiGe nanowire having (111)-oriented sidewalls |
US20140167162A1 (en) * | 2012-12-13 | 2014-06-19 | International Business Machines Corporation | Finfet with merge-free fins |
US8901607B2 (en) * | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US8927363B2 (en) | 2013-05-17 | 2015-01-06 | International Business Machines Corporation | Integrating channel SiGe into pFET structures |
US9209301B1 (en) | 2014-09-18 | 2015-12-08 | Soitec | Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers |
US9165945B1 (en) | 2014-09-18 | 2015-10-20 | Soitec | Method for fabricating semiconductor structures including transistor channels having different strain states, and related semiconductor structures |
US9219150B1 (en) | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
-
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-
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2005013375A1 (ja) * | 2003-08-05 | 2005-02-10 | Fujitsu Limited | 半導体装置及びその製造方法 |
JP2006049673A (ja) * | 2004-08-06 | 2006-02-16 | Seiko Epson Corp | 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法 |
JP2007180285A (ja) * | 2005-12-28 | 2007-07-12 | Siltronic Ag | Sgoi基板の製造方法 |
JP2008004910A (ja) * | 2006-06-23 | 2008-01-10 | Interuniv Micro Electronica Centrum Vzw | 歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス |
JP2009094229A (ja) * | 2007-10-05 | 2009-04-30 | Toshiba Corp | 電界効果トランジスタおよびその製造方法 |
US20090227078A1 (en) * | 2008-03-06 | 2009-09-10 | Ding-Yuan Chen | CMOS Devices having Dual High-Mobility Channels |
JP2012191170A (ja) * | 2011-03-09 | 2012-10-04 | Soytec | Ge・オン・III/V族・オン・インシュレータ構造を形成するための方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020511777A (ja) * | 2017-03-21 | 2020-04-16 | ソイテックSoitec | 特に、正面側型撮像装置のための、セミコンダクタオンインシュレータ型構造、及びこのような構造を製作する方法 |
JP7332158B2 (ja) | 2017-03-21 | 2023-08-23 | ソイテック | 特に、正面側型撮像装置のための、セミコンダクタオンインシュレータ型構造、及びこのような構造を製作する方法 |
KR20210021488A (ko) * | 2018-06-21 | 2021-02-26 | 소이텍 | 전면 이미지 센서 및 이러한 이미지 센서를 제조하기 위한 프로세스 |
JP2021527954A (ja) * | 2018-06-21 | 2021-10-14 | ソイテックSoitec | 前面撮像素子及びそのような撮像素子を製造するための方法 |
JP7467805B2 (ja) | 2018-06-21 | 2024-04-16 | ソイテック | 前面撮像素子及びそのような撮像素子を製造するための方法 |
KR102666552B1 (ko) * | 2018-06-21 | 2024-05-20 | 소이텍 | 전면 이미지 센서 및 이러한 이미지 센서를 제조하기 위한 프로세스 |
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DE102015217930A1 (de) | 2016-04-07 |
US20160268430A1 (en) | 2016-09-15 |
US9349865B2 (en) | 2016-05-24 |
JP2020202391A (ja) | 2020-12-17 |
JP6786755B2 (ja) | 2020-11-18 |
FR3026224B1 (fr) | 2018-06-01 |
KR20160033636A (ko) | 2016-03-28 |
US9818874B2 (en) | 2017-11-14 |
US20160087100A1 (en) | 2016-03-24 |
KR102465268B1 (ko) | 2022-11-10 |
TW201622106A (zh) | 2016-06-16 |
CN105448665A (zh) | 2016-03-30 |
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US9219150B1 (en) | 2015-12-22 |
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