JP5160080B2 - 歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス - Google Patents
歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス Download PDFInfo
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- JP5160080B2 JP5160080B2 JP2006331353A JP2006331353A JP5160080B2 JP 5160080 B2 JP5160080 B2 JP 5160080B2 JP 2006331353 A JP2006331353 A JP 2006331353A JP 2006331353 A JP2006331353 A JP 2006331353A JP 5160080 B2 JP5160080 B2 JP 5160080B2
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- 238000000034 method Methods 0.000 title claims description 58
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000001257 hydrogen Substances 0.000 claims description 71
- 229910052739 hydrogen Inorganic materials 0.000 claims description 71
- 239000000758 substrate Substances 0.000 claims description 67
- 238000000137 annealing Methods 0.000 claims description 64
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 63
- 230000004888 barrier function Effects 0.000 claims description 61
- 238000009792 diffusion process Methods 0.000 claims description 61
- 239000000463 material Substances 0.000 claims description 53
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- 238000000059 patterning Methods 0.000 claims description 13
- 239000012212 insulator Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 127
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 49
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 30
- 230000008569 process Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 150000002431 hydrogen Chemical class 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 239000002344 surface layer Substances 0.000 description 6
- 238000003631 wet chemical etching Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 230000000116 mitigating effect Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000007858 starting material Substances 0.000 description 3
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003841 Raman measurement Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
J. Wesler et al. "NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures", Electron Devices Meeting, 1992 Technical Digest (Dec. 13, 1992) pp. 31.7.1-31.7.3
Claims (19)
- マルチゲートデバイス中の歪を緩和する方法であって、
歪材料を含む基板を提供する工程と、
該歪材料中に、複数のフィンをパターニングする工程と、
少なくとも1つのフィンを含む第1領域を規定する工程と、
少なくとも1つのフィンを含む第2領域を規定する工程と、
該第1領域上に、拡散バリア層を形成する工程と、
該第2領域の該少なくとも1つのフィンの該歪材料が緩和されるように、水素アニールを行う工程と、を含み、
該拡散バリア層が所定の厚みを有し、該厚みが該水素アニールのアニールパラメータに依存する方法。 - 上記第1領域の少なくとも1つのフィンの歪材料が、上記水素アニール工程後に、部分的に緩和される請求項1にかかる方法。
- 上記第1領域の少なくとも1つのフィンの歪材料が、上記水素アニール工程後に、変化しないで残る請求項1にかかる方法。
- 上記アニールパラメータが、温度、圧力、濃度、または時間を含む請求項1にかかる方法。
- 上記水素アニールの温度が、900℃またはそれ以下である請求項4にかかる方法。
- 上記水素アニールの時間が、1分から5分の範囲内である請求項4〜5のいずれかにかかる方法。
- 上記拡散バリア層が、5nmから50nmの範囲内の厚みである請求項1〜6のいずれかにかかる方法。
- 上記拡散バリア層が、窒化物を含む請求項1〜7のいずれかにかかる方法。
- 上記拡散バリア層が、コンタクト・エッチ・ストップ層を含む請求項1〜8のいずれかにかかる方法。
- 上記コンタクト・エッチ・ストップ層が、圧縮歪または引っ張り歪を有する請求項1〜9のいずれかにかかる方法。
- 上記歪材料が、歪シリコンを含む請求項1〜10のいずれかにかかる方法。
- 上記基板が、歪シリコン・オン・インシュレータ基板である請求項11にかかる方法。
- 上記第1領域がNMOS領域であり、上記第2領域がPMOS領域である請求項11または12にかかる方法。
- 上記歪材料が、ゲルマニウムを含む請求項1〜10のいずれかにかかる方法。
- 上記基板が、シリコン・ゲルマニウム・オン・インシュレータ基板である請求項14にかかる方法。
- 上記第1領域がPMOS領域であり、上記第2領域がNMOS領域である請求項14または15にかかる方法。
- 半導体デバイス中の歪を緩和する方法であって、
歪材料を含む基板を提供する工程と、
第1領域を規定する工程と、
第2領域を規定する工程と、
該第1領域上に、拡散バリア層を形成する工程と、
該第2領域中の該歪材料が緩和されるように、水素アニールを行う工程と、を含み、
該拡散バリア層が所定の厚みを有し、該厚みが該水素アニールのアニールパラメータに依存する方法。 - 上記第1領域の上記歪材料が、上記水素アニール工程後に、部分的に緩和される請求項17にかかる方法。
- 上記アニールパラメータが、温度、圧力、濃度、または時間を含む請求項17にかかる方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/767,440 US7494902B2 (en) | 2006-06-23 | 2007-06-22 | Method of fabricating a strained multi-gate transistor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81613706P | 2006-06-23 | 2006-06-23 | |
US60/816,137 | 2006-06-23 |
Publications (2)
Publication Number | Publication Date |
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JP2008004910A JP2008004910A (ja) | 2008-01-10 |
JP5160080B2 true JP5160080B2 (ja) | 2013-03-13 |
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JP2006331353A Active JP5160080B2 (ja) | 2006-06-23 | 2006-12-08 | 歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス |
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JP (1) | JP5160080B2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2151852B1 (en) | 2008-08-06 | 2020-01-15 | Soitec | Relaxation and transfer of strained layers |
TWI457984B (zh) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | 應變層的鬆弛方法 |
EP2159836B1 (en) * | 2008-08-25 | 2017-05-31 | Soitec | Stiffening layers for the relaxation of strained layers |
EP2741320B1 (en) * | 2012-12-05 | 2020-06-17 | IMEC vzw | Manufacturing method of a finfet device with dual-strained channels |
US9219150B1 (en) * | 2014-09-18 | 2015-12-22 | Soitec | Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003229542A (ja) * | 2002-02-01 | 2003-08-15 | Fujitsu Ltd | 半導体装置の製造方法及び熱処理装置 |
JP2005019851A (ja) * | 2003-06-27 | 2005-01-20 | Sharp Corp | 半導体装置及びその製造方法 |
US7355253B2 (en) * | 2003-08-22 | 2008-04-08 | International Business Machines Corporation | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates |
JP2005072464A (ja) * | 2003-08-27 | 2005-03-17 | Sharp Corp | 半導体基板の製造方法および半導体装置の製造方法 |
JP4177775B2 (ja) * | 2004-03-16 | 2008-11-05 | 株式会社東芝 | 半導体基板及びその製造方法並びに半導体装置 |
JP4163169B2 (ja) * | 2004-10-29 | 2008-10-08 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
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