CN105321955B - 薄膜晶体管基板 - Google Patents

薄膜晶体管基板 Download PDF

Info

Publication number
CN105321955B
CN105321955B CN201410354713.8A CN201410354713A CN105321955B CN 105321955 B CN105321955 B CN 105321955B CN 201410354713 A CN201410354713 A CN 201410354713A CN 105321955 B CN105321955 B CN 105321955B
Authority
CN
China
Prior art keywords
rake
pixel electrode
thin film
film transistor
predetermined altitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410354713.8A
Other languages
English (en)
Other versions
CN105321955A (zh
Inventor
徐旭宽
邱国豪
朱夏青
黄鹏丞
孙铭谦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innolux Corp
Original Assignee
Innolux Display Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innolux Display Corp filed Critical Innolux Display Corp
Priority to CN201811462508.8A priority Critical patent/CN109585458B/zh
Publication of CN105321955A publication Critical patent/CN105321955A/zh
Application granted granted Critical
Publication of CN105321955B publication Critical patent/CN105321955B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133345Insulating layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

本发明是有关于一种薄膜晶体管基板,包括:一基板,且基板上方是依序设置多个薄膜晶体管单元、一绝缘层、一像素电极、以及一配向膜。其中,薄膜晶体管单元是设置于基板上且包括一栅极绝缘层、一主动层、一源极及一漏极;绝缘层具有接触孔以显露薄膜晶体管单元的漏极;而像素电极是设置于绝缘层上且向接触孔延伸以与漏极电性连接。其中,接触孔的侧壁在一第一方向上分别具有一第一倾斜部且在一第二方向上分别具有一第二倾斜部,第一方向与第二方向不同,且像素电极位于第一倾斜部的坡度与位于第二倾斜部的坡度不同。

Description

薄膜晶体管基板
技术领域
本发明是关于一种薄膜晶体管基板,尤指一种可改善显示面板漏光情形的薄膜晶体管基板。
背景技术
随着显示器技术不断进步,所有的装置均朝体积小、厚度薄、重量轻等趋势发展,故目前市面上主流的显示器装置已由以往的阴极射线管发展成液晶显示设备。特别是,液晶显示设备可应用的领域相当多,凡是日常生活中使用的手机、笔记本电脑、摄影机、照相机、音乐播放器、行动导航装置、电视等显示设备,大多数均使用液晶显示面板。
于现今所使用的液晶显示面板中,主要结构不外乎是通过设置于一薄膜晶体管基板上的薄膜晶体管单元控制液晶的转动,而达到显示面板呈现亮暗态的功效。然而,于薄膜晶体管单元上的漏极接触孔,却会因光线在孔内的反射,导致漏光的情形产生;而此漏光的情形却是造成显示面板显示效果降低的因素之一。
因此,为了达到提升显示面板显示效果的目的,各家厂商无不积极开发一种可减少漏光的显示面板,以符合消费者对于显示质量的要求。据此,目前亟需发展一种薄膜晶体管基板,当其应用于显示面板上时,可降低漏光的情形发生,而达到提升显示质量的目的。
发明内容
本发明的主要目的是在提供一种薄膜晶体管基板,其能减少以此所制备的显示面板的漏光情形。
为达成上述目的,本发明的一实施态样是提供一种薄膜晶体管基板,包括:一基板、多个薄膜晶体管单元、一绝缘层、一像素电极、以及一配向膜。其中,薄膜晶体管单元是设置于基板上且分别包括:一栅极绝缘层、一主动层、一源极及一漏极。此外,绝缘层则设置于所述薄膜晶体管单元上具有多个接触孔以分别显露所述薄膜晶体管单元的该漏极;像素电极是设置于绝缘层上且向所述接触孔延伸以与漏极电性连接;而配向膜则覆盖该像素电极。其中,所述接触孔的侧壁在一第一方向上分别具有一第一倾斜部且在一第二方向上分别具有一第二倾斜部,第一方向与第二方向不同,且像素电极位于至少一第一倾斜部的坡度与位于至少一第二倾斜部的坡度不同。
于本发明的另一实施态样是提供另一薄膜晶体管基板,包括:一基板、多个薄膜晶体管单元、一绝缘层、一像素电极、以及一配向膜。其中,薄膜晶体管单元是设置于该基板上且分别包括:一栅极绝缘层、一主动层、一源极及一漏极。此外,一绝缘层是设置于薄膜晶体管单元上具有多个接触孔以分别显露薄膜晶体管单元的漏极;一像素电极则设置于绝缘层上且向接触孔延伸以与漏极电性连接;而一配向膜是覆盖像素电极。其中,所述接触孔分别具有一中间底部,且设于至少一中间底部的配向膜具有一多孔性结构。于本实施态样中,主动层的材料并无特殊限制,可为本技术领域已知的半导体材料,如非晶硅、金属氧化物(如,IGZO)等。
于本发明的再一实施态样是提供另一薄膜晶体管基板,其同时包括前述两个实施态样的技术特征。
于本发明前述实施态样所提供的薄膜晶体管基板中,第一方向可与第二方向不同;较佳为第一方向与第二方向间的夹角是介于85至90度之间;且更佳为第一方向与第二方向实质上垂直。
于本发明前述实施态样所提供的薄膜晶体管基板中,第一方向与和薄膜晶体管单元电性连接的一扫描线间的夹角是介于0至5度之间,而第二方向与和薄膜晶体管单元电性连接的一资料线间的夹角是介于0至5度之间;较佳为,第一方向与扫描线实质上平行,而第二方向与资料线实质上平行。于此情形下,像素电极位于至少一第一倾斜部的坡度大于位于至少一第二倾斜部的坡度。
于本发明前述实施态样中,在此,所谓的“坡度”可以“斜率”方式定义;更具体而言,绝缘层的一绝缘层表面的延伸线于第一方向及第二方向上分别与位于接触孔的像素电极的一电极表面形成一第一接触点及一第二接触点,于像素电极及漏极间的一第一预定高度上位于第一倾斜部与第二倾斜部的像素电极的电极表面分别具有一第一相交点及一第二相交点,位于至少一第一倾斜部上的像素电极的斜率为第一接触点与第一相交点的连线,而位于至少一第二倾斜部上的像素电极的斜率为第二接触点与第二相交点的连线。于本发明前述实施态样所提供的薄膜晶体管基板中,像素电极位于至少一第一倾斜部与至少一第二倾斜部的斜率不同;较佳为,当第一方向与和薄膜晶体管单元电性连接的一扫描线间的夹角是介于0至5度之间或第一方向与扫描线实质上平行,而第二方向与和薄膜晶体管单元电性连接的一资料线间的夹角是介于0至5度之间或第二方向与资料线实质上平行时,该像素电极位于至少一第一倾斜部的斜率大于位于至少一第二倾斜部的斜率。
于本发明前述实施态样中,在此,所谓的“坡度”也可以“曲率半径”方式定义;更具体而言,于像素电极及漏极间的一第一预定高度及一第二预定高度上,且第二预定高度前述的第一预定高度不同,位于至少一该第一倾斜部在第一预定高度及第二预定高度下的像素电极的曲率半径与位于至少一第二倾斜部在第一预定高度及第二预定高度下的像素电极的曲率半径不同。较佳为,当第一方向与和薄膜晶体管单元电性连接的一扫描线间的夹角是介于0至5度之间或第一方向与扫描线实质上平行,而第二方向与和薄膜晶体管单元电性连接的一资料线间的夹角是介于0至5度之间或第二方向与资料线实质上平行时,位于至少一第一倾斜部在第一预定高度及第二预定高度下的像素电极的曲率半径均小于位于至少一第二倾斜部在第一预定高度及第二预定高度下的像素电极的曲率半径。
更佳为,于本发明前述实施态样中,第一倾斜部及第二倾斜部上的像素电极同时符合前述以“斜率”及“曲率半径”方式定义的相对关系。
于本发明前述实施态样所提供的薄膜晶体管基板中,位于接触孔中间底部的配向膜可具有一多孔性结构。其中,多孔性结构中的孔洞孔径并无特别限制,而较佳是介于50nm至1000nm之间。
此外,于本发明前述实施态样所提供的薄膜晶体管基板中,配向膜是设于接触孔中,且设于接触孔侧壁上的配向膜与设于中间底部的配向膜具有不同粗糙度。
再者,本发明更提供一液晶显示面板,其包括前述的薄膜晶体管基板。
附图说明
为进一步说明本发明的技术内容,以下结合实施例及附图详细说明如后,其中:
图1是本发明实施例1的液晶显示面板示意图。
图2是本发明实施例1的漏极接触孔结构示意图。
图3A及图3B是分别为本发明实施例1的漏极接触孔结构沿图2的A-A’与B-B’剖面线的剖面示意图。
图4A及图4B是分别为本发明实施例1的图3A及图3B的区域A的放大图。
图5A及图5B是分别为本发明实施例2的漏极接触孔结构沿图2的A-A’与B-B’剖面线的剖面示意图。
图6A及图6B是分别为本发明实施例2的图5A及图5B的区域A的放大图。
具体实施方式
以下是通过特定的具体实施例说明本发明的实施方式,熟习此技术的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。本发明亦可通过其他不同的具体实施例加以施行或应用,本说明书中的各项细节亦可针对不同观点与应用,在不悖离本发明的精神下进行各种修饰与变更。
实施例1
如图1所示,本实施例的液晶显示面板的包括:一薄膜晶体管基板1;一彩色滤光基板2,与薄膜晶体管基板1相对设置;多个间隔物4,设于薄膜晶体管基板1及彩色滤光基板2间;一框胶5,设于薄膜晶体管基板1及彩色滤光基板2间且位于设于薄膜晶体管基板1及彩色滤光基板2外周围;以及一液晶层3,设于薄膜晶体管基板1及彩色滤光基板2所形成的空间中。接下来,将描述本实施例的薄膜晶体管基板的结构。
如图2所示,其是为本实施例的漏极接触孔结构示意图;且如图3A所示,其为本实施例的漏极接触孔结构沿图2的A-A’剖面线的剖面示意图。请同时参照图2及图3A,本实施例的薄膜晶体管基板包括:一基板10,其上方设置有一由第一金属层形成的扫描线11与栅极111、一栅极绝缘层12、一主动层13、一由第二金属层形成的资料线14及源极(图未示)与漏极142、一第一绝缘层15、一第二绝缘层16、一像素电极17及一配向膜18;且栅极111、栅极绝缘层12、主动层13、源极(图未示)与漏极142是组成本实施例的薄膜晶体管单元。其中,如图2所示,扫描线11是沿第一方向X配置;更具体而言,第一方向X与和薄膜晶体管单元电性连接的扫描线11间的夹角是介于0至5度之间,且较佳为实质上平行。此外,资料线14则沿第二方向Y配置;更具体而言,第二方向Y与和薄膜晶体管单元电性连接的一资料线14间的夹角是介于0至5度之间,且较佳为实质上平行。此外,第一方向X与第二方向Y是不相同;于本实施例中,第一方向X与第二方向Y间的夹角是介于85至90度之间;较佳为,第一方向X与第二方向Y是实质上垂直。
如图3A所示,本实施例的薄膜晶体管基板包括:一基板10、多个薄膜晶体管单元、一包括第一绝缘层15及第二绝缘层16的绝缘层、一像素电极17、以及一配向膜18。其中,薄膜晶体管单元是设置于基板10上且分别包括:一栅极111;一栅极绝缘层12,设置于栅极111及基板10上;一主动层(图未示),设置于栅极绝缘层12上;以及一源极(图未示)及一漏极142,设置于主动层(图未示)上。此外,包括第一绝缘层15及第二绝缘层16的绝缘层则设置于薄膜晶体管单元上且分别具有一绝缘层开孔1521及一接触孔161以显露薄膜晶体管单元的漏极142;像素电极17是设置第一绝缘层15及第二绝缘层16上且向接触孔161延伸以与漏极142电性连接;而配向膜18则覆盖像素电极17。
于本实施例中,是以下栅极式薄膜晶体管单元作为示例,于本发明的其他实施例中,也可为其他类型的薄膜晶体管单元,如上栅极式薄膜晶体管单元。
在此,第一金属层及第二金属层材料可使用本技术领域常用的导电材料,如金属、合金、金属氧化物、金属氮氧化物、或其他本技术领域常用的电极材料;且较佳为金属材料。于本实施例中,第一金属层可为由Ta及W依序层叠的复合金属层,而第二金属层可为由Ti、A1及Ti依序层叠的复合金属层。此外,栅极绝缘层12的材料可为本技术领域常用的绝缘材料;于本实施例中,栅极绝缘层12为由氮化硅所形成的第一栅极绝缘层121及由氧化硅所形成的第二栅极绝缘层122依序层叠形成的绝缘层。再者,主动层13的材料可为本技术领域常用的半导体材料;于本实施例中,主动层13的材料为IGZO。同时,于本实施例中,设于第二金属层上的绝缘层是由第一绝缘层15及第二绝缘层16层叠形成;其中,第一绝缘层15的材料可为本技术领域常用的绝缘层材料,在此,第一绝缘层15是由氧化硅所形成的第一保护绝缘层151及由氮化硅所形成的第二保护绝缘层152依序层叠形成,且第一保护绝缘层151与第二保护绝缘层152分别具有一绝缘层开孔1511、1521以显露薄膜晶体管单元的漏极142;至于第二绝缘层16的材料可为本技术领域常用的平坦层材料,且具有一接触孔161以显露薄膜晶体管单元的漏极142。于本实施例中,设于第二金属层上的绝缘层是由第一绝缘层15及第二绝缘层16依序层叠形成;然而,于本发明的其他实施例中,设于第二金属层上的绝缘层可仅包括第一绝缘层15及第二绝缘层16的其中一者。再者,像素电极17的材料可使用本技术领域常用的透明导电材料,如ITO、IZO等金属氧化物的透明电极材料。在此须说明的是,前述的各层材料仅为本发明其中一实施例,但本发明并不仅限于此。
请同时参照图3A及图3B,于图3A中,显露漏极142的开孔大小是由第二保护绝缘层152的绝缘层开孔1521所决定,而于图3B中,则由第二绝缘层16的接触孔161所决定。
请同时参照图3A及图3B,其分别为本实施例的漏极接触孔结构沿图2的A-A’与B-B’剖面线的剖面示意图。请同时参照图2及图3A及3B,接触孔161的侧壁在第一方向X上具有一第一倾斜部1611且在第二方向Y上具有一第二倾斜部1612,且像素电极17位于第一倾斜部1611的坡度与位于第二倾斜部1612的坡度不同。
请同时参照图4A及图4B,其分别为图3A及图3B的区域A的放大图。请同时参照图2及图4A及4B,像素电极17位于接触孔161的侧壁在第一方向X上的第一倾斜部1611的坡度大于位于接触孔161的侧壁在第二方向Y的第二倾斜部1612的坡度。
更详细而言,如图2及图4A及4B所示,第二绝缘层16的一绝缘层表面16a的延伸线(如虚线所示)于第一方向X及第二方向Y上分别与位于接触孔161的像素电极17的一电极表面17a形成一第一接触点P1及一第二接触点P2,于像素电极17及漏极142间的一第一预定高度H1上位于第一倾斜部1611与第二倾斜部1612的像素电极17的电极表面17a分别具有一第一相交点Q1及一第二相交点Q2,位于第一倾斜部1611上的像素电极17a的斜率为第一接触点P1与第一相交点Q1的连线,位于第二倾斜部1612上的像素电极17的斜率为第二接触点P2与第二相交点Q2的连线,且像素电极17位于第一倾斜部1611与第二倾斜部1612的斜率不同。较佳为,于本实施例中,像素电极17位于第一倾斜部1611的斜率大于位于第二倾斜部1612的斜率。
第一倾斜部1611及第二倾斜部1612间除了有前述斜率关系外,更有曲率半径关系。如图2及图4A及4B所示,于像素电极17及漏极142间的一第一预定高度H1及一第二预定高度H2上,且第二预定高度H2与第一预定高度H1不同,位于第一倾斜部1611在第一预定高度H1及第二预定高度H2下的像素电极17的曲率半径与位于第二倾斜部1612在第一预定高度H1及第二预定高度H2下的像素电极17的曲率半径不同。在此,所谓的曲率半径是指于第一预定高度H1上分别位于第一倾斜部1611与第二倾斜部1612的像素电极17的电极表面17a的第一相交点Q1及第二相交点Q2、以及于第二预定高度H2上分别位于第一倾斜部1611与第二倾斜部1612的像素电极17的电极表面17a的第三相交点R1及第四相交点R4为基准所得到的曲率半径。较佳为,于本实施例中,位于第一倾斜部1611在第一预定高度H1及第二预定高度H2下的像素电极17的曲率半径均小于位于第二倾斜部1612在第一预定高度H1及第二预定高度H2下的像素电极17的曲率半径。
于本实施例中,如图2至图4B所示,通过将接触孔于不同方向上设计不同坡度,更具体而言,通过将接触孔的侧壁于不同方向上的第一倾斜部及第二倾斜部设计成具有不同坡度(包括斜率及曲率半径等),则可避免光线于接触孔中的反射角度相同,由此可达到降低漏光的效果。
此外,如图3A及图3B所示,于本实施例中,接触孔161分别具有一中间底部161a,配向膜18是设于接触孔161中,且设于接触孔161的中间底部161a的配向膜18具有一多孔性结构。其中,多孔性结构中的孔洞181孔径可介于50nm至1000nm之间。再者,设于接触孔161的侧壁上的配向膜18与设于中间底部161a的配向膜18具有不同粗糙度。在此,配向膜18可使用本技术领域常用的配向膜材料(如PI)制备;且可通过选择配向膜18材料的单体及聚合程度,进而控制配向膜18是否具有多孔性结构以及控制多孔性结构中的孔洞孔径大小。
于本实施例中,如图3A及图3B所示,通过将接触孔中的配向膜设计成具有多孔性结构,而可减少光线在多孔性结构内反射,以避免于接触孔中产生漏光的情形。
在此,于图3A至图4B中,仅以同一漏极接触孔的剖面表示,于其他实施例中,图2的A-A’及B-B’剖面线可位于不同接触孔,只要符合前述条件即可。
此外,如图2至图4B所示,在此仅以接触孔161于第一方向X及第二方向Y的左侧壁的第一倾斜部1611及第二倾斜部1612进行比较;然而,于本发明中,并不限于将接触孔161的左侧壁的倾斜部进行比较,而可将不同接触孔161于第一方向X的左侧壁和右侧壁的其中一者的倾斜部与相同或不同接触孔161于第二方向Y的左侧壁和右侧壁的其中一者的倾斜部进行比较,只要符合前述条件即可。
实施例2
本实施例的液晶显示面板及其薄膜晶体管基板结构是与实施例1相同,除了下述不同点。
首先,本实施例的薄膜晶体管元件中的主动层材料为非晶硅。
此外,图5A及图5B是分别为本实施例的漏极接触孔结构沿图2的A-A’与B-B’剖面线的剖面示意图。如图5A及图5B所示,本实施例的薄膜晶体管基板上,配向膜18不具有多孔性结构。再者,图6A及图6B是分别为图5A及图5B的区域A的放大图。请比较图4A、4B、6A及6B,虽然实施例1的第一倾斜部1611及第二倾斜部1612较本实施例弯曲,但本实施例的薄膜晶体管基板结构仍具有前述像素电极17位于接触孔161的侧壁在第一方向X上的第一倾斜部1611的坡度大于位于接触孔161的侧壁在第二方向Y的第二倾斜部1612的坡度的特征,由此而可避免光线于接触孔中的反射角度相同以达到降低漏光的效果。
于前述实施例中,仅以薄膜晶体管基板与彩色滤光基板相对设置的液晶显示面板加以示例,其他如阵列上彩色滤光膜(COA)显示面板亦可使用前述本发明所提供的薄膜晶体管基板。
此外,本发明前述实施例所制得的显示设备,可应用于本技术领域已知的任何需要显示屏幕的电子装置上,如显示器、手机、笔记本电脑、摄影机、照相机、音乐播放器、行动导航装置、电视等。
上述实施例仅是为了方便说明而举例而已,本发明所主张的权利范围自应以权利要求范围所述为准,而非仅限于上述实施例。

Claims (21)

1.一种薄膜晶体管基板,包括:
一基板;
多个薄膜晶体管单元,设置于该基板上且分别包括:一栅极绝缘层、一主动层、一源极及一漏极;
一绝缘层,设置于所述薄膜晶体管单元上具有多个接触孔以分别显露所述薄膜晶体管单元的该漏极,且至少一个所述接触孔具有一中间底部;
一像素电极,设置于该绝缘层上且向至少一个所述接触孔延伸以与该漏极电性连接;以及
一聚酰亚胺配向膜,覆盖该像素电极,该聚酰亚胺配向膜设于至少一个所述接触孔中,且于该中间底部的聚酰亚胺配向膜 厚度不同于覆盖该像素电极其他部分的聚酰亚胺配向膜 厚度;
其中至少一个所述接触孔的至少一个侧壁在一第一方向上分别具有一第一倾斜部且在一第二方向上分别具有一第二倾斜部,该第一方向与该第二方向不同,且该像素电极位于至少一所述第一倾斜部的坡度与位于至少一所述第二倾斜部的坡度不同。
2.如权利要求1所述的薄膜晶体管基板,其中该第一方向与该第二方向间的夹角介于85至90度之间。
3.如权利要求1所述的薄膜晶体管基板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且该像素电极位于至少一所述第一倾斜部的坡度大于位于至少一所述第二倾斜部的坡度。
4.如权利要求1所述的薄膜晶体管基板,其中该中间底部的该聚酰亚胺配向膜具有一多孔性结构。
5.如权利要求4所述的薄膜晶体管基板,其中该多孔性结构中的孔洞孔径介于50nm至1000nm之间。
6.如权利要求1所述的薄膜晶体管基板,其中设于至少一个所述接触孔的至少一个侧壁上的该聚酰亚胺配向膜与设于该中间底部的该聚酰亚胺配向膜具有不同粗糙度。
7.如权利要求1所述的薄膜晶体管基板,其中该绝缘层的一绝缘层表面的延伸线于该第一方向及该第二方向上分别与位于所述至少一个接触孔的该像素电极的一电极表面形成一第一接触点及一第二接触点,于该像素电极及该漏极间的一第一预定高度上位于所述第一倾斜部与所述第二倾斜部的该像素电极的该电极表面分别具有一第一相交点及一第二相交点,位于至少一所述第一倾斜部上的该像素电极的斜率为该第一接触点与该第一相交点的连线,位于至少一所述第二倾斜部上的该像素电极的斜率为该第二接触点与该第二相交点的连线,且该像素电极位于至少一所述第一倾斜部与至少一所述第二倾斜部的斜率不同。
8.如权利要求7所述的薄膜晶体管基板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且该像素电极位于至少一所述第一倾斜部的斜率大于位于至少一所述第二倾斜部的斜率。
9.如权利要求7所述的薄膜晶体管基板,其中于该像素电极及该漏极间的一第二预定高度上,且该第二预定高度与该第一预定高度不同,位于至少一所述第一倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径与位于至少一所述第二倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径不同。
10.如权利要求9所述的薄膜晶体管基板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且位于至少一所述第一倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径均小于位于至少一所述第二倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径。
11.如权利要求1所述的薄膜晶体管基板,其中该主动层的材料为IGZO。
12.一种显示面板,包括:
一种薄膜晶体管基板,包括:
一基板;
多个薄膜晶体管单元,设置于该基板上且分别包括:一栅极绝缘层、一主动层、一源极及一漏极;
一绝缘层,设置于该薄膜晶体管单元上具有多个接触孔以分别显露所述薄膜晶体管单元的该漏极;
一像素电极,设置于该绝缘层上且向至少一个所述接触孔延伸以与该漏极电性连接;以及
一配向膜,覆盖该像素电极;
其中至少一个所述接触孔分别具有一中间底部,且设于至少一所述中间底部的该配向膜具有一多孔性结构;
其中该配向膜设于至少一个所述接触孔中,且设于至少一个所述接触孔的至少一个侧壁上的该配向膜与设于该中间底部的该配向膜具有不同粗糙度;以及
一框胶,设置于该薄膜晶体管基板的外周围。
13.如权利要求12所述的显示面板,其中该多孔性结构中的孔洞孔径介于50nm至1000nm之间。
14.如权利要求12所述的显示面板,其中至少一个所述接触孔的至少一个侧壁在一第一方向上分别具有一第一倾斜部且在一第二方向上分别具有一第二倾斜部,该第一方向与该第二方向不同,且该像素电极位于至少一所述第一倾斜部的坡度与位于至少一所述第二倾斜部的坡度不同。
15.如权利要求14所述的显示面板,其中该第一方向与该第二方向间的夹角介于85至90度之间。
16.如权利要求14所述的显示面板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且该像素电极位于至少一所述第一倾斜部的坡度大于位于至少一所述第二倾斜部的坡度。
17.如权利要求14所述的显示面板,其中该绝缘层的一绝缘层表面的延伸线于该第一方向及该第二方向上分别与位于至少一个所述接触孔的该像素电极的一电极表面形成一第一接触点及一第二接触点,于该像素电极及该漏极间的一第一预定高度上位于所述第一倾斜部与所述第二倾斜部的该像素电极的该电极表面分别具有一第一相交点及一第二相交点,位于至少一所述第一倾斜部上的该像素电极的斜率为该第一接触点与该第一相交点的连线,位于至少一所述第二倾斜部上的该像素电极的斜率为该第二接触点与该第二相交点的连线,且该像素电极位于至少一所述第一倾斜部与至少一所述第二倾斜部的斜率不同。
18.如权利要求17所述的显示面板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且该像素电极位于至少一所述第一倾斜部的斜率大于位于至少一所述第二倾斜部的斜率。
19.如权利要求17所述的显示面板,其中于该像素电极及该漏极间的一第二预定高度上,且该第二预定高度与该第一预定高度不同,位于至少一所述第一倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径与位于至少一所述第二倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径不同。
20.如权利要求19所述的显示面板,其中该第一方向与和该薄膜晶体管单元电性连接的一扫描线间的夹角介于0至5度之间,该第二方向与和该薄膜晶体管单元电性连接的一资料线间的夹角介于0至5度之间,且位于至少一所述第一倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径均小于与位于至少一所述第二倾斜部在该第一预定高度及该第二预定高度下的该像素电极的曲率半径。
21.如权利要求12所述的显示面板,其中该主动层的材料为IGZO。
CN201410354713.8A 2014-06-06 2014-07-24 薄膜晶体管基板 Active CN105321955B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811462508.8A CN109585458B (zh) 2014-06-06 2014-07-24 薄膜晶体管基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103119692A TWI553881B (zh) 2014-06-06 2014-06-06 薄膜電晶體基板
TW103119692 2014-06-06

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201811462508.8A Division CN109585458B (zh) 2014-06-06 2014-07-24 薄膜晶体管基板

Publications (2)

Publication Number Publication Date
CN105321955A CN105321955A (zh) 2016-02-10
CN105321955B true CN105321955B (zh) 2019-01-18

Family

ID=51946201

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201811462508.8A Active CN109585458B (zh) 2014-06-06 2014-07-24 薄膜晶体管基板
CN201410354713.8A Active CN105321955B (zh) 2014-06-06 2014-07-24 薄膜晶体管基板
CN201420410804.4U Active CN204243040U (zh) 2014-06-06 2014-07-24 薄膜晶体管基板

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201811462508.8A Active CN109585458B (zh) 2014-06-06 2014-07-24 薄膜晶体管基板

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201420410804.4U Active CN204243040U (zh) 2014-06-06 2014-07-24 薄膜晶体管基板

Country Status (4)

Country Link
US (2) US9362314B2 (zh)
JP (1) JP3194341U (zh)
CN (3) CN109585458B (zh)
TW (1) TWI553881B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI553881B (zh) * 2014-06-06 2016-10-11 群創光電股份有限公司 薄膜電晶體基板
TWI553388B (zh) * 2014-09-11 2016-10-11 群創光電股份有限公司 液晶顯示裝置及其元件基板
TWI560503B (en) * 2015-01-30 2016-12-01 Innolux Corp Display panel
CN106483725B (zh) * 2015-08-28 2020-01-03 群创光电股份有限公司 液晶显示面板
KR102515002B1 (ko) * 2015-12-28 2023-03-28 엘지디스플레이 주식회사 어레이 기판 및 이를 갖는 디스플레이 패널
CN108735777B (zh) * 2017-04-21 2020-11-06 群创光电股份有限公司 显示装置
US10620496B2 (en) 2017-09-28 2020-04-14 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate, manufacturing method of array substrate and liquid crystal display panel
CN107479292B (zh) * 2017-09-28 2020-08-04 武汉华星光电技术有限公司 阵列基板、阵列基板的制作方法及液晶显示面板
JP2019174805A (ja) * 2018-03-29 2019-10-10 シャープ株式会社 液晶表示装置及び液晶表示装置の製造方法
JP6810718B2 (ja) * 2018-04-13 2021-01-06 シャープ株式会社 表示装置、及び表示装置の製造方法
CN112864233B (zh) * 2019-11-12 2023-04-07 群创光电股份有限公司 电子装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030202133A1 (en) * 2002-04-30 2003-10-30 Young-Nam Yun Liquid crystal display apparatus and method of manufacturing the same
CN1841168A (zh) * 2005-03-28 2006-10-04 精工爱普生株式会社 密封结构、密封方法、液晶装置及其制造方法、投影仪
CN103346159A (zh) * 2013-06-28 2013-10-09 北京京东方光电科技有限公司 一种阵列基板及其制造方法、显示装置
CN204243040U (zh) * 2014-06-06 2015-04-01 群创光电股份有限公司 薄膜晶体管基板

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060087577A (ko) * 2003-09-24 2006-08-02 샤프 가부시키가이샤 액정 표시 패널의 제조 방법 및 액정 표시 패널의 제조장치
JP2005234091A (ja) * 2004-02-18 2005-09-02 Hitachi Displays Ltd 表示装置
JP4201002B2 (ja) * 2005-03-28 2008-12-24 セイコーエプソン株式会社 液晶装置、その製造方法およびプロジェクタ
KR101292043B1 (ko) * 2007-03-26 2013-08-01 엘지디스플레이 주식회사 유기 전계 발광소자 및 그 제조방법
TWI463659B (zh) * 2009-07-06 2014-12-01 Au Optronics Corp 薄膜電晶體陣列及其製造方法
KR101905757B1 (ko) * 2011-11-17 2018-10-10 엘지디스플레이 주식회사 에프에프에스 방식 액정표시장치용 어레이기판 및 그 제조방법
JP6002478B2 (ja) * 2012-07-04 2016-10-05 株式会社ジャパンディスプレイ 液晶表示装置
JP6347937B2 (ja) * 2013-10-31 2018-06-27 株式会社ジャパンディスプレイ 液晶表示装置
JP2015114374A (ja) * 2013-12-09 2015-06-22 株式会社ジャパンディスプレイ 液晶表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030202133A1 (en) * 2002-04-30 2003-10-30 Young-Nam Yun Liquid crystal display apparatus and method of manufacturing the same
CN1841168A (zh) * 2005-03-28 2006-10-04 精工爱普生株式会社 密封结构、密封方法、液晶装置及其制造方法、投影仪
CN103346159A (zh) * 2013-06-28 2013-10-09 北京京东方光电科技有限公司 一种阵列基板及其制造方法、显示装置
CN204243040U (zh) * 2014-06-06 2015-04-01 群创光电股份有限公司 薄膜晶体管基板

Also Published As

Publication number Publication date
US20150357354A1 (en) 2015-12-10
US20160247937A1 (en) 2016-08-25
US9716179B2 (en) 2017-07-25
CN109585458A (zh) 2019-04-05
TWI553881B (zh) 2016-10-11
CN109585458B (zh) 2021-06-22
JP3194341U (ja) 2014-11-13
US9362314B2 (en) 2016-06-07
CN204243040U (zh) 2015-04-01
TW201547028A (zh) 2015-12-16
CN105321955A (zh) 2016-02-10

Similar Documents

Publication Publication Date Title
CN105321955B (zh) 薄膜晶体管基板
CN110045533A (zh) 一种显示基板、显示面板和显示装置
CN203894515U (zh) 一种阵列基板及显示装置
US10418383B2 (en) Array substrate, fabrication method thereof and display device
WO2022001412A1 (zh) 触控基板及触控显示装置
CN104503165B (zh) 一种显示面板及显示装置
CN103852942A (zh) 液晶显示器
CN104965370B (zh) 阵列基板及其制造方法、显示装置
CN105319751A (zh) 一种显示装置
US10539724B2 (en) Array substrate, method for manufacture thereof and display device
CN104503159B (zh) 液晶面板及其制备方法
CN105842934A (zh) 液晶显示面板和液晶显示装置
CN104460157B (zh) 阵列基板及显示装置
CN109616020A (zh) 柔性显示面板和显示装置
CN105208255A (zh) 摄像头组件
CN106707596A (zh) 显示面板及显示装置
CN106020544B (zh) 一种触控显示面板及其制作方法、触控显示装置
WO2015184649A1 (zh) 液晶面板以及液晶显示器
CN105629556B (zh) 光阀及显示装置
US11397348B2 (en) Array substrate having convex component, method for fabricating the same, liquid crystal display panel, and display device
CN106597771B (zh) 阵列基板、液晶显示面板和显示装置
CN109856870A (zh) 显示面板及显示装置
WO2019051971A1 (zh) 阵列基板及显示面板
CN208271545U (zh) 驱动基板和显示面板
CN108920033A (zh) 一种内嵌式触摸屏及显示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant