CN105261572B - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN105261572B
CN105261572B CN201510711045.4A CN201510711045A CN105261572B CN 105261572 B CN105261572 B CN 105261572B CN 201510711045 A CN201510711045 A CN 201510711045A CN 105261572 B CN105261572 B CN 105261572B
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solder mask
semiconductor chip
substrate
conducting wire
semiconductor
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CN105261572A (zh
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林子闳
黄清流
童耿直
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明公开一种半导体封装。所述半导体封装包括基板；第一导线，设置于所述基板上；半导体芯片，设置于所述第一导线的上方；阻焊层，所述阻焊层的一部分延伸到所述半导体芯片的一个边缘内；以及成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。本发明实施例提供了一种改良式的半导体封装。

Description

半导体封装
本发明为申请号“201210270189.7”，名称为“半导体封装”，申请日为2012年7月31日，优先权日为2011年12月21日的发明申请的分案申请。
技术领域
本发明有关于一种半导体封装，特别是有关于一种覆晶封装体的阻焊层设计。
背景技术
对现有技术中的覆晶封装体而言，众所周知覆晶填充材料(underfill)通过大幅降低导电凸块的应力的方式来保护导电凸块。然而，覆晶填充材料本身会遭受剪应力(shear stress)或掀拉应力(peeling stress)，因而会导致失效模式(failure mode)。举例来说，具有空隙(voids)或微裂缝(microcracks)的有瑕疵的覆晶填充材料，在高低温循环条件(under temperature cycling condition)下会导致裂缝(cracks)或分层(delamination)等问题。
因为有机覆晶填充材料和无机导线(inorganic conductive trace)之间的热膨胀系数(coefficient of thermal expansion，CTE)的不匹配，所以会在例如覆晶填充材料和导线的两种材料的界面产生分层(delamination)，而上述分层为失效模式的其中一种。当覆晶填充材料分层产生时，因为覆晶填充材料的保护能力丧失和覆晶填充材料分层造成应力上升(stress concentration arising)，而通常导致导电凸块产生疲劳裂缝(fatiguecrack)。
在本技术领域中，需要一种不具有覆晶填充材料分层问题的新的覆晶封装体。
发明内容
由此，本发明的目的在于提供改良式的半导体封装。
一种半导体封装的范例实施方式，包括：基板；第一导线，设置于所述基板上；半导体芯片，设置于所述第一导线的上方；阻焊层，所述阻焊层的一部分延伸到所述半导体芯片的一个边缘内；以及成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。
一种半导体封装的另一范例实施方式，包括：基板；第一导线，设置于所述基板上；半导体芯片，设置于所述第一导线的上方；阻焊层，所述阻焊层的一部分自所述半导体芯片的所述边缘的外部延伸至所述半导体芯片和所述基板之间的区域；以及成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。
一种半导体封装的另一范例实施方式，包括：基板；第一导线，设置于所述基板上；半导体芯片，设置于所述第一导线的上方；成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙；以及阻焊层，所述阻焊层的一部分被所述成型材料所覆盖。
一种半导体封装的另一范例实施方式，包括：基板；第一导线，设置于所述基板上；半导体芯片，设置于所述第一导线的上方；阻焊层，所述阻焊层的多个条体自所述半导体芯片的所述边缘的外部延伸至所述半导体芯片和所述基板之间的区域；以及成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。
本发明所公开的半导体封装，提供了一种改良式的半导体封装。
对于已经阅读后续由各附图及内容所显示的较佳实施方式的本领域的技术人员来说，本发明的各目的是明显的。
附图说明
图1本发明一实施例的半导体封装的俯视图。
图2为沿图1的A-A'切线的剖视图。
图3为沿图1的B-B'切线的剖视图。
图4为本发明另一实施例的半导体封装的俯视图。
图5为沿图4的A-A'切线的剖视图。
图6为沿图4的B-B'切线的剖视图。
具体实施方式
在权利要求书及说明书中使用了某些词汇来指称特定的组件。所属领域中的技术人员应可理解，硬件制造商可能会用不同的名词来称呼同样的组件。本权利要求书及说明书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在权利要求书及说明书中所提及的「包括」为开放式的用语，故应解释成「包括但不限定于」。以下以各实施例详细说明并伴随着图式说明的范例，作为本发明的参考依据。在图式或说明书描述中，相似或相同的部分均使用相同的图号。且在图式中，实施例的形状或是厚度可扩大，以简化或是方便标示。再者，图式中各组件的部分将以分别描述说明之，值得注意的是，图中未绘示或描述的组件，为所属技术领域中具有通常知识者所知的形式，另外，特定的实施例仅为揭示本发明使用的特定方式，其并非用以限定本发明。
图1为本发明一实施例的半导体封装500a的俯视图。图2为沿图1的A-A'切线的剖视图。图3为沿图1的B-B'切线的剖视图。本发明一实施例的半导体封装500a为覆晶封装体，其使用铜柱(copper pillar)以作为半导体芯片和基板之间的连接。如图1至图3所示，本发明一实施例的半导体封装500a包括基板200，基板200具有设置于其上的第一导线204和第二导线202。在本发明一实施例中，基板200可由例如硅的半导体材料来形成，或由例如双马来酰亚胺-三氮杂苯树脂(bismaleimide triacine，BT)、聚酰亚胺(polyimide)或ABF绝缘膜(ajinomoto build-up film，ABF)等有机材料来形成。在本发明一实施例中，第一导线204和第二导线202可包括信号线或接地线，上述信号线或接地线可用于直接固接(mounted)至基板200的半导体芯片210的输入/输出(input/output，I/O)连接。在本实施例中，每一条第一导线204可视为用于布线(routing)的信号线段/接地线段，而每一条第二导线202的一部分202a，其可视为基板200的垫区域(pad region)。
接着，如图1至图3所示，利用沉积工序，顺应地形成阻焊层(solder resistancelayer)206，以覆盖基板200。然后，对阻焊层206进行图案化工序(patterning process)。进行图案化工序之后，除了阻焊层206的延伸部分208之外，阻焊层206暴露出基板200与后续固着于(mounted)基板200之上的半导体芯片210之间的重叠区域。请注意，阻焊层206的延伸部分208沿着第一导线204延伸，且覆盖部分第一导线204。并且，除了延伸部分208之外的阻焊层206设置为远离于后续固着的半导体芯片210，且与半导体芯片210相距一段距离d1。在本发明一实施例中，阻焊层206可包括防焊材料(solder mask material)、氧化物、氮化物或氮氧化物。如图2所示，阻焊层206的延伸部分208覆盖第一导线204的一部分204a。请注意，阻焊层206的延伸部分208的宽度W2设计为大于第一导线204的一部分204a的宽度W1，使得延伸部分208的底面209的一部分暴露于第一导线204的一部分204a之外。且阻焊层206的延伸部分208具有垂直侧壁(vertical sidewall)207，第一导线204的一部分204a具有垂直侧壁205，垂直侧壁207凸出于与其相邻的垂直侧壁205。因此，延伸部分208与第一导线204的一部分204a共同具有T形剖面。
接着，在基板200上全面性地堆叠干膜光阻层(dry film photoresist)或液态光阻层(liquid photoresist)(图中未绘示)。之后，利用包括曝光步骤和显影步骤(development step)的微影工序(photolithography process)对上述干膜光阻层/液态光阻层进行图案化，以分别在第二导线202的一部分202a(即垫区域)的上方形成开口(图中未绘示)，以确定出后续形成的导电柱状物(conductive pillar)的形成位置。
然后，分别在第二导线202的一部分202a(即垫区域)上形成导电柱状物212，并填充上述干膜光阻层/液态光阻层的开口。在本发明另一实施例中，可在导电柱状物212和第二导线202的一部分202a(即垫区域)之间形成例如镍的导电缓冲层(图中未绘示)。上述导电缓冲层可作为导电柱状物212的种晶层(seed layer)、黏着层(adhesion layer)和/或阻障层(barrier layer)。在本发明一实施例中，导电柱状物212可作为后续形成的导电凸块的焊点(solder joint)，而导电凸块用于传输半导体芯片210的输入/输出(I/O)信号、接地(ground)信号或电源(power)信号。因此，导电柱状物212可帮助增加凸块结构的机械强度。在本发明一实施例中，导电柱状物212可由铜形成。接着，可利用例如使用适当蚀刻剂的湿蚀刻工序(wet etching process)的剥除工序(stripping process)，来移除上述干膜光阻层/液态光阻层。
接着，如图1至图3所示，将半导体芯片210固着于基板200上，其中半导体芯片210具有形成于其接合垫(bond pad)(图中未绘示)上的多个导电凸块214。上述导电凸块214通过导电柱状物212分别连接至第二导线202的一部分202a(即垫区域)，且导电柱状物212位于导电凸块214和第二导线202的一部分202a之间。如图1所示，阻焊层206设置为远离于与导电柱状物212重叠的第二导线202的一部分202a(即垫区域)，且与第二导线202的一部分202a相距一段距离d2。如图3所示，阻焊层206的延伸部分208位于半导体芯片210的下方，且位于半导体芯片210的底面224的下方，且位于半导体芯片210的投影区域(projectionarea)222内。
接着，如图2和图3所示，可利用点胶法(dispensing method)，通过毛细作用(capillary action)使覆晶填充材料220流动并填充基板200和半导体芯片210之间的间隙，且覆盖阻焊层206。覆晶填充材料220用以补偿基板、导线和半导体芯片之间热膨胀系数(CTE)的差异。之后，硬化(cure)覆晶填充材料220。在本发明一实施例中，阻焊层206的延伸部分208的底面209的一部分被覆晶填充材料220包裹。进行上述工序之后，即完成了本发明一实施例的半导体封装500a。
图4为本发明另一实施例的半导体封装500b的俯视图。图5为沿图4的A-A'切线的剖视图。图6为沿图4的B-B'切线的剖视图。本发明一实施例的半导体封装500b为覆晶封装体，其使用焊锡凸块(solder bump)而非使用铜柱以作为半导体芯片和基板之间的连接。如图4至图6所示，本发明一实施例的半导体封装500b包括基板300，基板300具有设置于其上的第一导线304和第二导线302。在本发明一实施例中，可由例如硅的半导体材料或例如双马来酰亚胺-三氮杂苯树脂、聚酰亚胺或ABF绝缘膜等有机材料形成基板300。在本发明一实施例中，第一导线304和第二导线302可包括信号线或接地线，上述信号线或接地线可用于直接固接至基板300的半导体芯片310的输入/输出(I/O)连接。在本实施例中，每一条第一导线304可视为用于布线的信号线段/接地线段，而每一条第二导线302的一部分302a，其可视为基板300的垫区域。
接着，如图4至图6所示，利用沉积工序，顺应地形成阻焊层306，以覆盖基板300。然后，对阻焊层306进行图案化工序。进行图案化工序之后，除了阻焊层306的延伸部分308之外，阻焊层306暴露出基板300与后续固着于基板300之上的半导体芯片310之间的重叠区域。请注意，阻焊层306的延伸部分308沿着第一导线304延伸，且覆盖部分第一导线304。并且，除了延伸部分308之外的阻焊层306设置为远离于后续固着的半导体芯片310，且与半导体芯片310相距一段距离d1。在本发明一实施例中，阻焊层306可包括防焊材料、氧化物、氮化物或氮氧化物。如图5所示，阻焊层306的延伸部分308覆盖第一导线304的一部分304a。请注意，阻焊层306的延伸部分308的宽度W2设计为大于第一导线304的一部分304a的宽度W1，使得延伸部分308的底面309的一部分暴露于第一导线204的一部分304a之外。且阻焊层306的延伸部分308具有垂直侧壁307，第一导线304的一部分304a具有垂直侧壁305，垂直侧壁307凸出于与其相邻的垂直侧壁305。因此，延伸部分308与第一导线304的一部分304a共同具有T形剖面。
接着，如图4至图6所示，进行焊料印刷工序(solder printing process)，以在第二导线302的一部分302a(即垫区域)上形成焊锡图案(solder paste pattern)(图中未绘示)。然后，将具有多个接合垫(图中未绘示)的半导体芯片310固着于基板300上。上述半导体芯片310的接合垫(图中未绘示)分别连接至焊锡图案。接着，依序进行回焊工序(reflowprocess)和冷却工序(cooling process)，使上述焊锡图案转变成焊锡凸块(solder bump)312。上述焊锡凸块312连接基板300的第二导线302的一部分302a和半导体芯片310的接合垫(图中未绘示)。如图4所示，阻焊层306设置为远离于与焊锡凸块312重叠的第二导线302的一部分302a(即垫区域)，且与第二导线302的一部分302a相距一段距离d2。如图6所示，阻焊层306的延伸部分308位于半导体芯片310的下方，且位于半导体芯片310的底面324的下方，且位于半导体芯片310的投影区域322内。
接着，如图5和图6所示，可利用点胶法(dispensing method)，通过毛细作用使覆晶填充材料320流动并填充基板300和半导体芯片310之间的间隙，且覆盖阻焊层306。覆晶填充材料320用以补偿基板、导线和半导体芯片之间热膨胀系数(CTE)的差异。之后，硬化覆晶填充材料320。在本发明一实施例中，阻焊层306的延伸部分308的底面309的一部分被覆晶填充材料320包裹。进行上述工序之后，即完成了本发明一实施例的半导体封装500b。
本发明实施例的半导体封装500a与500b具有以下优点。覆晶填充材料包裹阻焊层的延伸部分的底面的一部分，且阻焊层的延伸部分的宽度大于第一导线的部分的宽度，使上述覆晶填充材料会被由阻焊层的延伸部分和第一导线的部分共同构成的T形物锚定(anchored)。因此，可改善现有技术中在覆晶填充材料和导线之间发生的覆晶填充材料分层(underfill delamination problem)的问题。并且，阻焊层的延伸部分仅延伸进入半导体芯片的投影区域，以覆盖第一导线的一部分，阻焊层的剩余部分会设置为远离于半导体芯片，且与半导体芯片相距一段距离，使半导体封装仍然具有足够的空间容许覆晶填充材料流动，以填充基板和半导体芯片之间的间隙。因此，阻焊层的延伸部分不会影响点胶工序的成果。此外，本发明实施例的半导体封装可应用于多种的封装工序。举例来说，可仅使用成型材料(molding compound)来填充基板和半导体芯片之间的间隙。在本发明另一实施例中，可使用成型材料和覆晶填充材料两者填充基板和半导体芯片之间的间隙。在本发明其他实施例中，可仅使用覆晶填充材料填充基板和半导体芯片之间的间隙。
以上所述仅为本发明的较佳实施方式，凡依本发明权利要求所做的均等变化和修饰，均应属本发明的涵盖范围。

Claims (16)

1.一种半导体封装，其特征在于，包括：
基板；
第一导线，设置于所述基板上；
半导体芯片，设置于所述第一导线的上方；
阻焊层，当从俯视角度观看时，所述阻焊层的一部分沿所述第一导线延伸，延伸至所述半导体芯片的投影区域内且覆盖所述第一导线位于所述半导体芯片的投影区域内的部分的一部分，所述阻焊层的剩余部分与所述半导体芯片相距一段相同的距离；以及
成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。
2.如权利要求1所述的半导体封装，其特征在于，当从俯视角度观看时，所述阻焊层的所述一部分的宽度大于所述第一导线被所述阻焊层的所述一部分所覆盖的一部分的宽度。
3.如权利要求1所述的半导体封装，其特征在于，所述阻焊层的所述一部分具有垂直侧壁，所述垂直侧壁凸出于与所述第一导线被所述阻焊层的所述一部分所覆盖的一部分的侧壁。
4.如权利要求1所述的半导体封装，其特征在于，所述阻焊层延伸至所述半导体芯片的投影区域的部分位于所述半导体芯片和所述基板之间的区域。
5.如权利要求1所述的半导体封装，其特征在于，所述阻焊层的所述一部分被所述成型材料所覆盖。
6.如权利要求1所述的半导体封装，其特征在于，所述阻焊层的所述一部分包括多个条体，所述多个条体分别沿所述第一导线延伸，且延伸至所述半导体芯片的投影区域内且覆盖所述第一导线位于所述半导体芯片的投影区域内的部分的一部分。
7.一种半导体封装，其特征在于，包括：
基板；
第一导线，设置于所述基板上；
半导体芯片，设置于所述第一导线的上方；
阻焊层，当从俯视角度观看时，所述阻焊层的一部分自所述半导体芯片的一边缘的外部延伸至所述半导体芯片和所述基板之间的区域且覆盖所述第一导线位于所述半导体芯片和所述基板之间的区域的部分的一部分，所述阻焊层的剩余部分与所述半导体芯片相距一段相同的距离；以及
成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙。
8.如权利要求7所述的半导体封装，其特征在于，当从俯视角度观看时，所述阻焊层的所述一部分的宽度大于所述第一导线被所述阻焊层的所述一部分所覆盖的宽度。
9.如权利要求7所述的半导体封装，其特征在于，所述阻焊层的所述一部分被所述成型材料所覆盖。
10.如权利要求7所述的半导体封装，其特征在于，所述阻焊层的所述一部分包括多个条件，所述多个条体分别自所述半导体芯片的边缘的外部延伸至所述半导体芯片和所述基板之间的区域且覆盖所述第一导线位于所述半导体芯片和所述基板之间的区域的部分的一部分。
11.一种半导体封装，其特征在于，包括：
基板；
第一导线，设置于所述基板上；
半导体芯片，设置于所述第一导线的上方；
阻焊层，当从俯视角度观看时，所述阻焊层的一部分延伸到所述半导体芯片的一个边缘内且覆盖所述第一导线位于所述半导体芯片的所述边缘内的部分的一部分，所述阻焊层的剩余部分与所述半导体芯片相距一段距离；以及
成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙，其中，当从俯视角度观看时，所述成型材料覆盖所述阻焊层的所述一部分及所述第一导线位于所述半导体芯片的所述边缘内但未被所述阻焊层的所述一部分所覆盖的部分。
12.如权利要求11所述的半导体封装，其特征在于，当从俯视角度观看时，所述阻焊层的所述一部分的宽度大于所述第一导线被所述阻焊层的所述一部分所覆盖的一部分的宽度。
13.如权利要求11所述的半导体封装，其特征在于，所述阻焊层的所述一部分自所述半导体芯片的所述边缘的外部延伸至所述半导体芯片和所述基板之间的区域。
14.如权利要求11所述的半导体封装，其特征在于，所述阻焊层的所述一部分包括多个条体，所述多个条体自所述半导体芯片的所述边缘的外部延伸至所述边缘内。
15.一种半导体封装，其特征在于，包括：
基板；
第一导线，设置于所述基板上；
半导体芯片，设置于所述第一导线的上方；
阻焊层，当从俯视角度观看时，所述阻焊层的多个条体分别自所述半导体芯片的边缘的外部延伸至所述半导体芯片和所述基板之间的区域且覆盖所述第一导线位于所述半导体芯片和所述基板之间的区域的部分的一部分，所述阻焊层的剩余部分与所述半导体芯片相距一段距离；以及
成型材料，形成于所述基板上方，用于填充所述基板和所述半导体芯片之间的空隙，其中，当从俯视角度观看时，所述成型材料覆盖所述阻焊层的所述一部分及所述第一导线位于所述半导体芯片和所述基板之间的区域但未被所述阻焊层的所述一部分所覆盖的部分。
16.如权利要求15所述的半导体封装，其特征在于，当从俯视角度观看时，所述阻焊层的所述多个条体自所述半导体芯片的边缘的外部延伸至所述半导体芯片和所述基板之间的区域的所述部分的宽度大于所述第一导线被所述阻焊层的所述一部分所覆盖的一部分宽度。
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