CN104979279A - 二维自对准的晶体管接触 - Google Patents

二维自对准的晶体管接触 Download PDF

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Publication number
CN104979279A
CN104979279A CN201510162184.6A CN201510162184A CN104979279A CN 104979279 A CN104979279 A CN 104979279A CN 201510162184 A CN201510162184 A CN 201510162184A CN 104979279 A CN104979279 A CN 104979279A
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source
drain contact
cover layer
grid
transistor
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CN104979279B (zh
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A·C-H·魏
G·布赫
M·A·扎勒斯基
T·G·尼奥吉
J·E·史蒂芬斯
桂宗郁
J·曾
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GlobalFoundries US Inc
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GlobalFoundries Inc
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  • Crystallography & Structural Chemistry (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及二维自对准的晶体管接触，其中，本发明的具体实施例提供改良型半导体结构及制造方法，其提供二维自对准的晶体管接触。使用的是两个各由不同材料构成的不同覆盖层。这两个覆盖层互为可选择性蚀刻。一覆盖层用于栅极覆盖，而另一覆盖层用于源极/漏极覆盖。选择性蚀刻程序使所需的栅极和源极/漏极敞开，而阻隔掩模则用于覆盖并非连接架构任何部分的元件。金属化线件(层件)经沉积而与敞开的元件接触，以在两者之间提供电连接性。

Description

二维自对准的晶体管接触
技术领域
本发明基本上涉及半导体制造，并且更尤指用于晶体管接触的结构及制造方法。
背景技术
随着技术进步，必须将电子装置的制造改良以满足电子装置行动化、重量轻、有效率的趋势。除了缩减半导体装置的尺寸外，也能藉由缩减半导体装置之间的距离达成小型化。然而，制程问题仍然限制能达到的微缩量。尤其是，将装置接合至金属化层的接触会面临许多挑战。因此，期望具有改良型的接触及制造方法。
发明内容
本发明的具体实施例提供改良型半导体结构及制造方法，其提供二维自对准的晶体管接触。使用的是两个各由不同材料构成的不同覆盖层。这两个覆盖层可互相选择性蚀刻。一覆盖层用于栅极覆盖，而另一覆盖层用于源极/漏极覆盖。选择性蚀刻程序使所需的栅极和源极/漏极敞开(open)，而阻隔掩模(mask)则用于覆盖不属连接架构任何部分的元件。金属化线件(层件)经沉积而与敞开的元件接触，以在两者之间提供电连接性。这用以改良中段制程(MOL)密度，其常为尺寸调整能力的限制因子。
在第一态样中，本发明的具体实施例提供形成半导体结构的方法，其包含：以第一覆盖层覆盖多个晶体管栅极；以第二覆盖层覆盖多个源极/漏极接触区；在半导体结构上方形成第一掩模，其中，第一掩模使多个栅极接触位置曝露；将第一覆盖层从多个栅极接触位置移除；在半导体结构上方形成第二掩模，其中，第二掩模使多个源极/漏极接触位置曝露；将第二覆盖层从多个源极/漏极接触位置移除；以及在曝露的源极/漏极接触位置和曝露的栅极接触位置上方沉积金属化层。
在第二态样中，本发明的具体实施例提供形成半导体结构的方法，其包含：以第一覆盖层覆盖多个晶体管栅极；以第二覆盖层覆盖多个源极/漏极接触区；在半导体结构上方形成第一掩模，其中，第一掩模使多个栅极接触位置曝露；将第一覆盖层从多个栅极接触位置移除；在半导体结构上方形成第二掩模，其中，第二掩模使多个源极/漏极接触位置曝露；将第二覆盖层从多个源极/漏极接触位置移除；以及在曝露的源极/漏极接触位置和曝露的栅极接触位置上方沉积金属化线件，其中，第一覆盖层包含氧化硅，并且第二覆盖层包含氮化硅。
在第三态样中，本发明的具体实施例提供半导体结构，其包含：多个晶体管栅极；多个晶体管源极/漏极接触区；设置于多个晶体管栅极的子集(subset)上的第一覆盖层；设置于多个晶体管源极/漏极接触区的子集上的第二覆盖层；以及设置于第一覆盖层和第二覆盖层上的金属化层。
附图说明
并入且构成本说明书的一部分的随附图式描述许多本发明所教示的具体实施例，并且连同说明用于解释本发明所教示的原理。
为了清楚描述，某些图中的特定元件可予以省略，或未按照比例绘示。剖面图的形式可为「切片」、或「近观」的剖面图，为了清楚描述，省略可在「真实」剖面图中看到的特定背照线。
在图式的各个图中，类似元件常可用相同数字指称，在这种情况下，最后两位数常可相同，最前数字为图号。再者，为了清楚起见，某些参考元件符号在特定图式中可予以省略。
图1根据描述性具体实施例表示半导体结构由上往下看的图示。
图2针对描述性具体实施例表示半导体结构起始点的剖面图。
图3根据描述性具体实施例表示半导体结构在后续沉积第一掩模层的处理步骤后的剖面图。
图4根据描述性具体实施例表示半导体结构在后续使源极/漏极接触区曝露的处理步骤后的剖面图。
图5根据描述性具体实施例表示半导体结构在后续沉积第二掩模层的处理步骤后的剖面图。
图6根据描述性具体实施例表示半导体结构在后续使晶体管栅极曝露的处理步骤后的剖面图。
图7根据描述性具体实施例表示半导体结构在后续沉积金属化线件的处理步骤后的剖面图。
图8根据描述性替代具体实施例表示两个源极/漏极接触区之间形成连接的半导体结构的剖面图。
图9根据描述性替代具体实施例表示两个晶体管区之间形成连接的半导体结构的剖面图。
图10指示用于本发明具体实施例的程序步骤的流程图。
具体实施方式
将了解本揭示可用许多不同形式予以体现并且不应该被视为受限于本文所提的例示性具体实施例。反而，这些具体实施例经提供为使得本揭示变得透彻并且完整，并且将完整传达本发明的范畴给所属领域的技术人员。本文所用术语的目的仅在于说明特殊具体实施例并且意图不在于限制本揭示。例如，如本文中所用，除上下文另有所指外，单数形式「一」、「一种」、「一个」、以及「该」的用意在于同时包括复数形式。还有，「一」、「一种」、「一个」等用字未指示数量限制，而是指示存在至少一个所引用的项目。将进一步理解的是，用字「包含有」及/或「包含」、或「包括」及/或「包括有」若有用于本说明书，则是指定所述特征、区域、完整物(integer)、步骤、操作、元件、及/或组件的存在性，而非排除一或多个其它其特征、区域、完整物、步骤、操作、元件、组件、及/或群组的存在或增加。
本说明书全篇对于「一具体实施例」、「一个具体实施例」、「具体实施例」、「示例性具体实施例」、或类似用语意指结合具体实施例所述的特殊特征、结构、或特性含括于本发明的至少一具体实施例中。因此，本说明书全篇的用词表现「在一具体实施例中」、「在一个具体实施例」、「在具体实施例」以及类似用语可(但非必要)全部意指相同的具体实施例。
用字「上覆」或「在顶上」、「置于…上」或「上置于」、「在下面的」、「下方」或「下面」意指如第一结构(例如：第一层)等第一元件出现在如第二结构(例如：第二层)等第二元件上，其中，如介面结构(例如：介面层)等中介元件(intervening element)可出现在第一元件与第二元件之间。
图1根据描述性具体实施例表示半导体结构100由上往下看的图示。半导体结构100包含多个栅极102A、102B及102C(大体称为102)。栅极102A、102B及102C可由金属构成，并且可使用取代金属栅极(RMG)制程形成。栅极设置于源极/漏极接触层103上。源极/漏极接触层103有时可称为「TS」层。源极/漏极接触层103设置于半导体基材(substrate)110上方，半导体基材110上形成有多个晶体管源极与漏极。源极与漏极的结构通常一样，并且在本揭示全文中，将术语「源极/漏极」指称为当作晶体管的源极或漏极任一者的主动半导体区。晶体管可为鳍型场效晶体管(finFET)，其源极/漏极为半导体晶鳍的一部分，垂直于栅极102取向。多个金属化线件(104A-104H，大体称为104)也垂直于栅极102取向，并且设置于栅极102上面。
对于给定的电路设计，希望对不同晶体管的各个源极/漏极和栅极进行接触，为的是要实现各种电路，如：逻辑电路、SRAM单元、以及诸如此类。所述接触可连接至各个后段制程(BEOL)金属化层及贯孔层，用以实现所需连接。在某些情况下，希望将邻近的晶体管元件互相连接，例如：将一晶体管的源极/漏极连接至另一晶体管的源极/漏极或栅极。
本发明的具体实施例藉由采用不相似的覆盖材料的选择性蚀刻特性，并且也利用最下面金属化层(通常称为「M0」)与栅极102和源极/漏极接触层103的交截，藉此将接触形成程序简化。在具体实施例中，使用的是两个不同覆盖层：第一覆盖层用于源极/漏极接触层，且第二覆盖层用于栅极。各个栅极和源极/漏极敞开着，而阻隔掩模则保护仍受到覆盖的栅极和源极/漏极。相较于透过微影方法形成个别接触的传统制造方法，阻隔掩模的微影要求得以大幅减少。这由于关键尺寸随着每一世代半导体制造技术持续缩减而尤其如此。本发明的具体实施例提供二维自对准的源极/漏极和栅极接触，简化半导体制造程序，并且也藉由降低如栅极与相邻源极/漏极之间接触短路之类的缺陷风险，将产品良率改良。
如图1所示，在金属化线件104与栅极102和源极/漏极接触层区域103A-C交截的点位，详述多个源极/漏极接触(大致标示为108)以及多个栅极接触(大致标示为106)。区域103A是第一极性CMOS(也就是PMOS)的源极/漏极接触层区域，并且区域103B是相反极性(本实施例中为NMOS)的源极/漏极接触层区域。在具体实施例中，源极/漏极接触层区域103C可为由如同区域103A与103B的源极/漏极接触层所构成的NMOS与PMOS晶体管的「贯通(passthrough)」互连。此贯通互连可将多个NMOS场效晶体管连接至多个PMOS场效晶体管。透过后续图示中所述的程序，仅在有必要时才制作接触，从而能达到所需的连接性。许多不同的连接架构是可行的。例如，请参照金属化线件104A，将相邻于栅极102A的源极/漏极接触连接至相邻于栅极102C的源极/漏极接触。沿着金属化线件104B，在栅极102B上形成有栅极接触，而栅极102A和102C上则没有栅极接触形成。沿着金属线104C有单一源极/漏极接触。沿着金属化线件104D有两个互相连接的栅极接触。栅极102A连接至栅极102C，而未连接至S/D接触「贯通」103C。沿着金属化线件104E，栅极102B连接至栅极102C，同样未连接至S/D接触「贯通」103C。沿着金属化线件104F未形成接触。所有源极/漏极接触区和栅极都维持被覆盖层覆盖。沿着金属化线件104G，形成所谓的栅极-S/D联结结构，将晶体管的栅极连接至其源极/漏极接触的其中一者。沿着金属化线件104H，于两个邻接的源极/漏极接触之间形成连接，但未与中介栅极102B形成接触。所属领域技术人员将了解的是，这些只是实施例，并且实际上，金属化线件可扩及比图1所示多更多的栅极。
图2针对描述性具体实施例表示半导体结构200起始点的剖面图(如沿着图1线条A-A’检视)。半导体结构200包含半导体基材210。在具体实施例中，半导体基材210可包含硅基材。半导体基材210可为主体硅基材，或可为上覆半导体绝缘体(SOI)基材。多个栅极(220A及220B)形成于半导体基材210上。在具体实施例中，栅极220A和220B由金属构成，并且藉由取代金属栅极(RMG)程序形成。在具体实施例中，栅极220A和220B可由钨构成。源极/漏极区212A、212B及212C相邻于栅极220A与220B而成。源极/漏极接触区218A、218B及218C分别在源极/漏极区212A、212B及212C上方形成。一覆盖层224设置于栅极220A和220B每一者的上方。另一覆盖层222设置于源极/漏极接触区218A、218B及218C上方。覆盖层222及覆盖层224属于不同材料，并且较佳是对蚀刻程序互相具有选择性。在一些具体实施例中，覆盖层222可由氧化物(如：氧化硅)构成，而覆盖层224则由氮化物(如：氮化硅)构成。在其它具体实施例中，覆盖层224可由氧化物(如：氧化硅)构成，而覆盖层222则由氮化物(如：氮化硅)构成。场式绝缘体(介电质)214生成金属化线件凹穴215，金属化线件随后沉积于此。在具体实施例中，场式绝缘体214可由硅碳氧化物(SiOC)构成。场式绝缘体214较佳使得能将覆盖层222及覆盖层224两者蚀刻而未将场式绝缘体实质移除。在一些具体实施例中，场式绝缘体可相邻于源极/漏极接触区和栅极。视需要地，如图2所示，间隔物216可相邻于栅极(220A、220B)而置，并且也可相邻于源极/漏极接触区(218A、218B及218C)而置。用于间隔物216的材料较佳使得能将覆盖层222及覆盖层224两者蚀刻而未将间隔物实质移除。在一些具体实施例中，间隔物216由硅氧碳氮化物(SiOCN)构成，或可为硅碳氧化物(SiOC)。
图3根据描述性具体实施例表示半导体结构200在沉积第一掩模层226的后续处理步骤后的剖面图。在具体实施例中，第一掩模层226可由光阻构成。在其它具体实施例中，可将硬掩模用于掩模层226。如图3所示，第一掩模226的例示性沉积图样包含两个区域(226A与226B)，这两个区域之间有一距离D1，其将源极/漏极接触区218B的位置曝露。在这个实施例中，希望敞开源极/漏极接触区218B，距离为D2，但不要敞开相邻的栅极220A或220B。用于掩模层的微影要求使得距离D1有相当宽的范围，并且范围能从恰好稍大于距离D2往上到D1的距离，如图1所示。在一些具体实施例中，D2的范围可自约15纳米至约40纳米，并且D1的范围可自约D2加5纳米至约D2的3倍。因此，D1的容限范围宽，这使得掩模层226在执行微影时较直接。
图4根据描述性具体实施例表示半导体结构200在使源极/漏极接触区曝露的后续处理步骤后的剖面图。源极/漏极接触区218B使用选择性蚀刻程序予以曝露，其仅将源极/漏极接触区上方的覆盖层222移除，但未将设置于栅极(220A、220B)上方的覆盖层224移除。在具体实施例中，可使用选择性反应性离子蚀刻(RIE)程序，将源极/漏极接触区218B上方的覆盖层移除。在另一具体实施例中，取决于用于覆盖层的材料，可使用如SiCoNi蚀刻之类的等向性「数位」蚀刻技术。在覆盖层移除后，也将第一掩模层(图3的226)移除。
图5根据描述性具体实施例表示半导体结构200在沉积第二掩模层230的后续处理步骤后的剖面图。在这个实施例中，希望敞开栅极218C，距离为D3，但不要敞开相邻的栅极220B。因此，场式绝缘体214与第二掩模层230之间的距离D4能远大于D3。在一些具体实施例中，D3的范围可自约15纳米至约40纳米，并且D4的范围可自约D3加5纳米至约D3的3倍。因此，D4的容限范围宽，这使得掩模层230在执行微影时较直接。
图6根据描述性具体实施例表示半导体结构200在使晶体管栅极曝露的后续处理步骤后的剖面图。在具体实施例中，可使用选择性反应性离子蚀刻(RIE)程序，将栅极220B上方的覆盖层移除。在另一具体实施例中，取决于用于覆盖层的材料，可使用如SiCoNi蚀刻之类的等向性蚀刻。在覆盖层移除后，也将第二掩模层(图5的230)移除。
图7根据描述性具体实施例表示半导体结构200在沉积金属化线件232的后续处理步骤后的剖面图。金属化线件232藉由场式绝缘体214予以限制。在具体实施例中，金属化线件232可由钨、铜或铝构成。其它材料是可行的。可使用化学气相沉积(CVD)、物理气相沉积(PVD)、或电镀程序将金属化线件232沉积。由于金属化线件232的沉积，栅极220B与源极/漏极接触区218B电性接触。这导致类似于沿着图1金属化线件104G所示的「栅极-源极/漏极联结」。藉由将金属化线件与已敞开的栅极和源极/漏极接触区(已移除其各别覆盖层)进行交截，形成用于栅极与源极/漏极接触区的接触。与栅极和源极/漏极的接触属于二维自对准，允许电路密度提升且产品良率改善。与使用贯孔抵达金属化线件的传统设计对照，装置效能因连接路径较短、电阻降低而提升，成为另外的效益。在这种情况下，金属化线件是直接位于曝露(敞开)的栅极和曝露(敞开)的源极/漏极接触区上。在具体实施例中，栅极和源极/漏极接触区的子集维持以覆盖层覆盖。对于这些未曝露(未敞开)的元件(源极/漏极接触区和栅极)，金属化线件(层件)也与第一和第二覆盖层直接实体接触。
图8根据描述性替代具体实施例表示两个源极/漏极接触区之间形成连接的半导体结构300的剖面图。如前述，在图式的各个图中，类似元件可用相同数字指称，在这种情况下，最后两位数常可相同，最前数字为图号。例如，图3的半导体基材310类似于图2的半导体基材210。在这个实施例中，金属化线件322在源极/漏极区312A与源极/漏极区312C之间提供电连接性，在栅极320A与320B、以及源极/漏极区318B上方通过。类似于图1至图7所示的程序，藉由选择适当的第一和第二掩模图样，理想的连接点有将覆盖层移除而由金属化线件332致能连接性。
图9根据描述性替代具体实施例表示两个晶体管区之间形成连接的半导体结构400的剖面图。在这个实施例中，金属化线件432在栅极420A与栅极420B之间提供电连接性，在源极/漏极区418B上方通过。类似于图1至图7所示的程序，藉由选择适当的第一和第二掩模图样，理想的连接点有将覆盖层移除而由金属化线件422致能连接性。
图10指示用于本发明具体实施例的程序步骤的流程图1000。在处理步骤1050中，于晶体管栅极上方沉积第一覆盖层(例如：图2的224)。在处理步骤1052中，于源极/漏极接触区上方沉积第二覆盖层(例如：图2的222)。尽管流程图1000示出在栅极上方沉积覆盖层，接着在源极/漏极接触区上方沉积不同的覆盖层，本发明的具体实施例可将顺序逆转，并且先在源极/漏极接触区上方沉积覆盖材料，然后在栅极上方沉积材料不同的覆盖层。在处理步骤1053中，将介电层沉积并且将金属沟槽敞开，使栅极和源极/漏极覆盖层曝露。在处理步骤1054中，形成第一掩模层(请参阅图3的226)。第一掩模层覆盖不应被敞开的栅极。在处理步骤1056中，选择的栅极(未被第一掩模层覆盖)藉由将那些栅极(例如：图6的220B)上面的覆盖层移除而敞开。在处理步骤1058中，形成第二掩模(请参阅图5的230)。第二掩模层覆盖不应被敞开的源极/漏极接触区。在处理步骤1060中，选择的源极/漏极接触区(未被第二掩模层覆盖)藉由将那些源极/漏极接触区(例如：图4的218B)上面的覆盖层移除而敞开。在处理步骤1062中，沉积金属化线件，其在敞开的元件(栅极与源极/漏极)之间提供电连接性。尽管流程图1000示出先将栅极敞开，接着将源极/漏极接触区敞开，本发明的具体实施例可将顺序逆转，并且先将源极/漏极接触区敞开，接着才将栅极敞开。
如现在能领会的是，本发明的具体实施例提供改良型半导体结构及制造方法，其提供二维自对准的晶体管接触。这用以改良中段制程(MOL)密度，其常为尺寸调整能力的限制因子。
尽管已搭配例示性具体实施例特别表示并且说明本发明，仍将了解所属领域的技术人员将想到变异与改进。例如，虽然描述性具体实施例在本文说明为一连串动作或事件，将了解除非有特别说明，本发明不局限于此等动作或事件所述排序。根据本发明，某些动作可以不同顺序出现及/或与本文所示及/或所述不同的其它动作或事件同时发生。另外，可无需将所有所述步骤都用于实现如本发明所述的方法。此外，如本发明所述的方法可联合本文所示与所述架构的形成及/或处理以及联合其它未描述的架构予以实现。因此，要了解所附权利要求书的用意在于涵盖所有落于本发明真实精神内的此等改进及变更。

Claims (20)

1.一种形成半导体结构的方法，包含：
以第一覆盖层覆盖多个晶体管栅极；
以第二覆盖层覆盖多个源极/漏极接触区；
在该半导体结构上方形成第一掩模，其中，该第一掩模使多个栅极接触位置曝露；
将该第一覆盖层从该多个栅极接触位置移除；
在该半导体结构上方形成第二掩模，其中，该第二掩模使多个源极/漏极接触位置曝露；
将该第二覆盖层从该多个源极/漏极接触位置移除；以及
在所述曝露的源极/漏极接触位置以及曝露的栅极接触位置上方沉积金属化层。
2.根据权利要求1所述的方法，其中，以第一覆盖层覆盖多个晶体管栅极包含沉积氮化硅。
3.根据权利要求2所述的方法，其中，以第二覆盖层覆盖多个源极/漏极接触区包含沉积氧化硅。
4.根据权利要求1所述的方法，其中，沉积金属化层包含沉积钨。
5.根据权利要求1所述的方法，其中，沉积金属化层包含沉积铜。
6.根据权利要求1所述的方法，进一步包含形成栅极SD联结结构，该栅极SD联结结构将该多个晶体管栅极的一者连接至相邻源极/漏极接触区。
7.根据权利要求1所述的方法，进一步包含将该多个晶体管栅极的第一晶体管栅极连接至该多个晶体管栅极的第二晶体管栅极。
8.根据权利要求1所述的方法，进一步包含将该多个源极/漏极接触区的第一源极/漏极接触区连接至该多个源极/漏极接触区的第二源极/漏极接触区。
9.一种形成半导体结构的方法，包含：
以第一覆盖层覆盖多个晶体管栅极；
以第二覆盖层覆盖多个源极/漏极接触区；
在该半导体结构上方形成第一掩模，其中，该第一掩模使多个栅极接触位置曝露；
将该第一覆盖层从该多个栅极接触位置移除；
在该半导体结构上方形成第二掩模，其中，该第二掩模使多个源极/漏极接触位置曝露；
将该第二覆盖层从该多个源极/漏极接触位置移除；以及
在该曝露的源极/漏极接触位置及曝露的栅极接触位置上方沉积金属化线件，其中，该第一覆盖层包含氧化硅，以及该第二覆盖层包含氮化硅。
10.根据权利要求9所述的方法，其中，沉积金属化线件包含沉积钨。
11.根据权利要求9所述的方法，进一步包含形成栅极SD联结结构，该栅极SD联结结构将该多个晶体管栅极的一者连接至相邻源极/漏极接触区。
12.根据权利要求9所述的方法，进一步包含将该多个晶体管栅极的第一晶体管栅极连接至该多个晶体管栅极的第二晶体管栅极。
13.根据权利要求9所述的方法，进一步包含将该多个源极/漏极接触区的第一源极/漏极接触区连接至该多个源极/漏极接触区的第二源极/漏极接触区。
14.根据权利要求9所述的方法，进一步包含使用贯通互连，将含有NMOS晶体管的第一源极/漏极接触层区域连接至含有PMOS晶体管的第二源极/漏极接触层区域。
15.一种半导体结构，包含：
多个晶体管栅极；
多个晶体管源极/漏极接触区；
设置于该多个晶体管栅极的子集上的第一覆盖层；
设置于该多个晶体管源极/漏极接触区的子集上的第二覆盖层；以及
设置于该第一覆盖层及第二覆盖层上的金属化层。
16.根据权利要求15所述的半导体结构，其中，该金属化层与该多个晶体管栅极的至少一晶体管栅极电性接触。
17.根据权利要求15所述的半导体结构，其中，该金属化层与该多个晶体管源极/漏极接触区的至少一源极/漏极接触区电性接触。
18.根据权利要求15所述的半导体结构，进一步包含限制该金属化层的介电区。
19.根据权利要求18所述的半导体结构，进一步包含与该多个晶体管栅极的每一个晶体管栅极相邻的多个间隔物。
20.根据权利要求19所述的半导体结构，其中，该第一覆盖层由氮化硅构成，该第二覆盖层由氧化硅构成，该介电区由硅碳氧化物构成，以及该多个间隔物由选自由硅碳氧化物及硅氧碳氮化物所组成群组的材料构成。
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