CN110277362B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN110277362B
CN110277362B CN201810203798.8A CN201810203798A CN110277362B CN 110277362 B CN110277362 B CN 110277362B CN 201810203798 A CN201810203798 A CN 201810203798A CN 110277362 B CN110277362 B CN 110277362B
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conductive portion
layer
semiconductor structure
conductive
forming
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CN110277362A (zh
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许智凯
傅思逸
邱淳雅
吴骐廷
陈金宏
林毓翔
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构及其形成方法。半导体结构包括基底、栅结构、及导电元件。栅结构在基底上。栅结构包括栅电极与盖层。盖层在该栅电极上。导电元件邻接栅结构的外侧表面。导电元件包括下导电部及上导电部。上导电部电连接在下导电部上，并邻接盖层。下导电部与上导电部之间具有一界面。界面低于盖层的一上表面。

Description

半导体结构及其形成方法
技术领域
本发明涉及一种半导体结构及其形成方法。
背景技术
随着半导体制作工艺的线宽的不断缩小，半导体结构包括例如晶体管或存储阵列等等的尺寸不断朝向微型化发展。然而，临界尺寸愈小，制作工艺必须愈精准，否则一个步骤的制作工艺偏移或副效应(side effect)便会使得形成的半导体装置效能不佳。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，以解决上述问题。
为达上述目的，本发明提出一种半导体结构。半导体结构包括基底、栅结构、及导电元件。栅结构在基底上。栅结构包括栅电极与盖层。盖层在该栅电极上。导电元件邻接栅结构的外侧表面。导电元件包括下导电部及上导电部。上导电部电连接在下导电部上，并邻接盖层。下导电部与上导电部之间具有一界面。界面低于盖层的一上表面。
本发明还提出一种半导体结构的形成方法，其包括以下步骤。进行一蚀刻步骤移除栅电极外侧的基底上的第一材料层以形成第一开口。在该蚀刻步骤中，在栅电极上方的盖层是用作蚀刻停止层。在第一开口中形成下导电部。形成第二材料层在下导电部上。进行一另一蚀刻步骤移除第二材料层以形成露出下导电部的一第二开口，在该另一蚀刻步骤中，盖层是用作蚀刻停止层。在第二开口中形成上导电部。
为了对本发明的上述及其他方面有更佳的了解，下文特举实施例，并配合所附的附图详细说明如下：
附图说明
图1A至图12D为第一实施例的概念的半导体结构的形成方法的示意图；
图13为第二实施例的概念的半导体结构的剖视图；
图14A至图14C为第三实施例的概念的半导体结构及其制造方法的示意图；
图15为第四实施例的概念的半导体结构的剖视图；
图16为第五实施例的概念的半导体结构的剖视图。
具体实施方式
以下以一些实施例做说明。需注意的是，本发明并非显示出所有可能的实施例，未于本发明提出的其他实施态样也可能可以应用。再者，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和图示内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。另外，实施例中的叙述，例如细部结构、制作工艺步骤和材料应用等等，仅为举例说明之用，并非对本发明欲保护的范围做限缩。实施例的步骤和结构各的细节可在不脱离本发明的精神和范围内根据实际应用制作工艺的需要而加以变化与修饰。以下是以相同/类似的符号表示相同/类似的元件做说明。
图1A至图12D绘示根据第一实施例的概念的半导体结构的形成方法。
图1A绘示半导体结构的上视图。图1B绘示半导体结构沿AB线的剖视图。
请参照图1B，提供基底102。基底102可包括硅基底、绝缘层上覆硅、或其它合适的半导体基底。隔离元件104可形成基底102中。可利用隔离元件104定义出主动区域。隔离元件104可包括浅沟槽隔离、深沟槽隔离、场氧化结构、或其它合适的隔离设计。栅介电层106形成在基底102上，栅介电层106可为一字型(如图1B所示)或是U型。栅电极108可形成在栅介电层106上。栅电极108可包括金属或其它合适的导电材料。盖层110可形成在栅电极108上。盖层110的材质可包括但不限于氮化物，例如氮化硅等等。间隙壁112可形成在栅介电层106、栅电极108及盖层110的侧壁上。间隙壁112的材质可包括但不限于氮化物，例如氮化硅等等。源/漏极113可形成在栅电极108外侧的基底102中。源/漏极113可利用掺杂的方式形成。一实施例中，源/漏极113也可包括金属硅化层。材料膜116可形成在间隙壁112的侧壁上及基底102上。材料膜116的材质可包括但不限于氮化物，例如氮化硅等等。栅结构G，例如在第一方向D1上隔开配置的栅结构G1-G5，各可包括栅介电层106、栅电极108、盖层110、间隙壁112、及间隙壁114。间隙壁114可为材料膜116在间隙壁112的侧壁上的部分。第一材料层119可形成在栅结构G上。第一材料层119可包括形成在栅结构G1-G5的侧壁之间的第一材料部分118，及形成在栅结构G1-G5的上表面上的第二材料部分120。一实施例中，第一材料部分118包括例如层间介电层，材质可包括氧化物，例如氧化硅等等。第二材料部分120可包括氧化物，例如氧化硅等等。硬掩模122形成在第二材料部分120上。硬掩模122的材质可包括但不限于氮化物，例如氮化钛(TiN)、氮化硅(SiN)，或其它合适的材质。可对硬掩模122进行图案化以形成孔洞124。
请参照图1A，为求简单了解，其仅显示半导体结构的硬掩模122、栅结构G(包括栅结构G1-G5)与鳍元件111。硬掩模122包括数个孔洞124。图1A也显示半导体结构对应一孔洞124的部分的放大图，其中，延伸在第一方向D1的栅结构G1-G5可形成于沿第二方向D2延伸的鳍元件111上。一实施例中，晶体管可包括栅结构G、源/漏极113及鳍元件111。
请参照图2，可利用蚀刻步骤移除硬掩模122的孔洞124露出的第一材料层119的第二材料部分120及第一材料部分118以形成第一开口126。实施例中，用以形成第一开口126的蚀刻步骤是使用栅结构G的盖层110作为蚀刻停止层。然后可移除硬掩模122。硬掩模122可利用蚀刻方式或化学机械研磨移除。一实施例中，硬掩模122可利用用以移除第一材料层119的蚀刻步骤移除。另一实施例中，硬掩模122可利用额外的步骤个别移除。
请参照图3，可利用蚀刻步骤移除材料膜116位于基底102上的部分，使得第一开口126露出基底102(或源/漏极113)。
请参照图4，可在第一开口126中形成下导电部128。举例来说，下导电部128可包括导电膜130及导电材料132。导电膜130形成在第一开口126露出的基底102(或源/漏极113)的上表面及间隙壁114的侧表面上，并可形成在栅结构G的上表面及第二材料部分120上。导电材料132可形成在导电膜130上，并填满第一开口126。一实施例中，导电膜130及导电材料132的材质不相同。举例来说，导电膜130可为扩散阻障层，材质可例如包括但不限于TaN、TiN、MoN等等。导电材料132可包括例如钨、钴等等。然而本发明不限于此，导电膜130及导电材料132也可使用其它具有导电性质的合适材质。
请参照图5，可利用化学机械研磨进行平坦化步骤以得到至少对齐盖层110的上表面的平坦表面。
请参照图6，可对第一开口126中的下导电部128进行回蚀刻步骤。绝缘层134可形成在第一开口126中，并延伸在栅结构G的上表面上。一实施例中，绝缘层134可为利用沉积方法形成的一共形薄膜。绝缘层134的材质包括但不限于氮化硅碳(SiCN)、碳化硅(SiC)等等。
请参照图7，介电层136可形成在绝缘层134上。介电层136可利用沉积的方式形成。介电层136的材质包括但不限于氧化物，例如氧化硅等等。也可对介电层136进行化学机械研磨以平坦化其上表面。一实施例中，第二材料层140可包括绝缘层134及介电层136。可在介电层136上形成硬掩模142。一实施例中，硬掩模142的材质包括但不限于氮化钛(TiN)等等。
图8A绘示半导体结构的上视图。图8B绘示半导体结构沿AB线的剖视图。图8C绘示半导体结构沿CD线的剖视图。为求简单了解，图8A仅显示半导体结构的硬掩模142、栅结构G(包括栅结构G1-G5)与鳍元件111。请参照图8A与图8B，可对硬掩模142进行图案化，以形成孔洞144AB。请参照图8A与图8C，可对硬掩模142进行图案化，以形成孔洞144CD。一实施例中，孔洞144AB与孔洞144CD可利用相同制作工艺同时形成。然后可移除硬掩模142。
请参照图9A与图9B，可进行蚀刻步骤以移除硬掩模142的孔洞144AB及孔洞144CD露出的第二材料层140，以分别形成露出下导电部128的第二开口146AB与第二开口146CD。一实施例中，用以形成第二开口146AB与第二开口146CD的蚀刻步骤是自对准栅结构G，其中栅结构G的盖层110可用作蚀刻停止层。例如图9A中的第二开口146AB是利用栅结构G1、G2、G4、G5作为蚀刻停止层形成。例如图9B中的第二开口146CD是利用栅结构G2、G3、G4作为蚀刻停止层形成。请参照图9A与图9B，一实施例中，蚀刻制作工艺可能会稍微消耗掉盖层110露出孔洞144AB/孔洞144CD的部分，因而高度降低。举例来说，栅结构G2的盖层110的上表面包括对应孔洞144AB、144CD而被蚀刻步骤消耗掉所形成的第一上表面150，及/或非对应孔洞144AB、144CD而未被蚀刻步骤消耗掉的第二上表面152。第一上表面150低于第二上表面152。也可以此类推其它栅结构元件情况。
请参照图10A至图10D。图10A绘示半导体结构的上视图。图10B绘示半导体结构沿AB线的剖视图。图10C绘示半导体结构沿CD线的剖视图。图10D绘示半导体结构沿EF线的剖视图。可形成光致抗蚀剂层154覆盖整个半导体结构，并对光致抗蚀剂层154进行图案化以形成开孔156EF。一实施例中，光致抗蚀剂层154也可包括抗反射层。为求简单了解，图10A仅显示半导体结构的光致抗蚀剂层154、栅结构G(包括栅结构G1-G5)与鳍元件111。
请参照图11，其绘示半导体结构沿EF线的剖视图。利用蚀刻步骤将光致抗蚀剂层154的开孔156EF露出的第二材料层140及栅结构G2、G4的盖层110移除以形成露出栅电极108的孔洞160EF。然后可移除光致抗蚀剂层154。
图12A绘示半导体结构的上视图。图12B绘示半导体结构沿AB线的剖视图。图12C绘示半导体结构沿CD线的剖视图。图12D绘示半导体结构沿EF线的剖视图。请参照图12A与图12B，上导电部162AB可形成在第二开口146AB中。请参照图12A与图12C，上导电部162CD可形成在第二开口146CD中。请参照图12A与图12D，上导电部162EF可形成在孔洞160EF中。请参照图12B至图12C，上导电部162AB/上导电部162CD可包括形成在第二开口146AB/第二开口146CD的底部与侧壁上的导电膜164，及填满第二开口146AB/第二开口146CD的导电材料166。请参照图12D，上导电部162EF可包括形成在孔洞160EF的底部与侧壁上的导电膜164，及填满第二开口孔洞160EF的导电材料166。上导电部162EF可电连接栅电极108。
请参照图12B至图12C，一实施例中，上导电部162AB、上导电部162CD与上导电部162EF可利用相同的制作工艺同时形成。一实施例中，导电膜164及导电材料166的材质不相同。举例来说，导电膜164可为扩散阻障层，材质可例如包括但不限于TaN、TiN、MoN等等。导电材料166可包括例如钨、钴等等。然而本发明不限于此，导电膜164及导电材料166也可使用其它具有导电性质的合适材质。一实施例中，可利用化学机械研磨对上导电部162AB、上导电部162CD与上导电部162EF进行平坦化制作工艺。
图12B所示的导电元件170包括电连接的上导电部162AB及下导电部128。图12C所示的导电元件170包括电连接的上导电部162CD及下导电部128。在图12B及图12C中，导电元件170可电连接源/漏极113。导电元件170的上导电部162AB/162CD可邻接栅结构G的间隙壁114的外侧表面及上表面、间隙壁112的上表面、及盖层110的第一上表面150。导电元件170可未邻接盖层110的第二上表面152。上导电部162AB、162CD可具有一横向尺寸(例如在盖层110上方的部分于第一方向D1上的尺寸)大于下导电部128。下导电部128与上导电部162AB/162CD之间具有界面172(包括上导电部162AB/162CD的导电膜164与下导电部128的导电膜130之间的界面，与上导电部162AB/162CD导电膜164与下导电部128的导电材料132之间的界面)，界面172低于盖层110的上表面(包括第一上表面150及第二上表面152)。界面172为下导电部128与上导电部162AB/162CD之间一横向的共平面(例如将第一方向D1与第二方向D2分别视为x轴方向与y轴方向定义出的xy-平面)。请参照图12B，举例来说，栅结构G2的盖层110具有相对的第一侧表面174及第二侧表面176，其中上导电部162AB是在第一侧表面174上，且绝缘层134在第二侧表面176上。绝缘层134与下导电部128之间具有一界面182，其低于盖层110的上表面(包括第一上表面150及第二上表面152)。可以此类推其它栅结构与其它元件的关系。
请参照图12A至图12D，实施例中，电连接源/漏极113的上导电部162AB与162CD，及电连接栅结构G的上导电部162EF都是形成在主动区域中，故根据实施例概念的半导体结构可具有较高的装置密度。举例来说，一般的半导体结构中，电连接栅结构G的上导电部是配置在主动区域外侧，故会占用额外的面积导致装置密度难以提升。故根据实施例概念的半导体结构比起一般的半导体结构可具有较高的装置密度。此外，上导电部162AB与上导电部162CD可利用栅结构G的盖层110作为硬掩模形成，因此高度上可尽量靠近下导电部128而能对基底102(或源/漏极113)产生较低的电阻，从而能提高装置的操作效能。
本发明的概念也可适当调变。举例来说，一实施例中，可在图3所述的蚀刻步骤之后，对第一开口126露出的源/漏极113进行金属硅化步骤。一实施例中，硬掩模122(图1A、图1B)也可利用图5所述的化学机械研磨步骤移除。
图13绘示根据第二实施例的概念的半导体结构的剖视图，其与图12D的差异在于，上导电部262EF同时电连接至栅结构G2与栅结构G3的栅电极108。
图14A至图14C绘示根据第三实施例的概念的半导体结构及其制造方法。图14A与图12B的差异，及图14B与图12D的差异说明如下。绝缘层134是以绝缘层234取代。第二材料层240可包括绝缘层234及介电层136。绝缘层234的上表面可齐平栅结构G的间隙壁112与间隙壁114的上表面。绝缘层234的材质包括但不限于氮化硅碳(SiCN)、碳化硅(SiC)等等。源/漏极213可包括利用掺杂基底102形成的源/漏极113，与形成在源/漏极113上的金属硅化层321。金属硅化层321的材质可包括但不限于硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi)等等。举例来说，此实施例的半导体结构的制造方法可将图6所示的步骤替换为将绝缘层234填满在第一开口126中，并可进行化学机械研磨以平坦化上表面，然后以类似的概念进行后续的制造步骤获得，也可以此类推半导体结构其它部分的结构情况。一实施例中，举例来说，图11的步骤可替换成图14C的剖视图，其中，用以形成孔洞160EF的蚀刻步骤系可利用绝缘层234作为硬掩模，而齐平栅结构G的绝缘层234能提供优异的蚀刻掩模效能，更能避免因过度蚀刻造成后续形成的上导电部162EF(图14B)不期望地短接至栅结构G外侧的下导电部128。
图15绘示根据第四实施例的概念的半导体结构的剖视图，其与图14A～图14C的差异在于说明如下。绝缘层334包括第一绝缘层334A与第二绝缘层334B，且第二绝缘层334B在第一绝缘层334A的顶表面上。第一绝缘层334A与第二绝缘层334B可使用不同的材质。举例来说，第一绝缘层334A的材质包括但不限于氧化物，例如氧化硅等等。第二绝缘层334B的材质包括但不限于氮化硅碳(SiCN)、碳化硅(SiC)等等。举例来说，此实施例的半导体结构的制造方法可将图6所示的步骤替换为，将第一绝缘层334A形成在第一开口126中然后进行回蚀刻，然后形成第二绝缘层334B填满第一开口126，并可进行化学机械研磨以平坦化上表面，然后以类似的概念进行后续的制造步骤获得，也可以此类推半导体结构其它部分的结构情况。一实施例中，第二绝缘层334B可用做硬掩模。
图16绘示根据第五实施例的概念的半导体结构的剖视图，其与图15的差异在于说明如下。绝缘层334包括第一绝缘层334A与第二绝缘层334B，其中第一绝缘层334A具有U形状，且第二绝缘层334B形成在第一绝缘层334A上。举例来说，此实施例的半导体结构的制造方法可将图6所示的步骤替换为，以沉积方法将共形的第一绝缘层334A形成在第一开口126中，然后形成第二绝缘层334B填满第一开口126，并可进行化学机械研磨以平坦化上表面，然后以类似的概念进行后续的制造步骤获得，也可以此类推半导体结构其它部分的结构情况。
综上所述，虽然结合以上实施例公开了本发明，然而其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (16)

1.一种半导体结构，其特征在于，包括：
基底；
栅结构，在该基底上，该栅结构包括栅电极与盖层，该盖层在该栅电极上；
导电元件，邻接该栅结构的一外侧表面，该导电元件包括：
下导电部；及
上导电部，电连接在该下导电部上，并邻接该盖层，该下导电部与该上导电部之间具有一界面，该界面低于该盖层的一上表面；
另一下导电部，在该栅结构相对于该外侧表面的另一外侧表面；及
绝缘层，其中该盖层具有相对的第一侧表面与第二侧表面，该上导电部在该第一侧表面上，该绝缘层在该第二侧表面上且在该另一下导电部上，
其中在一横方向上，该上导电部的尺寸是大于该下导电部的尺寸，该上导电部邻接该盖层的该上表面的一部分。
2.如权利要求1所述的半导体结构，其中该下导电部与该上导电部分别包括不同的导电材料。
3.如权利要求1所述的半导体结构，其中该下导电部与该上导电部之间的该界面为一横向的共平面。
4.如权利要求1所述的半导体结构，其中该上导电部邻接该盖层的该上表面。
5.如权利要求1所述的半导体结构，其中该盖层包括相邻的第一上表面与第二上表面，该第一上表面低于该第二上表面，其中该上导电部邻接该第一上表面，但未邻接该第二上表面。
6.如权利要求1所述的半导体结构，其中该绝缘层不存在于该上导电部与该盖层之间。
7.如权利要求1所述的半导体结构，其中该绝缘层与该另一下导电部之间具有一界面低于该盖层的该上表面。
8.如权利要求1所述的半导体结构，其中该半导体结构包括晶体管，该晶体管包括该栅结构与源/漏极，其中该导电元件电连接该源/漏极。
9.如权利要求1所述的半导体结构，其中该栅结构还包括间隙壁，在该栅电极的一侧表面上。
10.一种半导体结构的形成方法，其特征在于，包括：
进行一蚀刻步骤移除一栅电极外侧的一基底上的一第一材料层以形成一第一开口，其中在该蚀刻步骤中，在该栅电极上方的一盖层是用作蚀刻停止层；
在该第一开口中形成一下导电部；
形成一第二材料层在该下导电部上，其中该第二材料层的形成方法包括形成一绝缘层在该第一开口中，并位于该下导电部上与该盖层的一侧表面上；
进行一另一蚀刻步骤移除该第二材料层以形成露出该下导电部的一第二开口，其中在该另一蚀刻步骤中，该盖层是用作蚀刻停止层；及
在该第二开口中形成一上导电部,
其中，该形成方法还包括在形成该第二材料层之前对该第一开口中的该下导电部进行一回蚀刻制作工艺。
11.如权利要求10所述的半导体结构的形成方法，其中该下导电部的形成方法包括：
形成一导电膜于该第一开口的底部与侧壁上；及
形成一导电材料填满该第一开口。
12.如权利要求11所述的半导体结构的形成方法，其中该导电膜与该导电材料的材质不相同。
13.如权利要求10所述的半导体结构的形成方法，其中该上导电部的形成方法包括：
形成一导电膜于该第二开口的底部与侧壁上；及
形成一导电材料填满该第二开口。
14.如权利要求13所述的半导体结构的形成方法，其中该导电膜与该导电材料的材质不相同。
15.如权利要求10所述的半导体结构的形成方法，还包括进行一又另一蚀刻步骤移除该盖层以形成露出该栅电极的一孔洞。
16.如权利要求15所述的半导体结构的形成方法，还包括形成另一上导电部在该孔洞中。
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