TWI525749B - 二維自對準之電晶體接觸 - Google Patents

二維自對準之電晶體接觸 Download PDF

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TWI525749B
TWI525749B TW103130078A TW103130078A TWI525749B TW I525749 B TWI525749 B TW I525749B TW 103130078 A TW103130078 A TW 103130078A TW 103130078 A TW103130078 A TW 103130078A TW I525749 B TWI525749 B TW I525749B
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Taiwan
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source
drain contact
gate
layer
transistor
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TW103130078A
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TW201539654A (zh
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奇宏 安迪 韋
古拉梅 伯奇
馬克Ａ 扎列斯基
特尼 古哈 尼歐
傑森Ｅ 史蒂芬斯
宗郁 桂
吉 奈恩
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格羅方德半導體公司
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

二維自對準之電晶體接觸
本發明基本上係關於半導體製造，並且更尤指用於電晶體接觸之結構及製造方法。
隨著技術進步，必須將電子裝置之製造改良以滿足電子裝置行動化、重量輕、有效率的趨勢。除了縮減半導體裝置之尺寸外，也能藉由縮減半導體裝置之間的距離達成小型化。然而，製程問題仍然限制能達到的微縮量。尤其是，將裝置接合至金屬化層的接觸會面臨許多挑戰。因此，期望具有改良型的接觸及製造方法。
本發明之具體實施例提供改良型半導體結構及製造方法，其提供二維自對準之電晶體接觸。使用的是兩個各由不同材料構成的不同覆蓋層。這兩個覆蓋層可互相選擇性蝕刻。一覆蓋層係用於閘極覆蓋，而另一覆蓋層係用於源極/汲極覆蓋。選擇性蝕刻程序使所需的閘極和源極/汲極敞開，而阻隔遮罩則係用於覆蓋不屬連接架構任何部分的元件。金屬化線件(層件)經沉積而與敞開之元件 接觸，以在兩者之間提供電連接性。這用以改良中段製程(MOL)密度，其常為尺寸調整能力的限制因子。
在第一態樣中，本發明之具體實施例提供形成半導體結構之方法，其包含：以第一覆蓋層覆蓋複數個電晶體閘極；以第二覆蓋層覆蓋複數個源極/汲極接觸區；在半導體結構上方形成第一遮罩，其中第一遮罩使複數個閘極接觸位置曝露；將第一覆蓋層從複數個閘極接觸位置移除；在半導體結構上方形成第二遮罩，其中第二遮罩使複數個源極/汲極接觸位置曝露；將第二覆蓋層從複數個源極/汲極接觸位置移除；以及在曝露之源極/汲極接觸位置和曝露之閘極接觸位置上方沉積金屬化層。
在第二態樣中，本發明之具體實施例提供形成半導體結構之方法，其包含：以第一覆蓋層覆蓋複數個電晶體閘極；以第二覆蓋層覆蓋複數個源極/汲極接觸區；在半導體結構上方形成第一遮罩，其中第一遮罩使複數個閘極接觸位置曝露；將第一覆蓋層從複數個閘極接觸位置移除；在半導體結構上方形成第二遮罩，其中第二遮罩使複數個源極/汲極接觸位置曝露；將第二覆蓋層從複數個源極/汲極接觸位置移除；以及在曝露之源極/汲極接觸位置和曝露之閘極接觸位置上方沉積金屬化線件，其中第一覆蓋層包含氧化矽，並且第二覆蓋層包含氮化矽。
在第三態樣中，本發明之具體實施例提供半導體結構，其包含：複數個電晶體閘極；複數個電晶體源極/汲極接觸區；設置於複數個電晶體閘極之子集上的第 一覆蓋層；設置於複數個電晶體源極/汲極接觸區之子集上的第二覆蓋層；以及設置於第一覆蓋層和第二覆蓋層上之金屬化層。
100‧‧‧半導體結構
102A、102B、102C‧‧‧閘極
103A、103B、103C‧‧‧源極/汲極接觸層區域
104A、104B、104D、104E、104F、104G、104H‧‧‧金屬化線件
104C‧‧‧金屬線
106‧‧‧閘極接觸
108‧‧‧源極/汲極接觸
110、210、310‧‧‧半導體基材
200、400‧‧‧半導體結構
212A、212B、212C‧‧‧源極/汲極區
214‧‧‧場式絕緣體
215‧‧‧金屬化線件凹穴
216‧‧‧間隔物
218A、218B、218C‧‧‧源極/汲極接觸區
220A、220B、320A、320B、420A、420B‧‧‧閘極
222、224‧‧‧覆蓋層
226‧‧‧第一遮罩層
226A、226B‧‧‧區域
230‧‧‧第二遮罩層
232、332、342‧‧‧金屬化線件
312A、312C、318B、418B‧‧‧源極/汲極區
1000‧‧‧流程圖
1050、1052、1053、1054、1056、1058、1060、1062‧‧‧處理步驟
併入且構成本說明書之一部分的隨附圖式描述許多本發明所教示之具體實施例，並且連同說明用於解釋本發明所教示之原理。
為了清楚描述，某些圖中的特定元件可予以省略，或未按照比例繪示。剖面圖的形式可為「切片」、或「近觀」之剖面圖，為了清楚描述，省略可在「真實」剖面圖中看到的特定背照線。
在圖式的各個圖中，類似元件常可用相同數字指稱，在這種情況下，最後兩位數常可相同，最前數字為圖號。再者，為了清楚起見，某些參考元件符號在特定圖式中可予以省略。
第1圖根據描述性具體實施例表示半導體結構由上往下看的圖示。
第2圖針對描述性具體實施例表示半導體結構起始點的剖面圖。
第3圖根據描述性具體實施例表示半導體結構在後續沉積第一遮罩層之處理步驟之後的剖面圖。
第4圖根據描述性具體實施例表示半導體結構在後續使源極/汲極接觸區曝露之處理步驟之後的剖面圖。
第5圖根據描述性具體實施例表示半導體結構在後續 沉積第二遮罩層之處理步驟之後的剖面圖。
第6圖根據描述性具體實施例表示半導體結構在後續使電晶體閘極曝露之處理步驟之後的剖面圖。
第7圖根據描述性具體實施例表示半導體結構在後續沉積金屬化線件之處理步驟之後的剖面圖。
第8圖根據描述性替代具體實施例表示兩個源極/汲極接觸區之間形成連接之半導體結構的剖面圖。
第9圖根據描述性替代具體實施例表示兩個電晶體區之間形成連接之半導體結構的剖面圖。
第10圖係指示用於本發明具體實施例之程序步驟的流程圖。
將了解本揭示可用許多不同形式予以體現並且不應該被視為受限於本文所提的例示性具體實施例。反而，這些具體實施例係經提供為使得本揭示變得透徹並且完整，並且將完整傳達本發明的範疇給所屬領域的技術人員。本文所用術語的目的僅在於說明特殊具體實施例並且意圖不在於限制本揭示。例如，如本文中所用，除上下文另有所指外，單數形式「一」、「一種」、「一個」、以及「該」的用意在於同時包括複數形式。還有，「一」、「一種」、「一個」等用字未指示數量限制，而是指示存在至少一個所引用的項目。將進一步理解的是，用字「包含有」及/或「包含」、或「包括」及/或「包括有」若有用於本說明書，則是指定所述特徵、區域、完整物(integer)、步驟、操作、 元件、及/或組件的存在性，而非排除一或多個其它其特徵、區域、完整物、步驟、操作、元件、組件、及/或群組的存在或增加。
本說明書全篇對於「一具體實施例」、「一個具體實施例」、「具體實施例」、「示例性具體實施例」、或類似用語意指結合具體實施例所述的特殊特徵、結構、或特性係含括於本發明的至少一具體實施例中。因此，本說明書全篇的用詞表現「在一具體實施例中」、「在一個具體實施例」、「在具體實施例」以及類似用語可(但非必要)全部意指相同的具體實施例。
用字「上覆」或「在頂上」、「置於…上」或「上置於」、「在下面的」、「下方」或「下面」意指如第一結構(例如：第一層)等第一元件出現在如第二結構(例如：第二層)等第二元件上，其中如介面結構(例如：介面層)等中介元件(intervening element)可出現在第一元件與第二元件之間。
第1圖根據描述性具體實施例表示半導體結構100由上往下看的圖示。半導體結構100包含多個閘極102A、102B及102C(大體稱為102)。閘極102A、102B及102C可由金屬構成，並且可使用取代金屬閘極(RMG)製程形成。閘極係設置於源極/汲極接觸層103上。源極/汲極接觸層103有時可稱為「TS」層。源極/汲極接觸層103係設置於半導體基材110上方，半導體基材110上形成有複數個電晶體源極與汲極。源極與汲極的結構通常一 樣，並且在本揭示全文中，係將術語「源極/汲極」指稱為當作電晶體之源極或汲極任一者之主動半導體區。電晶體可為鰭型場效電晶體(finFET)，其源極/汲極為半導體晶鰭之一部分，係垂直於閘極102取向。複數個金屬化線件(104A-104H，大體稱為104)也垂直於閘極102取向，並且係設置於閘極102上面。
對於給定的電路設計，希望對不同電晶體之各個源極/汲極和閘極進行接觸，為的是要實現各種電路，如：邏輯電路、SRAM單元、以及諸如此類。所述接觸可連接至各個後段製程(BEOL)金屬化層及貫孔層，用以實現所需連接。在某些情況下，希望將鄰近的電晶體元件互相連接，例如：將一電晶體之源極/汲極連接至另一電晶體之源極/汲極或閘極。
本發明之具體實施例藉由採用不相似之覆蓋材料的選擇性蝕刻特性，並且也利用最下面金屬化層(通常稱為「M0」)與閘極102和源極/汲極接觸層103之交截，藉此將接觸形成程序簡化。在具體實施例中，使用的是兩個不同覆蓋層：第一覆蓋層用於源極/汲極接觸層，且第二覆蓋層用於閘極。各個閘極和源極/汲極敞開著，而阻隔遮罩則保護仍受到覆蓋之閘極和源極/汲極。相較於透過微影方法形成個別接觸之傳統製造方法，阻隔遮罩之微影要求得以大幅減少。這由於關鍵尺寸隨著每一世代半導體製造技術持續縮減而尤其如此。本發明之具體實施例提供二維自對準之源極/汲極和閘極接觸，簡化半導體製造程序，並 且也藉由降低如閘極與相鄰源極/汲極之間接觸短路之類的缺陷風險，將產品良率改良。
如第1圖所示，在金屬化線件104與閘極102和源極/汲極接觸層區域103A-C交截之點位，詳述複數個源極/汲極接觸(大致標示為108)以及複數個閘極接觸(大致標示為106)。區域103A係第一極性CMOS(亦即PMOS)之源極/汲極接觸層區域，並且區域103B係相反極性(本實施例中為NMOS)之源極/汲極接觸層區域。在具體實施例中，源極/汲極接觸層區域103C可為由如同區域103A與103B之源極/汲極接觸層所構成的NMOS與PMOS電晶體之「貫通(passthrough)」互連。此貫通互連可將複數個NMOS場效電晶體連接至複數個PMOS場效電晶體。透過後續圖示中所述的程序，僅在有必要時才製作接觸，從而能達到所需的連接性。許多不同的連接架構是可行的。例如，請參照金屬化線件104A，係將相鄰於閘極102A之源極/汲極接觸連接至相鄰於閘極102C之源極/汲極接觸。沿著金屬化線件104B，在閘極102B上形成有閘極接觸，而閘極102A和102C上則沒有閘極接觸形成。沿著金屬線104C有單一源極/汲極接觸。沿著金屬化線件104D有兩個互相連接之閘極接觸。閘極102A係連接至閘極102C，而未連接至S/D接觸「貫通」103C。沿著金屬化線件104E，閘極102B係連接至閘極102C，同樣未連接至S/D接觸「貫通」103C。沿著金屬化線件104F未形成接觸。所有源極/汲極接觸區和閘極都維持被覆蓋層覆蓋。沿著金屬化線件 104G，形成所謂的閘極-S/D聯結結構，將電晶體之閘極連接至其源極/汲極接觸之其中一者。沿著金屬化線件104H，於兩個鄰接的源極/汲極接觸之間形成連接，但未與中介閘極102B形成接觸。所屬領域技術人員將了解的是，這些只是實施例，並且實際上，金屬化線件可擴及比第1圖所示多更多的閘極。
第2圖針對描述性具體實施例表示半導體結構200起始點的剖面圖(如沿著第1圖線條A-A’檢視)。半導體結構200包含半導體基材210。在具體實施例中，半導體基材210可包含矽基材。半導體基材210可為主體矽基材，或可為上覆半導體絕緣體(SOI)基材。複數個閘極(220A及220B)係形成於半導體基材210上。在具體實施例中，閘極220A和220B由金屬構成，並且係藉由取代金屬閘極(RMG)程序形成。在具體實施例中，閘極220A和220B可由鎢構成。源極/汲極區212A、212B及212C係相鄰於閘極220A與220B而成。源極/汲極接觸區218A、218B及218C係分別在源極/汲極區212A、212B及212C上方形成。一覆蓋層224係設置於閘極220A和220B每一者的上方。另一覆蓋層222係設置於源極/汲極接觸區218A、218B及218C上方。覆蓋層222及覆蓋層224屬於不同材料，並且較佳是對蝕刻程序互相具有選擇性。在一些具體實施例中，覆蓋層222可由氧化物(如：氧化矽)構成，而覆蓋層224則由氮化物(如：氮化矽)構成。在其它具體實施例中，覆蓋層224可由氧化物(如：氧化矽)構成，而覆蓋層222則由 氮化物(如：氮化矽)構成。場式絕緣體(介電質)214生成金屬化線件凹穴215，金屬化線件隨後沉積於此。在具體實施例中，場式絕緣體214可由矽碳氧化物(SiOC)構成。場式絕緣體214較佳係使得能將覆蓋層222及覆蓋層224兩者蝕刻而未將場式絕緣體實質移除。在一些具體實施例中，場式絕緣體可相鄰於源極/汲極接觸區和閘極。視需要地，如第2圖所示，間隔物216可相鄰於閘極(220A、220B)而置，並且也可相鄰於源極/汲極接觸區(218A、218B及218C)而置。用於間隔物216之材料較佳係使得能將覆蓋層222及覆蓋層224兩者蝕刻而未將間隔物實質移除。在一些具體實施例中，間隔物216由矽氧碳氮化物(SiOCN)構成，或可為矽碳氧化物(SiOC)。
第3圖根據描述性具體實施例表示半導體結構200在沉積第一遮罩層226之後續處理步驟之後的剖面圖。在具體實施例中，第一遮罩層226可由光阻構成。在其它具體實施例中，可將硬遮罩用於遮罩層226。如第3圖所示，第一遮罩226之例示性沉積圖樣包含兩個區域(226A與226B)，這兩個區域之間有一距離D1，其將源極/汲極接觸區218B之位置曝露。在這個實施例中，希望敞開源極/汲極接觸區218B，距離為D2，但不要敞開相鄰的閘極220A或220B。用於遮罩層之微影要求係使得距離D1有相當寬的範圍，並且範圍能從恰好稍大於距離D2往上到D1之距離，如第1圖所示。在一些具體實施例中，D2的範圍可自約15奈米至約40奈米，並且D1的範圍可自 約D2加5奈米至約D2的3倍。因此，D1的容限範圍寬，這使得遮罩層226在執行微影時較直接。
第4圖根據描述性具體實施例表示半導體結構200在使源極/汲極接觸區曝露之後續處理步驟之後的剖面圖。源極/汲極接觸區218B係使用選擇性蝕刻程序予以曝露，其僅將源極/汲極接觸區上方的覆蓋層222移除，但未將設置於閘極(220A、220B)上方的覆蓋層224移除。在具體實施例中，可使用選擇性反應性離子蝕刻(RIE)程序，將源極/汲極接觸區218B上方的覆蓋層移除。在另一具體實施例中，取決於用於覆蓋層之材料，可使用如SiCoNi蝕刻之類的等向性「數位」蝕刻技術。在覆蓋層移除後，也將第一遮罩層(第3圖之226)移除。
第5圖根據描述性具體實施例表示半導體結構200在沉積第二遮罩層230之後續處理步驟之後的剖面圖。在這個實施例中，希望敞開閘極218C，距離為D3，但不要敞開相鄰的閘極220B。因此，場式絕緣體214與第二遮罩層230之間的距離D4能遠大於D3。在一些具體實施例中，D3的範圍可自約15奈米至約40奈米，並且D4的範圍可自約D3加5奈米至約D3的3倍。因此，D4的容限範圍寬，這使得遮罩層230在執行微影時較直接。
第6圖根據描述性具體實施例表示半導體結構200在使電晶體閘極曝露之後續處理步驟之後的剖面圖。在具體實施例中，可使用選擇性反應性離子蝕刻(RIE)程序，將閘極220B上方的覆蓋層移除。在另一具體實施 例中，取決於用於覆蓋層之材料，可使用如SiCoNi蝕刻之類的等向性蝕刻。在覆蓋層移除後，也將第二遮罩層(第5圖之230)移除。
第7圖根據描述性具體實施例表示半導體結構200在沉積金屬化線件232之後續處理步驟之後的剖面圖。金屬化線件232係藉由場式絕緣體214予以限制。具體實施例金屬化線件232可由鎢、銅或鋁構成。其它材料是可行的。可使用化學氣相沉積(CVD)、物理氣相沉積(PVD)、或電鍍程序將金屬化線件232沉積。由於金屬化線件232之沉積，閘極220B與源極/汲極接觸區218B電性接觸。這導致類似於沿著第1圖金屬化線件104G所示的「閘極-源極/汲極聯結」。係藉由將金屬化線件與已敞開之閘極和源極/汲極接觸區(已移除其各別覆蓋層)進行交截，形成用於閘極與源極/汲極接觸區之接觸。與閘極和源極/汲極之接觸屬於二維自對準，允許電路密度提升且產品良率改善。與使用貫孔抵達金屬化線件之傳統設計對照，裝置效能因連接路徑較短、電阻降低而提升，成為另外的效益。在這種情況下，金屬化線件是直接位於曝露(敞開)之閘極和曝露(敞開)之源極/汲極接觸區上。在具體實施例中，閘極和源極/汲極接觸區之子集維持以覆蓋層覆蓋。對於這些未曝露(未敞開)之元件(源極/汲極接觸區和閘極)，金屬化線件(層件)也與第一和第二覆蓋層直接實體接觸。
第8圖根據描述性替代具體實施例表示兩個源極/汲極接觸區之間形成連接之半導體結構300的剖面 圖。如前述，在圖式的各個圖中，類似元件可用相同數字指稱，在這種情況下，最後兩位數常可相同，最前數字為圖號。例如，第3圖的半導體基材310類似於第2圖的半導體基材210。在這個實施例中，金屬化線件322在源極/汲極區312A與源極/汲極區312C之間提供電連接性，在閘極320A與320B、以及源極/汲極區318B上方通過。類似於第1至7圖所示的程序，藉由選擇適當的第一和第二遮罩圖樣，理想的連接點有將覆蓋層移除而由金屬化線件332致能連接性。
第9圖根據描述性替代具體實施例表示兩個電晶體區之間形成連接之半導體結構400的剖面圖。在這個實施例中，金屬化線件432在閘極420A與閘極420B之間提供電連接性，在源極/汲極區418B上方通過。類似於第1至7圖所示的程序，藉由選擇適當的第一和第二遮罩圖樣，理想的連接點有將覆蓋層移除而由金屬化線件422致能連接性。
第10圖係指示用於本發明具體實施例之程序步驟的流程圖1000。在處理步驟1050中，於電晶體閘極上方沉積第一覆蓋層(例如：第2圖之224)。在處理步驟1052中，於源極/汲極接觸區上方沉積第二覆蓋層(例如：第2圖之222)。儘管流程圖1000示出在閘極上方沉積覆蓋層，接著在源極/汲極接觸區上方沉積不同之覆蓋層，本發明之具體實施例可將順序逆轉，並且先在源極/汲極接觸區上方沉積覆蓋材料，然後在閘極上方沉積材料不同之覆蓋 層。在處理步驟1053中，將介電層沉積並且將金屬溝槽敞開，使閘極和源極/汲極覆蓋層曝露。在處理步驟1054中，形成第一遮罩層(請參閱第3圖之226)。第一遮罩層覆蓋不應被敞開之閘極。在處理步驟1056中，選擇之閘極(未被第一遮罩層覆蓋)係藉由將那些閘極(例如：第6圖之220B)上面之覆蓋層移除而敞開。在處理步驟1058中，形成第二遮罩(請參閱第5圖之230)。第二遮罩層覆蓋不應被敞開之源極/汲極接觸區。在處理步驟1060中，選擇之源極/汲極接觸區(未被第二遮罩層覆蓋)係藉由將那些源極/汲極接觸區(例如：第4圖之218B)上面之覆蓋層移除而敞開。在處理步驟1062中，沉積金屬化線件，其在敞開之元件(閘極與源極/汲極)之間提供電連接性。儘管流程圖1000示出先將閘極敞開，接著將源極/汲極接觸區敞開，本發明之具體實施例可將順序逆轉，並且先將源極/汲極接觸區敞開，接著才將閘極敞開。
如現在能領會的是，本發明之具體實施例提供改良型半導體結構及製造方法，其提供二維自對準之電晶體接觸。這用以改良中段製程(MOL)密度，其常為尺寸調整能力的限制因子。
儘管已搭配例示性具體實施例特別表示並且說明本發明，仍將了解所屬領域的技術人員將想到變異與改進。例如，雖然描述性具體實施例在本文係說明為一連串動作或事件，將了解除非有特別說明，本發明不侷限於此等動作或事件所述排序。根據本發明，某些動作可以 不同順序出現及/或與本文所示及/或所述不同的其它動作或事件同時發生。另外，可無需將所有所述步驟都用於實現如本發明所述的方法。此外，如本發明所述的方法可聯合本文所示與所述架構之形成及/或處理以及聯合其它未描述的架構予以實現。因此，要瞭解所附申請專利範圍的用意在於涵蓋所有落於本發明真實精神內的此等改進及變更。
1000‧‧‧流程圖
1050、1052、1053、1054、1056、1058、1060、1062‧‧‧處理步驟

Claims (20)

  1. 一種形成半導體結構之方法，係包含：以第一覆蓋層覆蓋複數個電晶體閘極；以第二覆蓋層覆蓋複數個源極/汲極接觸區；在該半導體結構上方形成第一遮罩，其中，該第一遮罩使複數個閘極接觸位置曝露；將該第一覆蓋層從該複數個閘極接觸位置移除；在該半導體結構上方形成第二遮罩，其中，該第二遮罩使複數個源極/汲極接觸位置曝露；將該第二覆蓋層從該複數個源極/汲極接觸位置移除；以及在該等曝露之源極/汲極接觸位置以及曝露之閘極接觸位置上方沉積金屬化層。
  2. 如申請專利範圍第1項所述之方法，其中，以第一覆蓋層覆蓋複數個電晶體閘極包含沉積氮化矽。
  3. 如申請專利範圍第2項所述之方法，其中，以第二覆蓋層覆蓋複數個源極/汲極接觸區包含沉積氧化矽。
  4. 如申請專利範圍第1項所述之方法，其中，沉積金屬化層包含沉積鎢。
  5. 如申請專利範圍第1項所述之方法，其中，沉積金屬化層包含沉積銅。
  6. 如申請專利範圍第1項所述之方法，更包含形成閘極SD聯結結構，該閘極SD聯結結構將該複數個電晶體閘極之一者連接至相鄰源極/汲極接觸區。
  7. 如申請專利範圍第1項所述之方法，更包含將該複數個電晶體閘極之第一電晶體閘極連接至該複數個電晶體閘極之第二電晶體閘極。
  8. 如申請專利範圍第1項所述之方法，更包含將該複數個源極/汲極接觸區之第一源極/汲極接觸區連接至該複數個源極/汲極接觸區之第二源極/汲極接觸區。
  9. 一種形成半導體結構之方法，係包含：以第一覆蓋層覆蓋複數個電晶體閘極；以第二覆蓋層覆蓋複數個源極/汲極接觸區；在該半導體結構上方形成第一遮罩，其中，該第一遮罩使複數個閘極接觸位置曝露；將該第一覆蓋層從該複數個閘極接觸位置移除；在該半導體結構上方形成第二遮罩，其中，該第二遮罩使複數個源極/汲極接觸位置曝露；將該第二覆蓋層從該複數個源極/汲極接觸位置移除；以及在該曝露之源極/汲極接觸位置及曝露之閘極接觸位置上方沉積金屬化線件，其中，該第一覆蓋層包含氧化矽，以及該第二覆蓋層包含氮化矽。
  10. 如申請專利範圍第9項所述之方法，其中，沉積金屬化線件包含沉積鎢。
  11. 如申請專利範圍第9項所述之方法，更包含形成閘極SD聯結結構，該閘極SD聯結結構將該複數個電晶體閘極之一者連接至相鄰源極/汲極接觸區。
  12. 如申請專利範圍第9項所述之方法，更包含將該複數個電晶體閘極之第一電晶體閘極連接至該複數個電晶體閘極之第二電晶體閘極。
  13. 如申請專利範圍第9項所述之方法，更包含將該複數個源極/汲極接觸區之第一源極/汲極接觸區連接至該複數個源極/汲極接觸區之第二源極/汲極接觸區。
  14. 如申請專利範圍第9項所述之方法，更包含使用貫通互連，將含有NMOS電晶體之第一源極/汲極接觸層區域連接至含有PMOS電晶體之第二源極/汲極接觸層區域。
  15. 一種半導體結構，係包含：複數個電晶體閘極；複數個電晶體源極/汲極接觸區；設置於該複數個電晶體閘極之子集上的第一覆蓋層；設置於該複數個電晶體源極/汲極接觸區之子集上的第二覆蓋層；以及設置於該第一覆蓋層及第二覆蓋層上之金屬化層。
  16. 如申請專利範圍第15項所述之半導體結構，其中，該金屬化層係與該複數個電晶體閘極之至少一電晶體閘極電性接觸。
  17. 如申請專利範圍第15項所述之半導體結構，其中，該金屬化層係與該複數個電晶體源極/汲極接觸區之至少一源極/汲極接觸區電性接觸。
  18. 如申請專利範圍第15項所述之半導體結構，更包含限 制該金屬化層之介電區。
  19. 如申請專利範圍第18項所述之半導體結構，更包含與該複數個電晶體閘極之每一個電晶體閘極相鄰之複數個間隔物。
  20. 如申請專利範圍第19項所述之半導體結構，其中，該第一覆蓋層係由氮化矽構成，該第二覆蓋層係由氧化矽構成，該介電區係由矽碳氧化物構成，以及該複數個間隔物係由選自由矽碳氧化物及矽氧碳氮化物所組成群組之材料構成。
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US9660040B2 (en) 2017-05-23
US20150287636A1 (en) 2015-10-08
US10056373B2 (en) 2018-08-21
CN104979279B (zh) 2018-07-03
TW201539654A (zh) 2015-10-16
US9202751B2 (en) 2015-12-01
CN104979279A (zh) 2015-10-14
US20170221886A1 (en) 2017-08-03

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