CN104726935A - Ga2O3系晶体膜的成膜方法和晶体层叠结构体 - Google Patents

Ga2O3系晶体膜的成膜方法和晶体层叠结构体 Download PDF

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CN104726935A
CN104726935A CN201410810880.9A CN201410810880A CN104726935A CN 104726935 A CN104726935 A CN 104726935A CN 201410810880 A CN201410810880 A CN 201410810880A CN 104726935 A CN104726935 A CN 104726935A
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CN104726935B (zh
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佐佐木公平
东胁正高
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Tamura Corp
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Abstract

提供能在量产时以足够的生长速度形成晶体品质、表面的平坦性优异的Ga2O3系晶体膜的Ga2O3系晶体膜的成膜方法和包括通过该成膜方法形成的Ga2O3系晶体膜的晶体层叠结构体。作为一实施方式,提供在Ga2O3系基板(10)的面方位为(001)的主面(11)上以750℃以上的生长温度使Ga2O3系晶体膜(12)外延生长的Ga2O3系晶体膜(12)的成膜方法。

Description

Ga2O3系晶体膜的成膜方法和晶体层叠结构体
技术领域
本发明涉及Ga2O3系晶体膜的成膜方法和晶体层叠结构体。
背景技术
以往,已知在Ga2O3系基板上使Ga2O3系晶体膜外延生长的技术(例如,参照专利文献1)。
根据专利文献1,在主面的面方位为(001)的Ga2O3系基板上以生长温度700℃使Ga2O3系晶体膜生长的情况下,Ga2O3系晶体膜的生长速度大致为90nm/h。另外,在主面的面方位为(010)的Ga2O3系基板上以生长温度700℃使Ga2O3系晶体膜生长的情况下,Ga2O3系晶体膜的生长速度大致为130nm/h。
现有技术文献
专利文献
专利文献1:国际公开第2013/035464号
发明内容
发明要解决的问题
Ga2O3系晶体膜的生长速度在考虑Ga2O3系晶体膜的量产性的情况下是越高越好,最低也要求0.1μm/h程度的速度。另一方面,即使Ga2O3系晶体膜的生长速度高,若晶体品质、表面的平坦性不充分,则也不堪实用。
因此,本发明的目的之一在于,提供能在量产时以足够的生长速度形成晶体品质、表面的平坦性优异的Ga2O3系晶体膜的Ga2O3系晶体膜的成膜方法和包括通过该成膜方法形成的Ga2O3系晶体膜的晶体层叠结构体。
用于解决问题的方案
为了达到上述目的,本发明的一方面提供下述[1]~[3]的Ga2O3系晶体膜的成膜方法。
[1]一种Ga2O3系晶体膜的成膜方法,在Ga2O3系基板的面方位为(001)的主面上以750℃以上的生长温度使Ga2O3系晶体膜外延生长。
[2]根据上述[1]所述的Ga2O3系晶体膜的成膜方法,其中,上述Ga2O3系晶体膜的主面具有RMS值为1nm以下的平坦性。
[3]根据上述[1]或[2]所述的Ga2O3系晶体膜的成膜方法,其中,上述Ga2O3系晶体膜为Ga2O3晶体膜。
另外,为了达到上述目的,本发明的另一方面提供下述[4]、[5]的晶体层叠结构体。
[4]一种晶体层叠结构体,其包括:Ga2O3系基板,其主面的面方位为(001);以及Ga2O3系晶体膜,其在上述Ga2O3系基板的上述主面上通过外延晶体生长而形成,其主面具有RMS值为1nm以下的平坦性。
[5]根据上述[4]所述的晶体层叠结构体,其中,上述Ga2O3系晶体膜为Ga2O3晶体膜。
发明效果
根据本发明,能够提供能在量产时以足够的生长速度形成晶体品质、表面的平坦性优异的Ga2O3系晶体膜的Ga2O3系晶体膜的成膜方法和包括通过该成膜方法形成的Ga2O3系晶体膜的晶体层叠结构体。
附图说明
图1是第1实施方式所涉及的晶体层叠结构体的垂直剖面图。
图2(a)、图2(b)是示出分别在主面的面方位为(010)、(-201)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与主面的平坦性的关系的坐标图。
图3(a)、图3(b)是示出分别在主面的面方位为(101)、(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与主面的平坦性的关系的坐标图。
图4是示出在面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与生长速度的关系的坐标图。
图5是示出在主面的面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的通过X射线摇摆曲线测定而得到的X射线衍射光谱的坐标图。
图6是示出在主面的面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的通过2θ-ω扫描而得到的X射线衍射光谱的坐标图。
图7是第2实施方式所涉及的高电子迁移率晶体管的垂直剖面图。
图8是第3实施方式所涉及的MESFET的垂直剖面图。
图9是第4实施方式所涉及的肖特基势垒二极管的垂直剖面图。
图10是第5实施方式所涉及的MOSFET的垂直剖面图。
附图标记说明
1…晶体层叠结构体,10…Ga2O3系基板,11…主面,12…Ga2O3系晶体膜
具体实施方式
〔第1实施方式〕
(晶体层叠结构体的构成)
图1是第1实施方式所涉及的晶体层叠结构体的垂直剖面图。晶体层叠结构体1具有Ga2O3系基板10和在Ga2O3系基板10上通过外延晶体生长而形成的Ga2O3系晶体膜12。
Ga2O3系基板10是包含Ga2O3系单晶体的基板。在此,所谓Ga2O3系单晶体,是指Ga2O3单晶体或者添加了Al、In等元素的Ga2O3单晶体。例如,也可以是作为添加了Al和In的Ga2O3单晶体的(GaxAlyIn(1-x-y))2O3(0<x≤1,0≤y<1,0<x+y≤1)单晶体。在添加了Al的情况下,带隙会变宽,在添加了In的情况下,带隙会变窄。此外,上述的Ga2O3单晶体例如具有β型的晶体结构。另外,Ga2O3系基板10也可以含有Si等导电型杂质。
Ga2O3系基板10的主面11的面方位为(001)。
Ga2O3系基板10例如是将通过FZ(Floating Zone:浮区)法、EFG(Edge Defined Film Fed Growth:限边馈膜生长)法等熔体生长法生成的Ga2O3系单晶体的块状晶体切成片并对表面进行研磨从而形成的。
Ga2O3系晶体膜12与Ga2O3系基板10同样地包含Ga2O3系单晶体。另外,Ga2O3系晶体膜12是在Ga2O3系基板10的主面11上通过外延晶体生长而形成的,因此,Ga2O3系晶体膜12的主面13的面方位与Ga2O3系基板10的主面11相同,为(001)。另外,Ga2O3系晶体膜12也可以含有Si等导电型杂质。
Ga2O3系晶体膜12例如是通过MBE(Molecular Beam Epitaxy:分子束外延)法等物理气相生长法、CVD(Chemical VaporDeposition:化学气相沉积)法等化学气相生长法形成的。
Ga2O3系晶体膜12是以750℃以上的生长温度通过外延生长形成的。通过使生长温度为750℃以上,Ga2O3系晶体膜12的主面13的平坦性会变高。具体地说,主面13的RMS值为1nm以下。
在此,RMS值是作为平坦性的指标的数值,通过以下方式得到:利用原子力显微镜测定表示Ga2O3晶体膜的主面的铅垂方向的高度和水平方向的位置的关系的曲线,求出对从其平均线至曲线为止的偏差的平方进行平均而得到的值的平方根。
若RMS值较大,则例如在使用晶体层叠结构体1制造肖特基二极管、MESFET(Metal-Semiconductor Field Effect Transistor:金属-半导体场效应晶体管)的情况下,有可能在形成于Ga2O3系晶体膜12上的肖特基电极中发生电场集中,引起元件耐压的下降。这是由电场集中到由Ga2O3系晶体膜12的主面13的凹凸形成的肖特基电极的底面的凹凸的凸部所致。作为用于抑制该电场集中的肖特基电极的底面的表面粗糙度的条件,已知RMS值为1nm以下。即,若Ga2O3系晶体膜12的主面13的RMS值为1nm以下,则能够抑制肖特基电极中的电场集中。
另外,通过使生长温度为750℃以上,能得到晶体品质高的Ga2O3系晶体膜12。此外,若生长温度超过900℃,则所供应的Ga的再蒸发会急激增加,与生长温度为600℃时相比,生长速度下降至1/10以下。这样,从原料使用效率这方面出发,优选生长温度较低。因此,优选Ga2O3系晶体膜12的生长温度为900℃以下。
Ga2O3系晶体膜12的晶体品质和主面的平坦性优异,因此,在Ga2O3系晶体膜12上能够形成高品质的金属―半导体界面和绝缘膜―半导体界面。因此,能够将晶体层叠结构体1用于高品质的半导体装置的制造。
(Ga2O3系晶体膜的评价)
以下,示出关于Ga2O3系晶体膜的主面的平坦性、生长速度、晶体品质的评价结果。此外,在本评价中,使用Ga2O3基板作为Ga2O3系基板,通过MBE法形成厚度大致为100~300nm的Ga2O3晶体膜作为Ga2O3系晶体膜。另外,使用臭氧作为Ga2O3晶体膜的氧源。
图2(a)、图2(b)是示出分别在主面的面方位为(010)、(-201)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与主面的平坦性的关系的坐标图。
图3(a)、图3(b)是示出分别在主面的面方位为(101)、(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与主面的平坦性的关系的坐标图。
图2(a)、图2(b)和图3(a)、图3(b)的横轴表示Ga2O3晶体膜的生长温度(℃),纵轴表示Ga2O3晶体膜的主面的RMS值(nm)。此外,RMS值是从1μm见方的区域中的原子力显微镜像算出的。
图2(b)和图3(a)示出:在Ga2O3基板的主面的面方位为(-201)或者(101)的情况下,无论是哪一生长温度均无法得到平坦性优异的(例如,主面的RMS值为1nm以下)的Ga2O3晶体膜。在Ga2O3晶体膜的平坦性低的情况下,也可以考虑通过研磨加工提高平坦性的方法,但随着工序的增加,制造成本会增加,因此不优选。
另外,图2(a)示出:在Ga2O3基板的主面的面方位为(010)的情况下,在生长温度大致为550~650℃时,Ga2O3晶体膜的主面的RMS值为1nm以下。然而,在生长温度为550~650℃程度时,无法得到晶体品质高的Ga2O3晶体膜。具体地说,例如,在以生长温度600℃形成的情况下,Ga2O3晶体膜的蚀坑密度为106cm-2程度,而在以生长温度700℃形成的情况下减少至104cm-2程度(即,缺陷减少至1/100)。此外,通过使Ga2O3基板的蚀坑密度为104cm-2程度,生长温度为700℃以上,能得到与Ga2O3基板相同程度的品质的Ga2O3晶体膜。
并且,根据图2(a),在700℃以上的区域,无法得到主面的RMS值为1nm以下的Ga2O3晶体膜。这一点表示:在Ga2O3基板的主面的面方位为(010)的情况下,得到晶体品质和主面的平坦性均优异的Ga2O3晶体膜是困难的。
另外,图3(b)示出:在Ga2O3基板的主面的面方位为(001)的情况下,在生长温度为750℃以上时,Ga2O3晶体膜的主面的RMS值为1nm以下。
此外,在取代Ga2O3基板而使用其它Ga2O3系基板的情况下和在取代Ga2O3晶体膜而形成其它Ga2O3系晶体膜的情况下,也均能得到与上述的评价结果同样的评价结果。即,可以说在Ga2O3系基板的主面的面方位为(001)的情况下,在Ga2O3系晶体膜的生长温度为750℃以上时,主面的RMS值为1nm以下。
图4是示出在主面的面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长时的Ga2O3晶体膜的生长温度与生长速度的关系的坐标图。
图4的横轴表示Ga2O3晶体膜的生长温度(℃),纵轴表示Ga2O3晶体膜的生长速度(μm/h)。
根据图4可知,虽然Ga2O3系晶体膜的主面的RMS值为1nm以下的750℃以上的生长温度时的生长速度低于600~700℃的相对较低的生长温度时的生长速度,但能得到0.4μm/h程度的值,Ga2O3晶体膜的量产性没有问题。
此外,在取代Ga2O3基板而使用其它Ga2O3系基板的情况下和在取代Ga2O3晶体膜而形成其它Ga2O3系晶体膜的情况下,也均能得到与上述的评价结果同样的评价结果。即,在Ga2O3系基板的主面的面方位为(001)的情况下,在Ga2O3系晶体膜的生长温度为750℃以上时,能得到0.4μm/h程度的生长速度。
图5是示出在主面的面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的通过X射线摇摆曲线测定而得到的X射线衍射光谱的坐标图。
图5的横轴表示X射线的入射角ω(degree:度),纵轴表示X射线的衍射强度(任意单位)。
图5示出Ga2O3基板(无Ga2O3晶体膜)的光谱和分别以600℃、650℃、700℃、725℃、750℃及775℃使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的光谱。在此,图5的各光谱所包含的衍射峰值为(002)面的衍射峰值。
图5示出:任一晶体层叠结构体的衍射峰值均具有与Ga2O3基板的衍射峰值大致相同的半值宽度。这一点表示:无论以600~775℃中的哪一生长温度使Ga2O3晶体膜生长,均能得到晶轴方向的偏差小的Ga2O3晶体膜。
此外,在取代Ga2O3基板而使用其它Ga2O3系基板的情况下和在取代Ga2O3晶体膜而形成其它Ga2O3系晶体膜的情况下,也均能得到与上述的评价结果同样的评价结果。即,在Ga2O3系基板的主面的面方位为(001)的情况下,无论以600~775℃中的哪一生长温度使Ga2O3系晶体膜生长,均能够得到晶轴方向的偏差小的Ga2O3系晶体膜。
图6是示出在主面的面方位为(001)的Ga2O3基板的主面上使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的通过2θ-ω扫描而得到的X射线衍射光谱的坐标图。
图6的横轴表示X射线的入射方位与反射方位所成的角2θ(degree),纵轴表示X射线的衍射强度(任意单位)。
图6示出Ga2O3基板(无Ga2O3晶体膜)的光谱和分别以600℃、650℃、700℃、725℃、750℃及775℃使Ga2O3晶体膜外延生长而形成的晶体层叠结构体的光谱。
图6示出:以600~725℃的生长温度使Ga2O3晶体膜生长而形成的晶体层叠结构体的光谱中可见的异相的存在所导致的(-401)面的衍射峰值在以750℃以上的生长温度使Ga2O3晶体膜生长而形成的晶体层叠结构体的光谱中消失了。这一点表示:通过以750℃以上的生长温度使Ga2O3晶体膜生长,能得到单相的Ga2O3晶体膜。此外,2θ=26°附近的较宽的峰值是由来自X射线衍射装置的基板支架的衍射所致。
另外,以750℃的生长温度形成的Ga2O3晶体膜的蚀坑密度为104cm-2程度,与作为104cm-2程度的Ga2O3基板的蚀坑密度大致相等。这一点表示:Ga2O3晶体膜具有与Ga2O3基板相同程度的高晶体品质。
此外,在取代Ga2O3基板而使用其它Ga2O3系基板的情况下和在取代Ga2O3晶体膜而形成其它Ga2O3系晶体膜的情况下,也均能得到与上述的评价结果同样的评价结果。即,在Ga2O3系基板的主面的面方位为(001)的情况下,通过以750℃以上的生长温度使Ga2O3系晶体膜生长,能得到单相的Ga2O3系晶体膜。
并且,综合从图5的X射线衍射光谱得到的评价结果和从图6的X射线衍射光谱得到的评价结果可知,通过以750℃以上的生长温度使Ga2O3系晶体膜生长,能得到晶体品质优异的Ga2O3系晶体膜。
〔第2实施方式〕
在第2实施方式中,对作为包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12的半导体装置之一的高电子迁移率晶体管(High Electron Mobility Transistor:HEMT)进行说明。
图7是第2实施方式所涉及的高电子迁移率晶体管的垂直剖面图。该高电子迁移率晶体管2包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12。而且,高电子迁移率晶体管2包括Ga2O3系晶体膜12的主面13上的电子供应层21、电子供应层21上的栅极电极23、源极电极24和漏极电极25。栅极电极23配置在源极电极24与漏极电极25之间。
栅极电极23与电子供应层21的主面22接触而形成肖特基接触。另外,源极电极24和漏极电极25与电子供应层21的主面22接触而形成欧姆接触。
在本实施方式中,Ga2O3系基板10含有Mg等II族的元素,具有高电阻。另外,Ga2O3系晶体膜12为i型,作为电子渡越层发挥功能。
电子供应层21例如包含添加了Si、Sn等供体的β-(AlGa)2O3单晶体,在Ga2O3系晶体膜12上通过外延生长而形成。
Ga2O3系晶体膜12和电子供应层21在带隙的大小上是不同的,因此,在其界面上会发生能带的不连续,从电子供应层21的供体产生的电子聚集到Ga2O3系晶体膜12侧而分布于界面附近的区域,形成被称为二维电子气的电子层。
这样,在电子供应层21中,会产生:因与栅极电极23之间的肖特基接触而产生的第1空乏层;以及因二维电子气的形成而导致的第2空乏层。电子供应层21具有第1空乏层和第2空乏层相接触这样的厚度。
并且,对栅极电极23施加电压,由此,使第1空乏层和第2空乏层的厚度变化来调节二维电子气的浓度,控制漏极电流。
Ga2O3系晶体膜12的厚度没有特别限定,但优选为1nm以上。另外,电子供应层21的厚度与掺杂浓度相应地设定为0.001~1μm。
在高电子迁移率晶体管2中,Ga2O3系晶体膜12的主面13的平坦性高,因此,形成在Ga2O3系晶体膜12上的电子供应层21的主面22的平坦性也高,能抑制与电子供应层21形成肖特基接触的栅极电极23中的电场集中。因此,能抑制高电子迁移率晶体管2的耐压性能的下降。
〔第3实施方式〕
在第3实施方式中,对作为包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12的半导体装置之一的MESFET(Metal-Semiconductor Field Effect Transistor)进行说明。
图8是第3实施方式所涉及的MESFET的垂直剖面图。该MESFET3包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12。而且,MESFET3包括Ga2O3系晶体膜12上的栅极电极31、源极电极32和漏极电极33。栅极电极31配置在源极电极32与漏极电极33之间。
栅极电极31与Ga2O3系晶体膜12的主面13接触而形成肖特基接触。另外,源极电极32和漏极电极33与Ga2O3系晶体膜12的主面13接触而形成欧姆接触。
在本实施方式中,Ga2O3系基板10含有Mg等II族的元素,具有高电阻。
在本实施方式中,Ga2O3系晶体膜12为n型,与源极电极32及漏极电极33的接触部附近的供体浓度高于其它部分的供体浓度。
通过控制施加到栅极电极31的偏置电压,能够使Ga2O3系晶体膜12内的栅极电极31下的空乏层的厚度变化,控制漏极电流。
在MESFET3中,Ga2O3系晶体膜12的主面13的平坦性高,因此,能抑制与Ga2O3系晶体膜12形成肖特基接触的栅极电极31中的电场集中。因此,能够抑制MESFET3的耐压性能的下降。
〔第4实施方式〕
在第4实施方式中,对作为包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12的半导体装置之一的肖特基势垒二极管进行说明。
图9是第4实施方式所涉及的肖特基势垒二极管的垂直剖面图。该肖特基势垒二极管4包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12。而且,肖特基势垒二极管4包括Ga2O3系晶体膜12的主面13上的肖特基电极41、Ga2O3系基板10的与主面11相反一侧的主面14上的欧姆电极42。
肖特基电极41与Ga2O3系晶体膜12的主面13接触而形成肖特基接触。另外,欧姆电极42与Ga2O3系基板10的主面14接触而形成欧姆接触。
在本实施方式中,Ga2O3系基板10和Ga2O3系晶体膜12为n型,Ga2O3系晶体膜12的供体浓度低于Ga2O3系基板10的供体浓度。
当对肖特基势垒二极管4施加正向电压(肖特基电极41侧为正电位)时,从Ga2O3系基板10向Ga2O3系晶体膜12移动的电子会增加。由此,正向电流从肖特基电极41流向欧姆电极42。
另一方面,当对肖特基势垒二极管4施加反向电压(肖特基电极41侧为负电位)时,流过肖特基势垒二极管4的电流几乎为零。
在肖特基势垒二极管4中,Ga2O3系晶体膜12的主面13的平坦性高,因此,能抑制与Ga2O3系晶体膜12形成肖特基接触的肖特基电极41中的电场集中。因此,能抑制肖特基势垒二极管4的耐压性能的下降。
〔第5实施方式〕
在第5实施方式中,对作为包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12的半导体装置之一的MOSFET(Metal-oxide-Semiconductor Field Effect Transistor)进行说明。
图10是第5实施方式所涉及的MOSFET的垂直剖面图。该MOSFET5包括第1实施方式所涉及的Ga2O3系基板10和Ga2O3系晶体膜12。而且,MOSFET5包括Ga2O3系晶体膜12上的氧化物绝缘膜52、栅极电极51、源极电极53和漏极电极54。氧化物绝缘膜52、栅极电极51配置在源极电极53与漏极电极54之间。
栅极电极51隔着氧化物绝缘膜52形成在Ga2O3系晶体膜12的主面13上。另外,源极电极53和漏极电极54与Ga2O3系晶体膜12的主面13接触而形成欧姆接触。
在本实施方式中,Ga2O3系基板10含有Mg等II族的元素,具有高电阻。
通过控制施加到栅极电极51的偏置电压,能够控制流过Ga2O3系晶体膜12内的漏极电流。
在MOSFET5中,Ga2O3系晶体膜12的主面13的平坦性高,因此,能够使Ga2O3系晶体膜12与氧化物绝缘膜52的界面陡峭,抑制电场集中、沟道迁移率的下降等。
(实施方式的效果)
根据上述实施方式,能在量产时以足够的生长速度形成晶体品质、主面的平坦性优异的Ga2O3系晶体膜。另外,Ga2O3系晶体膜的晶体品质和主面的平坦性优异,因此,能够在Ga2O3系晶体膜上使品质良好的晶体膜生长。因此,能够将包括本实施方式所涉及的Ga2O3系晶体膜的晶体层叠结构体用于高品质的半导体装置的制造。
以上,说明了本发明的实施方式,但本发明不限于上述实施方式,能在不脱离发明的宗旨的范围内进行种种变形实施。
另外,上面所述的实施方式并非限定权利要求所涉及的发明。另外,应当注意,实施方式中所说明的特征的组合并不全都是用于解决发明的问题的方案所必需的。

Claims (5)

1.一种Ga2O3系晶体膜的成膜方法,其特征在于,
在Ga2O3系基板的面方位为(001)的主面上以750℃以上的生长温度使Ga2O3系晶体膜外延生长。
2.根据权利要求1所述的Ga2O3系晶体膜的成膜方法,其中,
上述Ga2O3系晶体膜的主面具有RMS值为1nm以下的平坦性。
3.根据权利要求1或2所述的Ga2O3系晶体膜的成膜方法,其中,
上述Ga2O3系晶体膜为Ga2O3晶体膜。
4.一种晶体层叠结构体,其特征在于,包括:
Ga2O3系基板,其主面的面方位为(001);以及
Ga2O3系晶体膜,其在上述Ga2O3系基板的上述主面上通过外延晶体生长而形成,其主面具有RMS值为1nm以下的平坦性。
5.根据权利要求4所述的晶体层叠结构体,其中,
上述Ga2O3系晶体膜为Ga2O3晶体膜。
CN201410810880.9A 2013-12-24 2014-12-23 Ga2O3系晶体膜的成膜方法和晶体层叠结构体 Active CN104726935B (zh)

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