CN104659003A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN104659003A
CN104659003A CN201410377149.1A CN201410377149A CN104659003A CN 104659003 A CN104659003 A CN 104659003A CN 201410377149 A CN201410377149 A CN 201410377149A CN 104659003 A CN104659003 A CN 104659003A
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China
Prior art keywords
pad
substrate
certain embodiments
semiconductor device
solder mask
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CN201410377149.1A
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CN104659003B (zh
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陈洁
陈英儒
陈宪伟
于宗源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体器件，该半导体器件包括具有表面的衬底、设置在衬底的表面上的多个焊盘，多个焊盘包括非焊料掩模限定(NSMD)焊盘和焊料掩模限定(SMD)焊盘，并且NSMD焊盘布置在预定位置处。此外，一种制造半导体器件的方法包括：提供衬底，在衬底的表面上设置多个焊盘，在衬底的表面和多个焊盘的上方设置焊料掩模，在焊料掩模中形成第一凹槽以围绕多个焊盘中的一个，以及在焊料掩模中并且在多个焊盘中的一个之上形成第二凹槽。本发明还提供半导体器件的制造方法。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件和半导体器件的制造方法。
背景技术
包括许多半导体器件的电子设备在我们的日常生活中是不可缺少的。随着电子技术的进步，电子设备在尺寸上变得更小并且必须执行和实施越来越复杂而多样的功能。因此，电子设备变得更加小型化(包括更多的电子部件)并且在结构上变得更加复杂(在如此一个小区域内包括高密度的输入/输出(I/O)端子)。
晶圆级封装(WLP)技术已经变得普及。该技术提供了具有高功能和性能而半导体器件尺寸较小的半导体器件的晶圆级制造。在制造半导体器件期间，采用表面安装技术(SMT)以使半导体器件小型化。该半导体器件包括安装在另一衬底上的衬底，从而使得衬底的焊盘通过焊球与另一衬底的焊盘接合并且电连接。
通过多种方法在衬底的顶面上形成衬底的焊盘。然而，通过不同方法形成的焊盘将提供关于跌落试验、热循环、弯曲度等的不同的可靠性。例如，一些焊盘将能够承受高应力水平并因此将不容易发生破裂，而一些焊盘将能够承受高温并因此使与衬底分层的概率最小化。
同样地，对改进衬底上焊盘的配置以及焊盘的制造操作以优化焊盘的可靠性并解决上述缺陷有持续的需求。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：衬底，包括表面；多个焊盘，设置在所述衬底的表面上；其中，所述多个焊盘包括非焊料掩模限定(NSMD)焊盘和焊料掩模限定(SMD)焊盘，并且所述NSMD焊盘布置在预定位置处。
在上述半导体器件中，其中，所述预定位置位于所述衬底的拐角处。
在上述半导体器件中，其中，所述SMD焊盘设置为远离所述衬底的拐角。
在上述半导体器件中，其中，所述NSMD焊盘和所述SMD焊盘布置为不规则的阵列，所述不规则的阵列包括不含有所述NSMD焊盘和所述SMD焊盘的空白区域，并且所述NSMD焊盘布置为邻近所述空白区域。
在上述半导体器件中，其中，所述SMD焊盘被焊料掩模部分覆盖。
在上述半导体器件中，其中，所述NSMD焊盘与焊料掩模间隔开。
根据本发明的另一方面，还提供了一种半导体器件，包括：衬底，包括表面；多个焊盘，设置在所述衬底的表面上；焊料掩模，设置在所述衬底的表面上方；其中，所述焊料掩模包括多个第一凹进部分和多个第二凹进部分，所述多个焊盘中的至少一个相应地位于所述多个第一凹进部分内，并且所述多个焊盘中的至少一个相应地设置在所述多个第二凹进部分的下面。
在上述半导体器件中，其中，所述多个第一凹进部分中的每个均大于所述多个焊盘中的相应的一个。
在上述半导体器件中，其中，所述多个第二凹槽部分中的每个均小于所述多个焊盘中的相应的一个。
在上述半导体器件中，其中，所述多个第一凹进部分设置在所述衬底的拐角处。
在上述半导体器件中，其中，所述多个第二凹进部分设置在所述衬底的中心部分处。
根据本发明的又一方面，还提供了一种制造半导体器件的方法，包括：提供衬底；在所述衬底的表面上设置多个焊盘；在所述衬底的表面和所述多个焊盘的上方设置焊料掩模；在所述焊料掩模中形成第一凹槽以围绕所述多个焊盘中的一个；以及在所述焊料掩模中并且在所述多个焊盘中的一个之上形成第二凹槽。
在上述方法中，其中，当与所述第一凹槽相对应的所述多个焊盘中的一个设置在所述衬底的拐角处时，形成所述第一凹槽。
在上述方法中，还包括：确定在所述焊料掩模上形成的所述第一凹槽的位置和所述第二凹槽的位置。
在上述方法中，还包括：限定具有预定中点和预定直径的圆圈以确定所述焊料掩模上的所述第一凹槽的位置和所述第二凹槽的位置。
在上述方法中，其中，所述第一凹槽定位为围绕设置在具有预定中点和预定直径的圆圈外部的所述多个焊盘中的一个。
在上述方法中，其中，所述第二凹槽定位为位于设置在具有预定中点和预定直径的圆圈内部的所述多个焊盘中的一个之上。
在上述方法中，还包括：将邻近所述衬底的空白区域的所述多个焊盘中的至少一个定义为隔离焊盘。
在上述方法中，其中，形成所述第一凹槽以围绕定义为隔离焊盘的所述焊盘。
在上述方法中，其中，定义为隔离焊盘的所述焊盘与少于四个焊盘邻近。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或缩小。
图1A是根据本发明的一些实施例的具有非焊料掩模限定(NSMD)焊盘的半导体器件的示意图。
图1B是根据本发明的一些实施例的具有NSMD焊盘的半导体器件的顶视图。
图2A是根据本发明的一些实施例的具有焊料掩模限定(SMD)焊盘的半导体器件的示意图。
图2B是根据本发明的一些实施例的具有SMD焊盘的半导体器件的顶视图。
图3A是根据本发明的一些实施例的具有NSMD焊盘和SMD焊盘的半导体器件的示意图。
图3B是根据本发明的一些实施例的具有NSMD焊盘和SMD焊盘的半导体器件的顶视图。
图4A是根据本发明的一些实施例的在拐角处具有NSMD焊盘的半导体器件的顶视图。
图4B是根据本发明的一些实施例的在邻近拐角处具有NSMD焊盘的半导体器件的顶视图。
图4C是根据本发明的一些实施例的在邻近空白区处具有NSMD焊盘的半导体器件的顶视图。
图5是根据本发明的一些实施例制造半导体器件的方法的流程图。
图5A是根据本发明的一些实施例的具有第一衬底的半导体器件的示意图。
图5B是根据本发明的一些实施例的具有若干个焊盘的半导体器件的示意图。
图5C是根据本发明的一些实施例的具有焊料掩模的半导体器件的示意图。
图5D是根据本发明的一些实施例的在拐角处具有NSMD焊盘的半导体器件的顶视图。
图5E是根据本发明的一些实施例的在邻近拐角处具有NSMD焊盘的半导体器件的顶视图。
图5F是根据本发明的一些实施例的在邻近拐角处具有NSMD焊盘的半导体器件的顶视图。
图5G是根据本发明的一些实施例的在圆圈外侧具有NSMD焊盘的半导体器件的顶视图。
图5H是根据本发明的一些实施例的在圆圈外侧具有NSMD焊盘的半导体器件的顶视图。
图5I是根据本发明的一些实施例的具有NSMD焊盘和SMD焊盘的半导体器件的示意图。
图5J是根据本发明的一些实施例的具有第二衬底的半导体器件的示意图。
图5K是根据本发明的一些实施例的具有第一衬底和第二衬底的半导体器件的示意图。
具体实施方式
在表面安装技术(SMT)中，半导体器件包括至少两个衬底。通过诸如焊料接合点或焊料凸块的导电凸块将衬底的焊盘与另一衬底的焊盘附接，从而将一个衬底堆叠在另一个衬底上。通过在衬底上溅射或电镀导电材料来形成衬底的焊盘，从而使得焊盘在衬底的电路和位于该衬底外部的另一衬底的电路之间传导电。然后由焊接材料覆盖衬底的焊盘以选择性地暴露焊盘的顶面。可以通过多种方法暴露焊盘，其中这些方法在焊盘的顶面上限定用于接收凸块的区域。然后将焊盘的暴露表面与凸块附接。
然而，衬底上的焊盘的以上配置具有一些问题，诸如焊盘和衬底之间的粘附性降低、机械试验(诸如板弯曲或跌落试验)中的性能差、焊盘外周的应力集中、板层面温度循环的可靠性差等。由于通过不同方法形成和暴露的焊盘将具有不同的问题，最终衬底整体将可靠性低和功能性能差。
下面详细地讨论了本发明的实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中体现的适用的发明构思。应该理解，以下公开内容提供了许多用于实现各个实施例的不同特征的不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。
下面使用特定语言公开了图中示出的实施例或实例。然而，将理解，实施例和实例不旨在限制本发明。相关领域普通技术人员在正常情况下将想到公开的实施例中的任何改变和更改以及该文件中公开的原理的进一步应用。
而且，应该理解，可仅简要地描述若干工艺步骤和/或器件的部件。此外，可以添加额外的工艺步骤和/或部件，并且可以去除或改变以下工艺步骤和/或部件的一些，但是仍能实现权利要求。因此，以下描述应该理解为仅是代表性实例，而不旨在暗示需要一个以上的步骤或部件。
此外，本发明在各个实例中可以重复参考标号和/或字母。该重复是为了简单和清楚的目的，而且其本身不指示讨论的各个实施例和/或结构之间的关系。
在本发明中，公开了具有改进的结构的半导体器件。该半导体器件包括衬底和衬底上的若干焊盘，该若干焊盘是焊料掩模限定(SMD)焊盘和非焊料掩模限定(NSMD)焊盘的组合，从而使得弥补了SMD焊盘和NSMD焊盘的劣势，并因此作为整体的衬底拥有来自SMD焊盘和NSMD焊盘的优势，诸如相对于板层面温度循环的高可靠性、跌落试验中的良好性能、应力集中点数量的减少等。
图1A是半导体器件100的一个实施例。半导体器件100包括衬底101。在一些实施例中，衬底101是包括硅衬底的电路板，硅衬底用于承载硅衬底内的电路并且支撑连接至电路的若干半导体部件。硅衬底包括若干导电层和若干介电层。导电层包括用于电连接硅衬底上的若干半导体部件的一些导电迹线。介电层配置为用于导电迹线之间的绝缘。在一些实施例中，电路板是包括一些集成电路(IC)的印刷电路板(PCB)以电连接在其上的半导体部件。在一些实施例中，衬底101呈条状。
在一些实施例中，半导体器件100包括设置在衬底101的表面101a上的焊盘102。焊盘102沿着表面101a水平地延伸。在一些实施例中，焊盘102是用于接收包括铜、锡或铅等的导电凸块的凸块下金属(UBM)焊盘。UBM焊盘是暴露以用于接收凸块以及电连接焊盘102和衬底101内部的电路的可焊接表面。在诸如回流的热处理之后，焊盘102与凸块接合。
在一些实施例中，通过诸如电镀、溅射等的多种方法将焊盘102设置在表面101a上。在一些实施例中，焊盘102包括诸如金、银、铜、镍、钨、铝和/或它们的合金的导电材料。
在一些实施例中，半导体器件100包括设置在衬底101的表面101a上方的焊料掩模103。在一些实施例中，焊料掩模103与焊盘102间隔开。焊料掩模103围绕焊盘102。在焊料掩模103与焊盘102之间存在间隙104。焊料掩模103与焊盘102不接触并且不覆盖焊盘。在一些实施例中，焊料掩模103的顶面103a位于焊盘102的顶面102a之上的层级(level)处。
在一些实施例中，焊料掩模103包括诸如液体环氧树脂或聚环氧化物等的聚合物材料。在一些实施例中，通过丝网漏印法、喷雾等将焊料掩模103设置在衬底101的表面101a上。
在一些实施例中，焊料掩模103包括第一凹进部分103b。第一凹进部分103b围绕焊盘102，以使得焊盘102设置在焊料掩模103的第一凹进部分103b内。在一些实施例中，第一凹进部分103b从焊料掩模103的顶面103a延伸至衬底101的顶面101a。
在一些实施例中，第一凹进部分103b的侧壁设置为远离焊盘102。在一些实施例中，第一凹进部分103b配置为暴露焊盘102的顶面102a和外周部分102b以接收凸块。
在一些实施例中，焊盘102是非焊料掩模限定(NSMD)焊盘。NSMD焊盘102设置在第一凹进部分103b内并且与焊料掩模103间隔开。NSMD焊盘102与焊料掩模103隔离。焊盘102的顶面102a和外周部分102b不被焊料掩模103覆盖。NSMD焊盘102的顶面102a没有焊料掩模103。用于接收凸块的NSMD焊盘102的区域不取决于第一凹进部分103b的尺寸。第一凹进部分103b大于NSMD焊盘102。
图1B是如图1A中的半导体器件100的一个实施例的顶视图。半导体器件100包括衬底101、焊盘102和焊料掩模103。在一些实施例中，焊料掩模103基本上覆盖衬底101的顶面101a。焊料掩模103包括围绕焊盘102的第一凹进部分103b，从而使得焊料掩模103与焊盘102间隔开。在一些实施例中，在焊盘102和焊料掩模103之间存在环形间隙104。环形间隙104围绕焊盘102。
在一些实施例中，第一凹进部分103b呈圆形或椭圆形，并且焊盘102也呈圆形或椭圆形。在一些实施例中，第一凹进部分103b具有宽度或直径D第一凹进部分，并且焊盘102具有宽度或直径D焊盘。在一些实施例中，第一凹进部分103b的直径D第一凹进部分大于焊盘102的直径D焊盘。在一些实施例中，第一凹进部分103b的直径D第一凹进部分为约300μm至约350μm。在一些实施例中，焊盘102的直径D焊盘为约200μm至300μm。
图2A是半导体器件100的一个实施例。半导体器件100包括衬底101。在一些实施例中，衬底101是包括一些集成电路(IC)的印刷电路板(PCB)，以电连接在其上的半导体部件。在一些实施例中，衬底101呈条状。
在一些实施例中，半导体器件100包括设置在衬底101的表面101a上的焊盘102。焊盘102沿着表面101a水平地延伸。在一些实施例中，焊盘102是用于接收包括铜、锡、铅或焊料等的导电凸块的UBM焊盘。UBM焊盘配置为电连接焊盘102和衬底101内部的电路。在一些实施例中，通过电镀将焊盘102设置在表面101a上。在一些实施例中，焊盘102包括诸如金、银、铜、镍、钨、铝和/或它们的合金的导电材料。
在一些实施例中，半导体器件100包括设置在衬底101的表面101a上方的焊料掩模103。在一些实施例中，焊料掩模103包括诸如液体环氧树脂或聚环氧化物等的聚合物材料。在一些实施例中，焊料掩模103围绕焊盘102。在一些实施例中，焊料掩模103部分地覆盖焊盘102。焊料掩模103覆盖焊盘102的顶面102a的端部和外周部分102b。焊料掩模103与焊盘102接触。
在一些实施例中，暴露顶面102a的中心部分以用于接收凸块。在一些实施例中，焊料掩模103的顶面103a位于焊盘102的顶面102a之上的层级处并且位于焊盘102上方。
在一些实施例中，焊料掩模103包括第二凹进部分103c。在一些实施例中，第二凹进部分103c位于焊盘102之上，焊盘102设置在第二凹进部分103c的下面。在一些实施例中，第二凹进部分103c从焊料掩模103的顶面103a延伸至焊盘102的顶面102a。第二凹进部分103c的底部与顶面102a接界。
在一些实施例中，第二凹进部分103c的侧壁103e设置在焊盘102的顶面102a上。在一些实施例中，第二凹进部分103c配置为暴露焊盘102的顶面102a的中心部分以接收凸块。
在一些实施例中，焊盘102是焊料掩模限定(SMD)焊盘。SMD焊盘102由焊料掩模103部分地覆盖。焊料掩模103围绕SMD焊盘的外周，从而通过焊料掩模103限定用于接收凸块的SMD焊盘102的顶面102a的中心部分。根据第二凹进部分103c的尺寸暴露SMD焊盘102的顶面102a的中心部分。在一些实施例中，第二凹进部分103c小于SMD焊盘102。
图2B是如图2A中的半导体器件100的一个实施例的顶视图。半导体器件100包括衬底101、焊盘102和焊料掩模103。在一些实施例中，焊料掩模103覆盖衬底101的顶面101a和焊盘102的外周部分102b。焊料掩模103包括设置在焊盘102之上的第二凹进部分103c。在一些实施例中，通过焊料掩模103周向地围绕焊盘102的外周部分102b。
在一些实施例中，第二凹进部分103c呈圆形或椭圆形，并且焊盘102也呈圆形或椭圆形。在一些实施例中，第二凹进部分103c具有宽度或直径D第二凹进部分，并且焊盘102具有宽度或直径D焊盘。在一些实施例中，第二凹进部分103c的直径D第二凹进部分小于焊盘102的直径D焊盘。在一些实施例中，第二凹进部分103c的直径D第二凹进部分为约175μm至约250μm。在一些实施例中，焊盘102的直径D焊盘为约250μm至350μm。
图3A是半导体器件200的一个实施例。半导体器件200包括衬底101、焊料掩模103和设置在衬底101的顶面101a上的若干焊盘102。在一些实施例中，焊盘102包括若干NSMD焊盘102-1和若干SMD焊盘102-2。NSMD焊盘102-1具有与图1A和图1B类似的结构。SMD焊盘102-2具有与图2A和图2B类似的结构。在一些实施例中，焊料掩模103覆盖SMD焊盘102-2的外周部分102b，同时与NSMD焊盘102-1间隔开一定距离。
在一些实施例中，焊料掩模103包括若干第一凹进部分103b和若干第二凹进部分103c。NSMD焊盘102-1位于第一凹进部分103b内，并且SMD焊盘102-2设置在第二凹进部分103c的下面。
图3B是如图3A中的半导体器件200的一个实施例的顶视图。半导体器件200包括衬底101、若干NSMD焊盘102-1、若干SMD焊盘102-2和设置在顶面101a上方的焊料掩模103。在一些实施例中，焊料掩模103包括若干第一凹进部分103b和若干第二凹进部分103c，从而使得NSMD焊盘102-1与焊料掩模103间隔开环形间隙104，并且由焊料掩模103周向地覆盖SMD焊盘102-2的外周部分102b。
图4A是半导体器件200的一个实施例。半导体器件200包括衬底101、位于衬底上的焊料掩模103、设置在衬底101上的若干NSMD焊盘102-1和若干SMD焊盘102-2。在一些实施例中，SMD焊盘102-2设置为远离衬底101的拐角101b。在一些实施例中，SMD焊盘102-2设置在衬底101的中心部分处。
在一些实施例中，NSMD焊盘102-1和SMD焊盘102-2布置为一种规则的阵列。NSMD焊盘102-1和SMD焊盘102-2在衬底101上设置为若干水平行和若干垂直列。
在一些实施例中，NSMD焊盘102-1布置在预定位置处。在一些实施例中，预定位置位于衬底101的拐角101b处。NSMD焊盘102-1配置为接收可以与另一衬底上的焊盘电连接的凸块。
在一些实施例中，NSMD焊盘102-1布置在拐角101b处，这是因为NSMD焊盘102-1允许凸块设置在顶面102a上以及NSMD焊盘102-1的外周部分102b上，以最小化或甚至防止焊料掩模103周围的应力集中点的出现。因此，NSMD焊盘102-1在衬底101的拐角101b处的沉积提供了相对于跌落试验、板层面温度循环、板弯曲等的衬底101的改进的可靠性，并且使部件的破裂和分层的出现最小化。
在一些实施例中，焊料掩模103包括若干第一凹进部分103b和若干第二凹进部分103c。在一些实施例中，第一凹进部分103b围绕NSMD焊盘102-1，并且第二凹进部分103c设置在SMD焊盘102-2之上。
在一些实施例中，根据相应的NSMD焊盘102-1的位置，将第一凹进部分103b设置在预定位置处。在一些实施例中，因为NSMD焊盘102-1设置在拐角101b处，所以第一凹进部分103b也设置在衬底101的拐角101b处。第一凹进部分103b的位置与相应的NSMD焊盘102-1的位置相对应。
在一些实施例中，第二凹进部分103c设置在与SMD焊盘102-2的位置相对应的位置处。在一些实施例中，因为相应的SMD焊盘102-2设置在中心部分处，所以第二凹进部分103c也设置在衬底101的中心部分处。第二凹进部分103c的位置与相应的SMD焊盘102-2的位置相对应。
图4B是半导体器件200的一个实施例。半导体器件200包括衬底101、位于衬底上的焊料掩模103、设置在衬底101上的若干NSMD焊盘102-1和若干SMD焊盘102-2。在一些实施例中，SMD焊盘102-2设置在衬底101的中心部分处。
在一些实施例中，NSMD焊盘102-1布置在预定位置处。在一些实施例中，预定位置为位于衬底101的拐角101b处以及邻近拐角101b的拐角区域处。在一些实施例中，NSMD焊盘102-1与拐角101b处的NSMD焊盘102-1邻近。在一些实施例中，存在三个设置在拐角101b和拐角区域处的NSMD焊盘102-1。
在一些实施例中，焊料掩模103包括若干第一凹进部分103b和若干第二凹进部分103c。在一些实施例中，根据相应的NSMD焊盘102-1的位置，将第一凹进部分103b设置在预定位置处。在一些实施例中，第一凹进部分103b设置在拐角101b以及拐角区域处。在一些实施例中，存在三个设置在与相应的NSMD焊盘102-1的位置对应的拐角101b和拐角区域处的第一凹进部分103b。
图4C是半导体器件200的一个实施例。半导体器件200包括衬底101、位于衬底上的焊料掩模103、设置在衬底101上的若干NSMD焊盘102-1和若干SMD焊盘102-2。在一些实施例中，NSMD焊盘102-1和SMD焊盘102-2布置为不规则的阵列，该不规则的阵列包括不含有NSMD焊盘和SMD焊盘的空白区101c。
在一些实施例中，NSMD焊盘102-1布置在预定位置处。在一些实施例中，预定位置位于邻近衬底101的空白区101c的位置处。邻近空白区101c的焊盘102定义为隔离焊盘并且设置为NSMD焊盘102-1。隔离焊盘与少于四个焊盘102邻近。在一些实施例中，存在两个邻近空白区101c的隔离焊盘并且该隔离焊盘设置为NSMD焊盘102-1。
在一些实施例中，焊料掩模103包括若干第一凹进部分103b和若干第二凹进部分103c。在一些实施例中，根据相应的NSMD焊盘102-1的位置，将第一凹进部分103b设置在预定位置处。在一些实施例中，第一凹进部分103b设置为邻近空白区101c。第一凹进部分103b围绕邻近空白区101c的隔离焊盘。在一些实施例中，存在两个设置为邻近空白区101c的第一凹进部分103b，其位置与定义为隔离焊盘的相应的NSMD焊盘102-1的位置对应。
在本发明中，也公开了一种制造半导体器件的方法。在一些实施例中，通过方法300形成半导体器件。方法300包括多步操作，并且描述和说明不应被认为是限制操作的顺序。
图5是制造半导体器件的方法300的一个实施例。方法300包括多步操作(301、302、303、304、305、306、307、308、309)。
如图5A所示，在操作301中，提供了第一衬底101。在一些实施例中，第一衬底101是用于支撑若干半导体部件以及承载衬底内的电路的硅衬底。在一些实施例中，第一衬底101是印刷电路板(PCB)。
如图5B所示，在操作302中，在衬底101的表面101a上设置若干焊盘102。在一些实施例中，焊盘102沿着表面101a水平地设置。在一些实施例中，焊盘102是用于接收凸块的凸块下金属(UBM)焊盘。在一些实施例中，通过电镀将焊盘102设置在表面101a上。在一些实施例中，焊盘102包括诸如金、银、铜、镍、钨、铝和/或它们的合金的导电材料。
如图5C所示，在操作303中，在衬底101的表面101a上方设置焊料掩模103。焊料掩模103覆盖焊盘102和表面101a。在一些实施例中，焊料掩模103包括诸如液体环氧树脂或聚环氧化物等的聚合物材料。在一些实施例中，通过丝网漏印法、喷雾等将焊料掩模103设置在衬底101的表面101a上。
在操作304中，通过多种方法确定焊料掩模上的第一凹槽的位置和第二凹槽的位置。在一些实施例中，第一凹槽的位置和第二凹槽的位置位于预定位置处。
在一些实施例中，通过如图5D所示的方法确定上述位置。图5D是如图5A、图5B和图5C中的半导体器件200的顶视图。在一些实施例中，通过限定具有预定中点NP和预定直径DNP的圆圈105来确定第一凹槽103b的位置和第二凹槽103c的位置。在一些实施例中，圆圈105以中点NP为中心并且具有直径DNP。中点NP是圆圈105的中心。
在一些实施例中，第一凹槽103b的位置确定在圆圈105外部的焊盘102上方的位置处。在一些实施例中，焊盘102设置在距离大于圆圈105的中点NP和圆周之间的距离DNP的位置处。在一些实施例中，圆圈105外部的焊盘102之上的位置是衬底101的拐角101b。因此，第一凹槽103b确定为在拐角101b处并且位于焊盘102上方。在一些实施例中，存在四个设置在焊料掩模103上并且设置在拐角101b处的第一凹槽103b。
在一些实施例中，第二凹槽103c的位置确定在圆圈105内部的焊盘之上的位置处。在一些实施例中，焊盘102设置在距离小于圆圈105的中点NP和圆周之间的距离DNP的位置处。在一些实施例中，圆圈105内部的焊盘102之上的位置是衬底101的中心部分，并因此第二凹槽103c确定在中心部分处。在一些实施例中，存在三十个设置在焊料掩模103上并且设置在衬底101的中心部分处的第二凹槽103c。
在一些实施例中，通过如图5E中的方法来确定第一凹槽和第二凹槽的位置。图5E是如图5A、图5B和图5C中的半导体器件200的顶视图。在一些实施例中，通过限定具有预定中点NP和预定直径DNP的圆圈105来确定第一凹槽103b的位置和第二凹槽103c的位置。在一些实施例中，中点NP是圆圈105的中心。
在一些实施例中，第一凹槽103b的位置确定为在圆圈105外部的焊盘102上方的位置处。在一些实施例中，焊盘102设置在距离大于圆圈105的中点NP和圆周之间的距离DNP的位置处。在一些实施例中，圆圈105外部的焊盘102之上的位置邻近衬底101的拐角101b，并因此第一凹槽103b确定为在邻近拐角101b并且位于焊盘102上方的位置处。在一些实施例中，存在十二个设置在焊盘102上方的焊料掩模103上并且设置在邻近拐角101b的位置处的第一凹槽103b。
在一些实施例中，第二凹槽103c的位置确定为在圆圈105内部的焊盘之上的位置处。在一些实施例中，焊盘102设置在距离小于圆圈105的中点NP和圆周之间的距离DNP的位置处。在一些实施例中，圆圈105内部的焊盘102之上的位置是衬底101的中心部分，并因此第二凹槽103c确定为在中心部分处。在一些实施例中，存在二十四个设置在焊盘102之上的焊料掩模103上并且设置在衬底101的中心部分处的第二凹槽103c。
在一些实施例中，通过如图5F中的方法来确定第一凹槽和第二凹槽的位置。图5F是如图5A、图5B和图5C中的半导体器件200的顶视图。在一些实施例中，根据作为隔离焊盘的焊盘102的定义来确定第一凹槽103b的位置和第二凹槽103c的位置。
在一些实施例中，如果焊盘102邻近衬底101的空白区101c，则将焊盘102定义为隔离焊盘。在一些实施例中，如果焊盘102与少于四个焊盘102邻近，则将焊盘102定义为隔离焊盘。在一些实施例中，存在两个邻近空白区101c的隔离焊盘，并因此将第一凹槽103b设置在隔离焊盘之上。在一些实施例中，第二凹槽103c设置在定义为非隔离焊盘的焊盘102之上。非隔离焊盘是与多于四个焊盘102邻近的焊盘102。
在一些实施例中，通过如图5G中的方法(图5D和图5F的方法的组合)来确定第一凹槽和第二凹槽的位置。图5G是如图5A、图5B和图5C中的半导体器件200的顶视图。在一些实施例中，通过将一个焊盘102定义为隔离焊盘以及限定具有预定中点NP和预定直径DNP的圆圈105来确定第一凹槽103b的位置。第一凹槽103b设置在作为隔离焊盘邻近空白区101c或圆圈105外部的焊盘102上方，而第二凹槽103c设置在作为非隔离焊盘远离空白区101c或圆圈105内部的焊盘102上方。
在一些实施例中，通过如图5H中的方法(图5E和图5F的方法的组合)来确定第一凹槽和第二凹槽的位置。图5H是如图5A、图5B和图5C中的半导体器件200的顶视图。在一些实施例中，通过将焊盘102定义为隔离焊盘以及限定具有预定中点NP和预定直径DNP的圆圈105来确定第一凹槽103b的位置。第一凹槽103b设置在作为隔离焊盘邻近空白区101c或圆圈105外部的焊盘102上方，而第二凹槽103c设置在作为非隔离焊盘远离空白区101c或圆圈105内部的焊盘102上方。
如图5I所示，在操作305中，去除焊料掩模103的一部分。在一些实施例中，参考如上所述的操作304和图5D至图5H，根据对焊盘102上方的第一凹槽103b和第二凹槽103c的位置的确定而去除焊料掩模103的一部分。
如图5I所示，在操作306中，形成焊料掩模103的第一凹槽103b。在一些实施例中，第一凹槽103b形成在焊盘102上方，从而使得焊盘102成为非焊料掩模限定(NSMD)焊盘102-1。NSMD焊盘102-1的结构类似于图1A和图1B中所示的结构。NSMD焊盘102-1相应地位于第一凹槽103b内并且与焊料掩模103间隔开间隙104。
如图5I所示，在操作307中，形成焊料掩模103的第二凹槽103c。在一些实施例中，第二凹槽103c形成在焊盘102之上，从而使得焊盘102成为焊料掩模限定(SMD)焊盘102-2。SMD焊盘102-2的结构类似于图2A和图2B中所示的结构。SMD焊盘102-2相应地位于第二凹槽103c之上并且被焊料掩模103部分覆盖。
如图5J所示，在操作308中，提供了第二衬底401。在一些实施例中，第二衬底401是在晶圆衬底内包括管芯和电路的晶圆衬底。在一些实施例中，在第二衬底401的表面404上设置若干管芯焊盘402。管芯焊盘402配置为用于接收凸块。
在操作309中，将第一衬底101与第二衬底401接合。在一些实施例中，通过若干凸块403将第一衬底101的焊盘102相应地与第二衬底401的管芯焊盘402连接来使第一衬底101与第二衬底401接合。凸块403相应地与管芯焊盘402和焊盘102附接，从而使得第一衬底101内的电路通过焊盘102、管芯焊盘402和凸块403电连接至第二衬底401内的电路。
在一些实施例中，一种半导体器件包括具有表面的衬底、设置在衬底的表面上的若干焊盘，焊盘包括非焊料掩模限定(NSMD)焊盘和焊料掩模限定(SMD)焊盘，并且NSMD焊盘布置在预定位置处。
在一些实施例中，预定位置位于衬底的拐角处。在一些实施例中，SMD焊盘设置为远离衬底的拐角。在一些实施例中，NSMD焊盘和SMD焊盘布置为不规则的阵列，该不规则的阵列包括不含有NSMD焊盘和SMD焊盘的空白区，并且NSMD焊盘布置为邻近空白区域。在一些实施例中，SMD焊盘由焊料掩模部分覆盖。在一些实施例中，NSMD焊盘与焊料掩模间隔开。
在一些实施例中，一种半导体器件包括具有表面的衬底、设置在衬底的表面上的若干焊盘、设置在衬底的表面上方的焊料掩模，焊料掩模包括若干第一凹进部分和若干第二凹进部分，至少一个焊盘相应地位于第一凹进部分内，并且至少一个焊盘相应地设置在第二凹进部分的下面。
在一些实施例中，每个第一凹进部分均大于相应的一个焊盘。在一些实施例中，每个第二凹槽部分均小于相应的一个焊盘。在一些实施例中，第一凹进部分设置在衬底的拐角处。在一些实施例中，第二凹进部分设置在衬底的中心部分处。
在一些实施例中，一种制造半导体器件的方法包括：提供衬底，在衬底的表面上设置若干焊盘，在衬底的表面和焊盘的上方设置焊料掩模，在焊料掩模中形成第一凹槽以围绕其中的一个焊盘，以及在焊料掩模中并且在其中的一个焊盘之上形成第二凹槽。
在一些实施例中，当与第一凹槽相对应的焊盘中的一个设置在衬底的拐角处时，形成第一凹槽。在一些实施例中，该方法还包括确定在焊料掩模上形成的第一凹槽的位置和第二凹槽的位置。在一些实施例中，该方法还包括限定具有预定中点和预定直径的圆圈以确定焊料掩模上的第一凹槽的位置和第二凹槽的位置。
在一些实施例中，第一凹槽定位为围绕设置在具有预定中点和预定直径的圆圈外部的焊盘中的一个。在一些实施例中，第二凹槽定位为位于设置在具有预定中点和预定直径的圆圈内部的焊盘中的一个之上。在一些实施例中，该方法还包括将邻近衬底的空白区域的焊盘中的至少一个定义为隔离焊盘。在一些实施例中，形成第一凹槽以围绕定义为隔离焊盘的焊盘。在一些实施例中，定义为隔离焊盘的焊盘与少于四个焊盘邻近。
已经在以上实例和描述中充分地描述了本发明的方法和特征。应该理解，在不背离本发明的精神的情况下的任何更改或改变涵盖在本发明的保护范围内。
此外，本申请的范围不旨在限于说明书中描述的工艺、机器、制造、和物质组成、工具、方法和步骤的特定实施例。本领域的普通技术人员将容易地从本发明的公开内容理解，根据本发明，可以利用现有的或之后将开发的与本文描述的相应实施例实施基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、工具、方法或步骤。
因此，所附权利要求旨在将这些工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。此外，每个权利要求构成单独的实施例，并且各个权利要求和实施例的组合在本发明的范围内。

Claims (10)

1.一种半导体器件，包括：
衬底，包括表面；
多个焊盘，设置在所述衬底的表面上；
其中，所述多个焊盘包括非焊料掩模限定(NSMD)焊盘和焊料掩模限定(SMD)焊盘，并且所述NSMD焊盘布置在预定位置处。
2.根据权利要求1所述的半导体器件，其中，所述预定位置位于所述衬底的拐角处。
3.根据权利要求1所述的半导体器件，其中，所述SMD焊盘设置为远离所述衬底的拐角。
4.根据权利要求1所述的半导体器件，其中，所述NSMD焊盘和所述SMD焊盘布置为不规则的阵列，所述不规则的阵列包括不含有所述NSMD焊盘和所述SMD焊盘的空白区域，并且所述NSMD焊盘布置为邻近所述空白区域。
5.根据权利要求1所述的半导体器件，其中，所述SMD焊盘被焊料掩模部分覆盖。
6.根据权利要求1所述的半导体器件，其中，所述NSMD焊盘与焊料掩模间隔开。
7.一种半导体器件，包括：
衬底，包括表面；
多个焊盘，设置在所述衬底的表面上；
焊料掩模，设置在所述衬底的表面上方；
其中，所述焊料掩模包括多个第一凹进部分和多个第二凹进部分，所述多个焊盘中的至少一个相应地位于所述多个第一凹进部分内，并且所述多个焊盘中的至少一个相应地设置在所述多个第二凹进部分的下面。
8.根据权利要求7所述的半导体器件，其中，所述多个第一凹进部分中的每个均大于所述多个焊盘中的相应的一个。
9.根据权利要求7所述的半导体器件，其中，所述多个第二凹槽部分中的每个均小于所述多个焊盘中的相应的一个。
10.一种制造半导体器件的方法，包括：
提供衬底；
在所述衬底的表面上设置多个焊盘；
在所述衬底的表面和所述多个焊盘的上方设置焊料掩模；
在所述焊料掩模中形成第一凹槽以围绕所述多个焊盘中的一个；以及
在所述焊料掩模中并且在所述多个焊盘中的一个之上形成第二凹槽。
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US10964659B2 (en) 2021-03-30
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US9831205B2 (en) 2017-11-28
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US20150137349A1 (en) 2015-05-21
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