TW564534B - Chip carrier - Google Patents

Abstract

A chip carrier for ball grid array semiconductor package is proposed, with at least a core layer, a set of conductive traces formed on the dice attached surface of the core and solder mask coating on the conductive traces. There is at least one trace across the interval between terminal of one trace and corresponding to the other, and the first opening and the second opening individually formed on the solder mask corresponding to the terminal of the conductive traces. As a result, conductive paste applied on the solder mask corresponding to the first opening and the second opening is composed as a conductive pathway in a following way: ""traces-first opening-conductive paste-second opening-traces"". Moreover, wire conductive bridges are replaced with conductive paste, so as to avoid bridges being touched by wires, and to avoid trace cross problems of wire bonding area of the substrate. Simultaneously, cost of fabrication may further be reduced if replacing the conductive bridges with cheaper globing technology.

Description

564534 ——— 一 丨 Off 丨, V. Description of the invention (1) [FIELD OF THE INVENTION The present invention relates to a wafer carrier, which is a wafer carrier for electrically connecting too many conductor wafers to the back of a substrate and suitable for semi-packages. . Undressing Ball Grid Array Semiconductor [Background of the Invention]:

Ball Grid Array BGA A-conductor packaging technology, which is characterized by the use of a substrate i;: ;; into the half piece ", the substrate is mounted on the back of a plurality of; ::; with = (Solder Balls),. 7 M i ^ ^ w 丨 平 夕 丨 ”The solder balls arranged in a row are connected to the external printed electrical board., V The package structure is soldered and electrically connected. Figure 3 shows the front of a typical ball grid array 20. On 2Ga, XiRi and 2tA1 are placed on the substrate | t ^ m; 0Hirri film 21 has an active surface 210 and an opposite 212 Λ plane Λ ", a plurality of welds are formed on the Haier surface 210. The pads are one-to-one and one-to-one solder balls 24, which are implanted on the back surface 20b of the substrate 20 and correspond to the wafer pads 2 1 2 in a paired manner. Conventionally, only thunder w :, hit, the method is The wafer pad 212 on the semiconductor wafer 21 is connected to the bonding wire pad 2 04 (Finger), the conductive trace 20 (Trace), the conductive two = 20 3 (Vlas), and the solder ball pad (Ban pad). ) (Not shown) is connected to its corresponding solder ball 24 (however, Figure 4 and the following figures are shown as =: the diagram illustrates the packaging structure of the present invention only in a schematic way, I only shows Show the elements related to the present invention, the actual number of each element | mesh, shape, layout and size ratio may be more complicated.) 16955.ptd Page 6 564534 V. Description of the invention (2) Figure 4 shows the ball A type of substrate circuit layout for a gate array semiconductor package. As shown in the figure, this substrate circuit layout is used to place a plurality of pads (here only four pads are shown, and their numbers are 2 1 2 A , 2 1 2 B, 2 1 2 C, 2 1 2 D) are electrically connected to the corresponding solder balls (here only represented by four fresh balls 24A, 24B, 24C, 24D). Known chip electrical connection Firstly, a plurality of bonding wires (Finger) are arranged beside the semiconductor wafer 21, and the bonding wires 2 3 A, 2 3 B, 2 3 C, and 2 3 D are electrically connected to the bonding pads respectively. 204A, 204B, 204C, and 204D, and then through a plurality of conductive through holes 203A, 203B, 203C, and 203D penetrate the substrate 20 and are electrically connected to the solder balls corresponding to the back surface 20b of the substrate 20.

As can be seen from the circuit layout of the substrate shown in Figure 4, all of the wire recording pads are electrically connected to their corresponding conductive vias through continuous conductive traces 201 A, 20 1B, 20 1C, and 201 D, respectively. 203A, 203B, 203C, and 203D so that each wafer pad 2 1 2 A, 2 1 2 B, 2 1 2 C, 2 1 2 D can be generated between its corresponding solder balls 24A, 24B, 2 4C, 24D Electrical connection relationship. However, this type of continuous conductive traces that do not interfere with each other is only an ideal state in circuit layout. In fact, the circuit layout of the substrate often results in trace obstruction (Cross).

I n t e r ρ 〇 s i t i ο η) problem. As shown in Fig. 5, if it is assumed that the bonding wire 〇2 〇4 A corresponds to the solder ball 2 4 B, and the bonding pad 2 0 4 B corresponds to the solder ball 2 4 A, in this case, the bonding wire A continuous conductive trace 2 0 8 must be provided between the pad 2 4 A and its corresponding conductive through hole 2 0 3B (as the position of the solder ball 2 4 B) to connect the two. However, as shown in the figure, at least one conductive trace (such as the conductive trace 2 0 1 B) has been originally arranged between the bonding pad 20 4B and the conductive through hole 230 3A.

564534 V. Description of the invention (3) A continuous conductive trace 2 0 1 A is set between the pad 2 0 4B and the conductive through-hole 2 0 34. The conductive trace 2 0 1 A is bound to intersect with other conductive traces without 0 1 8 o'clock. Traces to connect with each other. The nucleus continuous figure 6 provides a conventional solution to the above problems. ^ When the circuit layout is implemented under the original substrate, an additional circuit layer (c 丨 γ is attached to the layer) is used for routing, so as to avoid the intersection of the circuit and the crossing line through the lower circuit ball. As shown in the figure, a fresh plate is prepared as the substrate 30. The substrate 30 has two or more substrates and two brushes on the substrate. The soil plate 30 'is patterned to form Ximei and Zeng traces. After the line 30 1 ′, guide the upper layer 22 =, 3 0 1 'through the at least one conductive through hole 3303 to the lower US Cup qn ", it ’s really Ding Sidao | Dian AP AP & the lower conductive through hole 3 〇3, is connected to the solder ball 34 of the 30th surface of the substrate. Therefore, under the continuity between Γ 丄 304B and the corresponding solder ball 3 ", it can pass through the upper layer \ electrical trace 3 〇i, an upper layer conductive speech: Γ ί lower conductive through hole 3 03" and another path : Ϊ to = X and ball 34A, 俾 to solve the problem of the intersection of different traces. To the cloth == used, 'because of the general ball grid array package structure, the forward-looking type can be too much of the solder balls and wafer pads' and As a result, the circuit layout of the substrate is complicated. Therefore, if a multi-layer method is used to carry out a κ sa Φ, # address to the corresponding soldering +, + Ρ *-Μ 沣, σ will be more than 1 dry pad conductive connection In the case of complicated substrates, the number of substrate layers is even as high as 6 1 so that the sealing substrate layer I will increase the complexity and cost of the circuit fabric. Trend. The overall thickness is increased, which does not meet the light and short electronic production f. β arrived here, and Taiwan Patent Application No. 9 0 1 8 9 7 2 then unveiled a way to solve the problem of trace crossing from the bridge element.

16955.ptd Page 8 564534 V. Description of the invention (4) As shown in FIG. 7, the ball grid array semiconductor package structure includes a substrate 40 and at least one connected to the substrate 4. Wafer 41 (each welding pad is represented by 412A, 412B, 412C, 412D), and a plurality of bonding pads 4 are formed around the substrate 40 where the wafer 41 is placed. 4 〇4 A4 〇4 β, 4 04C, 4 04D 'To electrically connect the solder balls 44A, 44B, 4 4C, 44D through conductive traces and conductive vias, respectively. However, as shown in the figure, when the bonding pad 4 04B and the solder ball 44A are to be connected by conductive traces, the continuous conductive trace 40 ^ will cross the groove at the bonding pad 4 0 and is extremely conductive. Between the holes 408 (the same position as the solder ball 44A), the bonding pads 404β and their corresponding conductive vias 4 0 3 Α cannot be connected with each other using continuous conductive traces. The problem that the 404B and the conductive vias 40 cannot be electrically connected. The industry therefore uses a conductive trace 47 connected to the bonding pad 404B and a conductive trace 47 connected to the conductive via 4 0 3A. Or, a zero-resistance chip resistor 48 (Chip Res istor) electrically connects the bonding pad 404B and its corresponding conductive via 403A to avoid continuous conductive traces placed on the same circuit surface. 4 〇1 A. Yu yi f i ΐ ϋ: The electrical connection method of the bridge element across the traces does not require Γ, cost, but it becomes higher and higher as the chip becomes more integrated. At this time, in order to prevent the inferiority of the Ba κ Η 生 Η τ 由 ^ 十 a # # ^ The gold wire between the Wanzhiri film and the 1 main line pad accidentally touched the cross-line short circuit. & It also occurs in the wiring area of the substrate, so this method cannot be adopted and it will hinder the substrate design. 〆 On the other hand, the bridge wire or passive k is used to electrically connect the obstructed p early traces to the electrical components (such as the above chip resistor ′ bridge wire arc and passive elements).

564534 V. Description of the invention (5)

The height of the component will hinder wire bonding. S The above electrical connection method is only applicable to L = does not affect the wiring of gold wires. For the trace intersection between the chip and the bonding pads, the substrate outside the area, use the wire bonding method or solder Xidong Nai: It is difficult to improve; secondly, it will also increase the complexity of the process. 2 π pieces must increase the number of work steps, board traces and crossovers. An effective 5 'industry urgently needs the basics [Summary of Invention]: Liver resolution. The main purpose of the present invention is to prevent long-distance isoelectric solder balls from being able to be used, which can improve the problem of electrical solder balls due to circuit restrictions (such as the problem of multiple ground pads), so that multiple identical ones can be achieved using existing process technology. Several fresh power balls) only need the complex-purpose connection of the present invention; the wafer carrier of the purpose. The intersection of traces is another problem, and then one of them can be used to solve any position of the substrate. Wafer loading with flexible layout of the substrate This test: The purpose of the month # is to provide a way to avoid the impact of wire bonding and improve the substrate mounting FK & "The objective of this problem is to provide a wafer carrier that does not increase the cost of processing steps and avoid the increase in the unit price of the substrate. Based on the above and other purposes, the present invention is applicable to balls The wafer carrier of a gate array semiconductor package includes at least one core layer, which has at least one surface on which the wafer is adhered. A plurality of conductive traces are arranged on the surface, and at least two conductive traces are at the end. Correspond to each other with a gap to allow other conductive traces to pass through it; a solder resist layer covering the majority of the conductive

16955.pul Page 10 564534 V. Description of the invention (6) '~~~ Trace 3 and a first opening and a second opening are provided at the end positions corresponding to the two conductive traces for the two conductive traces The end of the wire exposes the solder resist layer, and a conductive coating is applied to a predetermined area of the solder resist layer to connect the ends of the two conductive traces through the first opening and the second opening.俾 Make the two conductive traces form an electrical connection relationship. Compared with the conventional substrate, the conductive adhesive of the wafer carrier of the present invention can be coated, and any trace intersection on the surface of the core layer allows the end of the wire to pass through the conductive adhesive or conductive carbon. Make a flexible connection to avoid other traces under the solder resist layer. ^ $ Conductive glue or conductive toner is applied to the cross contacts to provide electrical bridges 2: Rows: Traditionally, because of the concern that the gold wires connected to the chip accidentally touch the bridge components: = To solve the problem of trace crossing at any position on the substrate; even ) '5 的 电 电 ΪSettings; ΐ 限制 is limited and can not be connected to a long distance electrical connection high ΠΓ :: conductive path formed by conductive glue to introduce [detailed description of the invention]: Figure 1 Figure 2 and 3α and the detailed meaning of X1 X 1 embodiment of your daily film carrier. Application of the board-the majority of the substrate 10, placed on the base gold wire 13 and electrically connected to the θH 丨 bu substrate 10 and the chip 1 1 are transmitted to the external printed circuit board ( The ball grid array semiconductor package is not shown to overcome the aforementioned problems. Trace Cross and other problems need to be changed

16955.ptd Page 11 564534 V. Description of the Invention (7) The substrate circuit layout can only be used for packaging, so the following is only a detailed description of the structure of the substrate. For other components and their connection relationships, please refer to the conventional ball grid array package structure. As shown in FIG. 2, the substrate 10 is suitable for a single-layer substrate or a build-up multilayer board, and includes a core layer 100. The core layer 100 is patterned on the surface to form a plurality of conductive traces. Line 101, a solder resist layer 1 〇2 (S ο 1 der M ask) is provided on the top of the trace 101, and the trace 1 〇1 is electrically isolated from the outside. A conductive trace 1 〇1 It can pass through the conductive through holes 103 inside the core layer and is electrically connected one-to-one with the solder ball pad (not shown) on the other surface of the core layer 100. This is a common practice and will not be repeated here. However, when the package is limited by the circuit design or space constraints and wants to connect the solder balls with a longer distance or overcome the Trace Cross problem, the circuit layout of the substrate needs to be further as shown in Figure 1. The core layer 100 is a resin insulating layer made of FR4 resin, glass tree moon purpose 2 = grease, etc., and has an upper surface i〇〇a Ξ _, which is previously defined on the upper surface 100a- Wafer placement ㈣ (not shown), and a plurality of = electric traces are arranged outside the wafer placement area. The conductive traces include at least a first trace 101 and a second trace ioib. An end portion 106a of the first trace 101a (hereinafter referred to as a first end portion 106a) is connected to the first trace portion 101a. The ends i06b (with end 106b) of the two traces 10lb correspond to each other, and the first and second ends are separated by a distance for other conductive traces 丨 〇 丨 c to pass through. ′, The first trace 101a may be connected to the first end portion 106. This: the bonding wire 塾 KI or the first end portion 106 may be bumped through the first conductive through hole 103.

16955.ptd Page 12

564534 V. Description of the invention (8) The first solder ball 丨 4 a which is in contact with the lower surface 1 0 0 b of the core layer 1 0; the second trace 1 0 1 b is through a second conductive through hole 103 b is connected to the second solder ball 1 4 b on the lower surface 1 0 0 b of the core layer, and at the same time the first and second solder balls 1 4 a, 1 4 b can have the same electrical properties (such as These are ground balls (Ground Bal 1) or power balls (P ower B a 1 1). The solder resist layer 102 is coated on the surface of the core layer 100a, which is 100a, so as to protect the traces 101 from the external electrical interference. As shown in Figs. 1 and 2, the solder resist layer 102 forms a wire bonding area i02b outside the wafer-mounting area of the core layer 100 to provide a majority of finger pad distribution for gold wires. 13 is connected to electrically connect the wafer 11 and the substrate 10. The wafer carrier of the present invention is different from the conventional substrate in that the first end portion 106a and the first end portion 106b of the conductive trace 10 are respectively provided with a first for trace exposure. The opening of the solder resist layer 105a (referred to as the first opening 105a) and the opening of the second solder resist layer 105b (referred to as the second opening 105b) are provided for a conductive coating 12 to connect . The conductive coatings 12 are commonly used conductive silver glue, conductive carbon (Conductive Carbon), etc., other flowable or non-flowable conductive adhesives can also be applied to the present invention. If it is considered from this embodiment that after the conductive paste is applied onto the solder resist layer 1 by screen printing, the fluid conductive paste 12 will be connected and fill the first opening 105a and The second opening 1 0 5 b electrically connects the first trace 10a and the second trace 1b. In this way, the first and second solder balls 丨 4 a, 丨 4 b, which are far apart, can form a "first solder ball (or the first trace of the wire pad) through the conductive adhesive 12

Page 13 564534 V. Description of the invention (9) Electrical connection path of "wire-conductive glue _ second trace-second fresh ball" to solve the problem of trace crossing; at the same time, solder balls with the same electrical properties can also be used. Under the consideration of the existing process scale and without increasing the cost of the substrate, the cross-circuit and space constraints are broken to improve the layout flexibility of the circuit. The foregoing are merely preferred embodiments of the present invention, and are not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person, if it is exactly the same as defined in the scope of patent application described below, or an equivalent change, will be considered to be covered by this patent scope.

16955.ptd Page 14 564534

Brief description of the drawings [Simplified description of the drawings]: Figure 1 is a partial top view of the present invention applicable to the wafer carrying of BGA semiconductor packages; Figure 2 is a cross-sectional view of the wafer carrying members of the present invention applicable to BGA semiconductor packages. Intent; 苐 3 is a cross-sectional view of a conventional Ball Grid Array (BGA) semiconductor package; FIG. 4 is a schematic diagram of a circuit layout of a conventional BGA semiconductor package in an ideal state; FIG. 5 is a conventional BGA The circuit layout of the semiconductor package with trace barriers is not intended; Figure 6 is a schematic cross-sectional view of a semiconductor package conventionally used to build a layer to solve trace crossing; and Figure 7 is a semiconductor conventionally used to bridge components to resolve trace crossing Partial top view of the seal. < [Description of component symbols]: 1 0, 2 0, 3 0, 40 Substrate 10 0 Core layer 100a Upper surface of core layer 10 〇b Lower surface of core layer 1 0 1, 2 0 1, 2 0 1 A to D , 3 0 1 ', 3 0 1π, 4 0 1 A to D conductive traces 10 2 solder resist layer 102 b wire area 1 0 3, 2 0 3, 2 0 3A to D, 3 0 3', 3 03 ", 4 0 3A to D conductive vias

16955.ptd Page 15 564534

Brief description of the drawing 1 0 4, 2 0 4, 2 04A to D, 404A to D Fresh line 塾 104 Fresh line pad 105a First opening 105b Second opening 11, 21, 31 Chip 12 Conductive adhesive 1 3, 2 3, 2 3A to D gold wire 1 4, 24, 24A to D solder ball 14a first solder ball 14b second solder ball 210 active surface 211 non-active surface 212, 212A to D, 412A to D wafer pad 30 'upper substrate 30 π lower substrate 4 7, 4, 4 7 π conductive trace 48 bridge element 16955.ptd page 16

Claims (1)

564534 6. Scope of patent application 1. A wafer carrier includes: a core layer having at least a surface on which a wafer is adhered, a plurality of conductive traces are arranged on the surface, and at least two conductive trace ends The parts correspond to each other and are separated by a distance for other conductive traces to pass through a solder resist layer. The conductive traces are applied to the plurality of conductive traces and a first opening is formed at a position corresponding to the ends of the two conductive traces. And a second opening, so that the ends of the two conductive traces expose the solder resist layer; and a conductive coating is applied on the solder resist layer so as to be electrically conductive through the first opening and the second opening Connect the ends of the two conductive traces to form an electrical connection relationship between the two conductive traces. 2. For example, the wafer carrier of the first patent application scope, wherein the two conductive traces are respectively connected to a first fresh ball and a second solder ball. 3. For the wafer carrier according to item 2 of the patent application scope, wherein the first solder ball and the second fresh ball are fresh balls having the same electrical properties. 4. For example, the wafer carrier of the scope of the patent application, wherein the two conductive traces are respectively connected to a fresh wire and a solder ball. 5. The wafer carrier according to item 1 of the patent application scope, wherein the conductive coating is a conductive silver glue. 6. The wafer carrier according to item 1 of the patent application scope, wherein the conductive coating is a conductive carbon. 7. For example, the wafer carrier of the scope of patent application, wherein the conductive coating is coated on the rejection by screen printing (S c r e e η P r i n t i ng). 16955.ptd Page 17 564534 6. Scope of patent application On the flux layer. 1IIII 16955.ptd Page 18