JP5107270B2 - 実装基板および電子機器 - Google Patents
実装基板および電子機器 Download PDFInfo
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Description
BGAパッケージが採用された半導体装置では、実装基板との対向面に、ボール状の外部端子が正方行列状に整列して配列されている。これに対応して、実装基板上には、各外部端子と接続されるランドが正方行列状に整列して配列されている。たとえば、100個の外部端子を備える半導体装置が実装される実装基板(100ピン用実装基板)上には、100個の外部端子に対応して、100個のランドが10行×10列の正方行列状に整列して配列されている。各ランドには、半導体装置の動作電圧の供給や各種信号を送受するための配線が接続されている。各配線は、実装基板上の半導体装置が接合される領域外へ引き出され、実装基板上の電源回路などに接続されている。
そこで、本発明の目的は、コストの低減を図ることができる構造の実装基板およびこれに半導体装置を表面実装してなる電子機器を提供することである。
2 実装基板
19 外部端子
21 ランド(接合部)
22 絶縁層
23 表側配線層
24 裏側配線層
25 配線
28 配線
100 電子機器
図1は、本発明の一実施形態に係る電子機器の構成を図解的に示す断面図である。
電子機器100は、表面実装型の半導体装置1を実装基板2に表面実装した構成を有している。
半導体装置1は、半導体チップ11と、半導体チップ11が搭載されるインタポーザ12と、半導体チップ11を封止する封止樹脂13とを備えている。
インタポーザ12は、絶縁性樹脂(たとえば、ガラスエポキシ樹脂)からなる絶縁性基板14を備えている。
半導体装置1(絶縁性基板14)の下面には、104個の外部端子19が8行×13列の行列状に整列して配置されている。言い換えれば、104個の外部端子19は、4行×9列およびこれを取り囲む環状2列に配列されている。なお、図面の簡素化のため、図2では、一部の外部端子19のみに参照符号を付している。
実装基板2の表面には、半導体装置1の外部端子19に対応して、104個のランド21が8行×13列の行列状に整列して配置されている。なお、図面の簡素化のため、図3では、一部のランド21のみに参照符号を付している。
図4は、実装基板2の断面図である。
図5は、表側配線層23の一部を示す平面図である。
表側配線層23には、104個のランド21と、最外の環状2列をなすランド21(図3にハッチングを付して示す。)に接続された配線25とが形成されている。
図6は、裏側配線層24の一部を示す底面図である。
裏側配線層24には、各ビア26に接続された配線28が形成されている。配線28は、銅などの金属からなる。4行×9列における外側各行に配列された各ビア26に接続される配線28は、各ビア26から外側に向けて列方向(図6の紙面における上下方向)に沿って延びている。4行×9列における内側2行に配列された各ビア26のうちの行方向(図6の紙面における左右方向)両端に配置される各ビア26に接続される配線28は、各ビア26から外側に向けて行方向に沿って延びている。また、内側2行×7列に配列された各ビア26に接続される配線28は、外側各行に配列された各ビア26に接続される配線28の間を通して、外側に向けて延びている。そして、各配線28は、実装基板2上の電源回路などに接続されている。
なお、本発明は、他の形態で実施することもできる。たとえば、裏側配線層24において、4行×9列における内側の2行に配列された各ビア26のうちの行方向両端に配置される各ビア26に接続される配線28は、各ビア26から外側に向けて行方向に沿って延びているとしたが、図6に破線で示すように、列方向に引き出されてもよい。
この出願は、2007年2月7日に日本国特許庁に提出された特願2007−27953号に対応しており、この出願の全開示はここに引用により組み込まれるものとする。
Claims (2)
- 行列状に整列して配列された外部端子を有する半導体装置が実装される実装基板であって、
前記半導体装置が対向される表面に配列され、各前記外部端子が接合される接合部と、
各前記接合部に接続され、前記半導体装置が接合される領域外に引き出される配線とを備え、
内側に配列された4行×n列(n:5以上の整数)個の各前記接合部に接続される前記配線は、第1の配線層に形成され、
前記4行×n列個の前記接合部の外側を取り囲む環状2列に配列された各前記接合部に接続される前記配線は、前記第1の配線層とは異なる第2の配線層に形成されており、
前記内側に配列された4行×n列個の各接合部に接続される配線は、前記4行×n列個の接合部のうちの内側の2行×(n−2)列に配列された各接合部に接続される配線を前記4行における外側各行に配列された接合部のうちの隣り合う接合部に接続された配線の間に1本のみを通すようにして、前記第1の配線層に形成されており、
前記4行×n列個の接合部の外側を取り囲む環状2列に配列された各接合部に接続される配線は、当該環状2列における内側の列に配列された各接合部に接続される配線を当該環状2列における外側の列に配列された接合部のうちの隣り合う接合部に接続された配線の間に1本のみを通すようにして、前記第2の配線層に形成されている、実装基板。 - 実装基板と、行列状に整列して配列された外部端子を有し、前記実装基板に対して表面実装される半導体装置とを含む電子機器であって、
前記実装基板は、
前記半導体装置が対向される表面に配列され、各前記外部端子が接合される接合部と、
各前記接合部に接続され、前記半導体装置が接合される領域外に引き出される配線とを備え、
内側に配列された4行×n列(n:5以上の整数)個の各前記接合部に接続される前記配線は、第1の配線層に形成され、
前記4行×n列個の前記接合部の外側を取り囲む環状2列に配列された各前記接合部に接続される前記配線は、前記第1の配線層とは異なる第2の配線層に形成されており、
前記内側に配列された4行×n列個の各接合部に接続される配線は、前記4行×n列個の接合部のうちの内側の2行×(n−2)列に配列された各接合部に接続される配線を前記4行における外側各行に配列された接合部のうちの隣り合う接合部に接続された配線の間に1本のみを通すようにして、前記第1の配線層に形成されており、
前記4行×n列個の接合部の外側を取り囲む環状2列に配列された各接合部に接続される配線は、当該環状2列における内側の列に配列された各接合部に接続される配線を当該環状2列における外側の列に配列された接合部のうちの隣り合う接合部に接続された配線の間に1本のみを通すようにして、前記第2の配線層に形成されている、電子機器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008557070A JP5107270B2 (ja) | 2007-02-07 | 2008-01-29 | 実装基板および電子機器 |
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Application Number | Priority Date | Filing Date | Title |
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JP2007027953 | 2007-02-07 | ||
JP2007027953 | 2007-02-07 | ||
PCT/JP2008/051250 WO2008096633A1 (ja) | 2007-02-07 | 2008-01-29 | 実装基板および電子機器 |
JP2008557070A JP5107270B2 (ja) | 2007-02-07 | 2008-01-29 | 実装基板および電子機器 |
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Publication Number | Publication Date |
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JPWO2008096633A1 JPWO2008096633A1 (ja) | 2010-05-20 |
JP5107270B2 true JP5107270B2 (ja) | 2012-12-26 |
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US (1) | US7939951B2 (ja) |
JP (1) | JP5107270B2 (ja) |
CN (1) | CN101601129B (ja) |
TW (1) | TWI433281B (ja) |
WO (1) | WO2008096633A1 (ja) |
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JP5955216B2 (ja) * | 2012-12-30 | 2016-07-20 | 京セラ株式会社 | プローブカード用配線基板 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH1013026A (ja) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | 多層プリント配線板 |
JPH11260956A (ja) * | 1998-03-11 | 1999-09-24 | Shinko Electric Ind Co Ltd | 多層回路基板 |
JP2000150735A (ja) * | 1998-11-17 | 2000-05-30 | Lucent Technol Inc | 回路組立体および集積回路デバイスに放熱器を接続する方法 |
JP2006066753A (ja) * | 2004-08-30 | 2006-03-09 | Hirose Electric Co Ltd | 伝送回路基板 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US5952726A (en) * | 1996-11-12 | 1999-09-14 | Lsi Logic Corporation | Flip chip bump distribution on die |
US6285560B1 (en) * | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
CN1369122A (zh) * | 2000-06-12 | 2002-09-11 | 三菱电机株式会社 | 插件连接装置、包含它的安装基板和包含它们的电子设备 |
US6770963B1 (en) * | 2001-01-04 | 2004-08-03 | Broadcom Corporation | Multi-power ring chip scale package for system level integration |
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
JP4137929B2 (ja) * | 2005-09-30 | 2008-08-20 | シャープ株式会社 | 半導体装置 |
JP2009123993A (ja) * | 2007-11-16 | 2009-06-04 | Nec Electronics Corp | 半導体集積回路装置 |
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2008
- 2008-01-29 WO PCT/JP2008/051250 patent/WO2008096633A1/ja active Application Filing
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH1013026A (ja) * | 1996-06-19 | 1998-01-16 | Ibiden Co Ltd | 多層プリント配線板 |
JPH11260956A (ja) * | 1998-03-11 | 1999-09-24 | Shinko Electric Ind Co Ltd | 多層回路基板 |
JP2000150735A (ja) * | 1998-11-17 | 2000-05-30 | Lucent Technol Inc | 回路組立体および集積回路デバイスに放熱器を接続する方法 |
JP2006066753A (ja) * | 2004-08-30 | 2006-03-09 | Hirose Electric Co Ltd | 伝送回路基板 |
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CN101601129B (zh) | 2011-08-17 |
TW200845338A (en) | 2008-11-16 |
JPWO2008096633A1 (ja) | 2010-05-20 |
TWI433281B (zh) | 2014-04-01 |
US20100314770A1 (en) | 2010-12-16 |
WO2008096633A1 (ja) | 2008-08-14 |
US7939951B2 (en) | 2011-05-10 |
CN101601129A (zh) | 2009-12-09 |
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