TWI433281B - Installation of the substrate and electronic equipment - Google Patents

Installation of the substrate and electronic equipment Download PDF

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TWI433281B
TWI433281B TW097104069A TW97104069A TWI433281B TW I433281 B TWI433281 B TW I433281B TW 097104069 A TW097104069 A TW 097104069A TW 97104069 A TW97104069 A TW 97104069A TW I433281 B TWI433281 B TW I433281B
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rows
wiring
mounting substrate
semiconductor device
wiring layer
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TW097104069A
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TW200845338A (en
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Hirotoshi Usui
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

安裝基板及電子機器
本發明係關於表面安裝半導體裝置之安裝基板、及將半導體裝置表面安裝於此安裝基板所構成之電子機器。
作為可施行半導體裝置之表面安裝之封裝(表面安裝型封裝)之代表者，已知例如有BGA(Ball Grid Array：球柵陣列)封裝。
在採用BGA封裝之半導體裝置中，在與安裝基板之對向面，球狀之外部端子係被整齊排列成正方行列狀。對應於此，在安裝基板上，與各外部端子連接之接合部係被整齊排列成正方行列狀。例如，在安裝100個外部端子之半導體裝置之安裝基板(100接腳用安裝基板)上，對應於100個外部端子，100個接合部被整齊排列成10列×10行之正方行列狀。在各接合部，連接半導體裝置之動作電壓之供應及各種信號之送受用之布線。各布線被引出至安裝基板上之接合半導體裝置之區域外，並被連接於安裝基板上之電源電路等。
在現在提供之100接腳用之安裝基板上，例如如圖7所示，在列方向及行方向，每隔0.5 mm配置著0.2 mm見方之矩形狀之接合部L。由於此種接合部L之配置，在列方向或行方向相鄰之接合部L間之寬度窄至只有0.3 mm，連接於該等接合部L之各布線間只能通過1條布線。因此，在同一面(1個布線層)，只能形成連接於構成環狀2行之接合部L 之布線。因此，連接於各接合部L之布線分開形成於複數之布線層。具體言之，連接於構成最外之環狀2行之接合部L(在圖7中附上右上之影線表示)之布線、在其內側連接於構成環狀2行之接合部L(在圖7中附上左上之影線表示)之布線、及連接於中央4個之接合部L(在圖7中未附上影線表示)之布線係分別形成於相異之布線層。
[專利文獻1] 日本特開2000－150735號公報
然而，此種多層布線構造之安裝基板具有層數愈多時成本愈高之問題。
因此，本發明之目的在於提供可謀求成本之降低之構造之安裝基板及將半導體裝置表面安裝於此所構成之電子機器。
達成前述之目的用之請求項1所記載之發明之安裝基板係安裝具有整齊排列成行列狀之外部端子之半導體裝置者，且包含：接合部，其係排列於前述半導體裝置所對向之表面，並接合各前述外部端子；及布線，其係被連接於各前述接合部，且被引出至接合前述半導體裝置之區域外；連接於排列於內側之4列×n行(n：5以上之整數)個之各前述接合部之前述布線係形成於第1布線層；連接於排列於包圍前述4列×n行個之前述接合部之外側之環狀2行之各 前述接合部之前述布線係形成於異於前述第1布線層之第2布線層。
又，請求項2所記載之發明之電子機器係包含安裝基板、與具有整齊排列成行列狀之外部端子，且被表面安裝於前述安裝基板之半導體裝置者；前述安裝基板係包含：接合部，其係排列於前述半導體裝置所對向之表面，並接合各前述外部端子；及布線，其係被連接於各前述接合部，且被引出至接合前述半導體裝置之區域外；連接於排列於內側之4列×n行(n：5以上之整數)個之各前述接合部之前述布線係形成於第1布線層；連接於排列於包圍前述4列×n行個之前述接合部之外側之環狀2行之各前述接合部之前述布線係形成於異於前述第1布線層之第2布線層。
安裝基板上，連接於整齊配置成行列狀之接合部中之排列於內側之4列×n行個之各接合部之布線可藉由使連接於其內側之至少排列成2列×(n－2)行之各接合部之布線通過連接於排列在4列之外側各列之接合部之布線之間而形成於1個布線層(第1布線層)。又，連接於排列於包圍4列×n行個之接合部之外側之環狀2行之各接合部之布線係藉由使連接於排列在該環狀2行之內側之行之各接合部之布線通過連接於排列在外側之列之接合部之布線之間而形成於1個布線層(第2布線層)。
例如，接合部排列成8列×13行之行列狀之情形，連接於排列於內側之4列×9行之接合部之布線係形成於第1布線層，連接於排列於外側之環狀2行之接合部之布線係形成 於第2布線層。因此，形成連接於104個之接合部之布線用之布線層只要2層即可。如前所述，在以往之100接腳用之安裝基板中，至少需要3個布線層，故在本發明之安裝基板中，比以往之100接腳用之安裝基板更能減少布線層數。在多層布線構造之安裝基板中，布線層數愈多時成本愈高，故可藉由布線層數之減少而謀求安裝基板之成本之降低。
本發明之上述或其他目的、特徵及效果可由參照附圖之後述之實施型態之說明獲得更明確之瞭解。
以下，參照附圖詳細說明本發明之實施型態。
圖1係圖解地表示本發明之一實施型態之電子機器之構成之剖面圖。
電子機器100具有將表面安裝型之半導體裝置1表面安裝於安裝基板2之構成。
半導體裝置1係包含半導體晶片11、裝載半導體晶片11用之中介層12、及封閉半導體晶片11之封閉樹脂13。
半導體晶片11例如係包含連接於液晶顯示器用驅動器之時間控制電路。半導體晶片11之最表面被表面保護膜所覆蓋，在其周緣部，複數焊墊(未圖示)被設置成由表面保護膜露出之狀態。
中介層12係包含由絕緣性樹脂(例如玻璃環氧樹脂)構成之絕緣性基板14。
在絕緣性基板14之一方面(上面)，於其中央部形成在平 面視上具有比半導體晶片11稍大尺寸之矩形薄板狀之島部15。又，在絕緣性基板14之一方面，於包圍島部15之周緣部，形成複數之內部端子16。島部15及內部端子16例如係由銅等金屬所構成，具有導電性。
在島部15，例如隔著高熔點焊料(熔點260℃以上之焊料)構成之接合劑17，接合半導體晶片11之背面。又，各內部端子16例如係經由細金線構成之焊接線18連接於半導體晶片11之表面之各焊墊(連線焊接)。藉此，半導體晶片11可使其背面經由接合劑17電性連接於島部15，並使其內部電路(未圖示)經由焊接線18電性連接於內部端子16。
在絕緣性基板14之他方面(下面)，整齊配置複數之外部端子19。各外部端子19例如係利用焊料等金屬材料形成球狀。內部端子16與外部端子19係藉在厚度方向貫通絕緣性基板14之通路而被電性連接。此通路例如係形成貫通絕緣性基板14之通路孔，將金屬材料(例如銅)完全埋入此通路孔內所形成。
在安裝半導體裝置1之安裝基板(印刷布線基板)2上，對應於設置於半導體裝置1之外部端子19，配置有連接各外部端子19之接合部21。半導體裝置1係藉由將各外部端子19連接於安裝基板2上之各接合部21，達成對安裝基板2之表面安裝。絕緣性基板14之一方面上之內部端子16與他方面上之外部端子19係被電性連接，故將外部端子19連接於安裝基板2上之接合部21時，可達成接合部21與內部端子16之電性連接，進而可達成接合部21與半導體晶片11之電 性連接。
圖2係表示半導體裝置1之外部端子19之配置之圖(半導體裝置1之底面圖)。
在半導體裝置1(絕緣性基板14)之下面，104個外部端子19係整齊被配置成8列×13行之行列狀。換言之，104個外部端子19係被排列成4列×9行及包圍此之環狀2行。又，為簡化圖面，在圖2中，僅在一部分之外部端子19附上參照符號。
圖3係表示在安裝基板2之接合部21之配置之平面圖。
在安裝基板2之表面，對應於半導體裝置1之外部端子19，將104個接合部21整齊被配置成8列×13行之行列狀。又，為簡化圖面，在圖3中，僅在一部分之接合部21附上參照符號。
圖4係安裝基板2之剖面圖。
安裝基板2係由環氧樹脂等之樹脂材料所構成，包含形成基體之絕緣層22、積層於絕緣層22之一方面(表面)上之表側布線層23、及積層於絕緣層22之他方面(背面)上之背側布線層24。
圖5係表示表側布線層23之一部分之平面圖。
在表側布線層23，形成有104個接合部21、及連接於最外之環狀2行之接合部21(在圖3中附上影線表示)之布線25。
布線25係由銅等金屬所構成，連接於排列在外側之環狀1行之各接合部21之布線25係沿著列方向(圖5之紙面之左 右方向)或行方向(圖5之紙面之上下方向)延伸，而被引出至在安裝基板2之接合半導體裝置1之區域(以下僅稱為「接合區域」)外。又，連接於排列在內側之環狀1行之各接合部21之布線25係通過連接於排列在外側之環狀1行之各接合部21之布線25之間而被引出至接合區域外。而，各布線25係在接合區域外，連接於安裝基板2上之電源電路等。
如圖4及圖5所示，在絕緣層22中，對應於配置在構成最外之環狀2行之接合部21之內側之4列×9行個之各接合部21(在圖3中未附上影線表示)，形成貫通絕緣層22之厚度方向之通路26。此36個通路26係配置於分別對應之接合部21之附近之位置，藉以整齊被排列成例如4列×9行之行列狀。各通路26例如係形成貫通絕緣層22之通路孔，可藉將金屬材料(例如銅)完全埋入此通路孔內而形成。
在表側布線層23，形成連接4列×9行個之各接合部21與對應於此等各接合部21之通路26之連接布線27。連接布線27係由銅等金屬所構成。
圖6係表示背側布線層24之一部分之底面圖。
在背側布線層24，形成連接於各通路26之布線28。布線28係由銅等金屬所構成。連接於排列在4列×9行之外側各列之各通路26之布線28係由各通路26向外側沿著行方向(圖6之紙面之上下方向)延伸。連接於排列在4列×9行之內側2列之各通路26中之配置於列方向(圖6之紙面之左右方向)兩端之各通路26中之布線28係由各通路26向外側沿著 列方向延伸。又，連接於排列在內側2列×7行之各通路26之布線28係通過連接於排列在外側各列之各通路26之布線28之間而向外側延伸。而，各布線28係連接於安裝基板2上之電源電路等。
如以上所述，在半導體裝置1中，104個外部端子19被整齊配置成8列×13行之行列狀。另一方面，在安裝半導體裝置1之安裝基板2上，對應於104個外部端子19，104個接合部21被整齊排列成8列×13行之行列狀。而，與內側之4列×9行個之各接合部21電性連接之布線28係形成於背側布線層24，連接於排列於包圍該4列×9行個之各接合部21之環狀2行之各接合部21之布線25係形成於表側布線層23。即，連接於104個之各接合部21之布線25、28係被分開形成於表側布線層23、背側布線層24之2層。
在以往之100接腳用之安裝基板中，至少需要3個布線層，故安裝基板2比以往之該100接腳用之安裝基板更能減少布線層數。在多層布線構造之安裝基板中，布線層數愈多時成本愈高，故可藉由布線層數之減少而謀求安裝基板2之成本之降低。
又，本發明也可以其他型態實施。例如，在背側布線層24中，連接於排列在4列×9行之內側之2列之各通路26中之配置於列方向兩端之各通路26之布線28係由各通路26向外側沿著列方向延伸，但如圖6之虛線所示，也可向行方向被引出。
又，採取將半導體裝置1之外部端子19排列成4列×9行及 包圍此之環狀2行，對應於此，且將安裝基板2之接合部21排列成4列×9行及包圍此之環狀2行之構成。但，外部端子19及接合部21不限定於排列成4列×9行及包圍此之環狀2行，也可排列成4列×10行及包圍此之環狀2行等，排列成4列×n行(n：5以上之整數)及包圍此之環狀2行。另外，也可設置排列成包圍其外側之環狀之外部端子19及接合部21，此情形，需追加設置形成連接於接合部21之布線之布線層。
以上，雖已就本發明之實施型態予以詳細說明，但此等僅不過係用於說明本發明之技術的內容之具體例，但本發明不應被限定於此等具體例而作解釋，本發明之精神及範圍僅受到後附之申請專利範圍所限定。
本申請案對應於2007年2月7日向日本國特許廳提出之特願2007－27953號，該申請案之所有揭示可經由引用而納入於本案。
1‧‧‧半導體裝置
2‧‧‧安裝基板
19‧‧‧外部端子
21‧‧‧接合部(land)
22‧‧‧絕緣層
23‧‧‧表側布線層
24‧‧‧背側布線層
25‧‧‧布線
28‧‧‧布線
100‧‧‧電子機器
圖1係圖解地表示本發明之一實施型態之電子機器之構成之剖面圖。
圖2係表示半導體裝置之外部端子之配置之圖(半導體裝置之底面圖)。
圖3係表示在安裝基板之接合部之配置之平面圖。
圖4係安裝基板之剖面圖。
圖5係表示第1布線層之一部分之平面圖。
圖6係表示第2布線層之一部分之底面圖。
圖7係表示在以往之100接腳用之安裝基板之接合部之配置例之圖。
2‧‧‧安裝基板
21‧‧‧接合部
22‧‧‧絕緣層
23‧‧‧表側布線層
24‧‧‧背側布線層
25、28‧‧‧布線
26‧‧‧通路

Claims (2)

  1. 一種安裝基板，其係安裝具有整齊排列成行列狀之外部端子之半導體裝置者，且包含：接合部，其係排列於前述半導體裝置所對向之表面，並接合各前述外部端子；及布線，其係被連接於各前述接合部，且被引出至接合前述半導體裝置之區域外；連接於排列於內側之4列×n行(n：5以上之整數)個之各前述接合部之前述布線係形成於第1布線層；連接於排列於包圍前述4列×n行個之前述接合部之外側之環狀2行之各前述接合部之前述布線係形成於異於前述第1布線層之第2布線層。
  2. 一種電子機器，其係包含安裝基板、與具有整齊排列成行列狀之外部端子，且被表面安裝於前述安裝基板之半導體裝置者；前述安裝基板係包含：接合部，其係排列於前述半導體裝置所對向之表面，並接合各前述外部端子；及布線，其係被連接於各前述接合部，且被引出至接合前述半導體裝置之區域外；連接於排列於內側之4列×n行(n：5以上之整數)個之各前述接合部之前述布線係形成於第1布線層；連接於排列於包圍前述4列×n行個之前述接合部之外側之環狀2行之各前述接合部之前述布線係形成於異於前述第1布線層之第2布線層。
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JP3462385B2 (ja) 1998-03-11 2003-11-05 新光電気工業株式会社 多層回路基板
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